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path: root/linux-core/via_dmablit.c
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/* via_dmablit.c -- PCI DMA BitBlt support for the VIA Unichrome/Pro
 * 
 * Copyright (C) 2005 Thomas Hellstrom, All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: 
 *    Thomas Hellstrom.
 *    Partially based on code obtained from Digeo Inc.
 */


/*
 * Unmaps the DMA mappings. 
 * FIXME: Is this a NoOp on x86? Also 
 * FIXME: What happens if this one is called and a pending blit has previously done 
 * the same DMA mappings? 
 */

#include "drmP.h"
#include "via_drm.h"
#include "via_drv.h"
#include "via_dmablit.h"

#include <linux/pagemap.h>

#define VIA_PGDN(x)             (((unsigned long)(x)) & PAGE_MASK)
#define VIA_PGOFF(x)            (((unsigned long)(x)) & ~PAGE_MASK)
#define VIA_PFN(x)              ((unsigned long)(x) >> PAGE_SHIFT)

typedef struct _drm_via_descriptor {
	uint32_t mem_addr;
	uint32_t dev_addr;
	uint32_t size;
	uint32_t next;
} drm_via_descriptor_t;


/*
 * Unmap a DMA mapping.
 */



static void
via_unmap_blit_from_device(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
{
	int num_desc = vsg->num_desc;
	unsigned cur_descriptor_page = num_desc / vsg->descriptors_per_page;
	unsigned descriptor_this_page = num_desc % vsg->descriptors_per_page;
	drm_via_descriptor_t *desc_ptr = vsg->desc_pages[cur_descriptor_page] + 
		descriptor_this_page;
	dma_addr_t next = vsg->chain_start;

	while(num_desc--) {
		if (descriptor_this_page-- == 0) {
			cur_descriptor_page--;
			descriptor_this_page = vsg->descriptors_per_page - 1;
			desc_ptr = vsg->desc_pages[cur_descriptor_page] + 
				descriptor_this_page;
		}
		dma_unmap_single(&pdev->dev, next, sizeof(*desc_ptr), DMA_TO_DEVICE);
		dma_unmap_page(&pdev->dev, desc_ptr->mem_addr, desc_ptr->size, vsg->direction);
		next = (dma_addr_t) desc_ptr->next;
		desc_ptr--;
	}
}

/*
 * If mode = 0, count how many descriptors are needed.
 * If mode = 1, Map the DMA pages for the device, put together and map also the descriptors.
 * Descriptors are run in reverse order by the hardware because we are not allowed to update the
 * 'next' field without syncing calls when the descriptor is already mapped.
 */

static void
via_map_blit_for_device(struct pci_dev *pdev,
		   const drm_via_dmablit_t *xfer,
		   drm_via_sg_info_t *vsg, 
		   int mode)
{
	unsigned cur_descriptor_page = 0;
	unsigned num_descriptors_this_page = 0;
	unsigned char *mem_addr = xfer->mem_addr;
	unsigned char *cur_mem;
	unsigned char *first_addr = (unsigned char *)VIA_PGDN(mem_addr);
	uint32_t fb_addr = xfer->fb_addr;
	uint32_t cur_fb;
	unsigned long line_len;
	unsigned remaining_len;
	int num_desc = 0;
	int cur_line;
	dma_addr_t next = 0 | VIA_DMA_DPR_EC;
	drm_via_descriptor_t *desc_ptr = NULL;

	if (mode == 1) 
		desc_ptr = vsg->desc_pages[cur_descriptor_page];

	for (cur_line = 0; cur_line < xfer->num_lines; ++cur_line) {

		line_len = xfer->line_length;
		cur_fb = fb_addr;
		cur_mem = mem_addr;
		
		while (line_len > 0) {

			remaining_len = min(PAGE_SIZE-VIA_PGOFF(cur_mem), line_len);
			line_len -= remaining_len;

			if (mode == 1) {
				desc_ptr->mem_addr = dma_map_page(&pdev->dev,
					vsg->pages[VIA_PFN(cur_mem) -
					VIA_PFN(first_addr)],
					VIA_PGOFF(cur_mem), remaining_len,
					vsg->direction);
				desc_ptr->dev_addr = cur_fb;
				
				desc_ptr->size = remaining_len;
				desc_ptr->next = (uint32_t) next;
				next = dma_map_single(&pdev->dev, desc_ptr, sizeof(*desc_ptr), 
						      DMA_TO_DEVICE);
				desc_ptr++;
				if (++num_descriptors_this_page >= vsg->descriptors_per_page) {
					num_descriptors_this_page = 0;
					desc_ptr = vsg->desc_pages[++cur_descriptor_page];
				}
			}
			
			num_desc++;
			cur_mem += remaining_len;
			cur_fb += remaining_len;
		}
		
		mem_addr += xfer->mem_stride;
		fb_addr += xfer->fb_stride;
	}

	if (mode == 1) {
		vsg->chain_start = next;
		vsg->state = dr_via_device_mapped;
	}
	vsg->num_desc = num_desc;
}

/*
 * Function that frees up all resources for a blit. It is usable even if the 
 * blit info has only been partially built as long as the status enum is consistent
 * with the actual status of the used resources.
 */


static void
via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg) 
{
	struct page *page;
	int i;

	switch(vsg->state) {
	case dr_via_device_mapped:
		via_unmap_blit_from_device(pdev, vsg);
	case dr_via_desc_pages_alloc:
		for (i=0; i<vsg->num_desc_pages; ++i) {
			if (vsg->desc_pages[i] != NULL)
			  free_page((unsigned long)vsg->desc_pages[i]);
		}
		kfree(vsg->desc_pages);
	case dr_via_pages_locked:
		for (i=0; i<vsg->num_pages; ++i) {
			if ( NULL != (page = vsg->pages[i])) {
				if (! PageReserved(page) && (DMA_FROM_DEVICE == vsg->direction)) 
					SetPageDirty(page);
				page_cache_release(page);
			}
		}
	case dr_via_pages_alloc:
		vfree(vsg->pages);
	default:
		vsg->state = dr_via_sg_init;
	}
	if (vsg->bounce_buffer) {
		vfree(vsg->bounce_buffer);
		vsg->bounce_buffer = NULL;
	}
	vsg->free_on_sequence = 0;
}		

/*
 * Fire a blit engine.
 */

static void
via_fire_dmablit(struct drm_device *dev, drm_via_sg_info_t *vsg, int engine)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;

	VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0);
	VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0);
	VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | 
		  VIA_DMA_CSR_DE);
	VIA_WRITE(VIA_PCI_DMA_MR0  + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
	VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0);
	VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
	DRM_WRITEMEMORYBARRIER();
	VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
	VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04);
}

/*
 * Obtain a page pointer array and lock all pages into system memory. A segmentation violation will
 * occur here if the calling user does not have access to the submitted address.
 */

static int
via_lock_all_dma_pages(drm_via_sg_info_t *vsg,  drm_via_dmablit_t *xfer)
{
	int ret;
	unsigned long first_pfn = VIA_PFN(xfer->mem_addr);
	vsg->num_pages = VIA_PFN(xfer->mem_addr + (xfer->num_lines * xfer->mem_stride -1)) - 
		first_pfn + 1;
	
	if (NULL == (vsg->pages = vmalloc(sizeof(struct page *) * vsg->num_pages)))
		return -ENOMEM;
	memset(vsg->pages, 0, sizeof(struct page *) * vsg->num_pages);
	down_read(&current->mm->mmap_sem);
	ret = get_user_pages(current, current->mm, (unsigned long) xfer->mem_addr,
			     vsg->num_pages, (vsg->direction == DMA_FROM_DEVICE), 
			     0, vsg->pages, NULL);

	up_read(&current->mm->mmap_sem);
	if (ret != vsg->num_pages) {
		if (ret < 0) 
			return ret;
		vsg->state = dr_via_pages_locked;
		return -EINVAL;
	}
	vsg->state = dr_via_pages_locked;
	DRM_DEBUG("DMA pages locked\n");
	return 0;
}

/*
 * Allocate DMA capable memory for the blit descriptor chain, and an array that keeps track of the
 * pages we allocate. We don't want to use kmalloc for the descriptor chain because it may be
 * quite large for some blits, and pages don't need to be contingous.
 */

static int 
via_alloc_desc_pages(drm_via_sg_info_t *vsg)
{
	int i;
	
	vsg->descriptors_per_page = PAGE_SIZE / sizeof( drm_via_descriptor_t);
	vsg->num_desc_pages = (vsg->num_desc + vsg->descriptors_per_page - 1) / 
		vsg->descriptors_per_page;

	if (NULL ==  (vsg->desc_pages = kmalloc(sizeof(void *) * vsg->num_desc_pages, GFP_KERNEL))) 
		return -ENOMEM;
	
	memset(vsg->desc_pages, 0, sizeof(void *) * vsg->num_desc_pages);
	vsg->state = dr_via_desc_pages_alloc;
	for (i=0; i<vsg->num_desc_pages; ++i) {
		if (NULL == (vsg->desc_pages[i] = 
			     (drm_via_descriptor_t *) __get_free_page(GFP_KERNEL)))
			return -ENOMEM;
	}
	DRM_DEBUG("Allocated %d pages for %d descriptors.\n", vsg->num_desc_pages,
		  vsg->num_desc);
	return 0;
}
			
static void
via_abort_dmablit(struct drm_device *dev, int engine)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;

	VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA);
}

static void
via_dmablit_engine_off(struct drm_device *dev, int engine)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;

	VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); 
}



/*
 * The dmablit part of the IRQ handler. Trying to do only reasonably fast things here.
 * The rest, like unmapping and freeing memory for done blits is done in a separate workqueue
 * task. Basically the task of the interrupt handler is to submit a new blit to the engine, while
 * the workqueue task takes care of processing associated with the old blit.
 */
		
void
via_dmablit_handler(struct drm_device *dev, int engine, int from_irq)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
	drm_via_blitq_t *blitq = dev_priv->blit_queues + engine;
	int cur;
	int done_transfer;
	unsigned long irqsave=0;
	uint32_t status = 0;

	DRM_DEBUG("DMA blit handler called. engine = %d, from_irq = %d, blitq = 0x%lx\n",
		  engine, from_irq, (unsigned long) blitq);

	if (from_irq) {
		spin_lock(&blitq->blit_lock);
	} else {
		spin_lock_irqsave(&blitq->blit_lock, irqsave);
	}

	done_transfer = blitq->is_active && 
	  (( status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
	done_transfer = done_transfer || ( blitq->aborting && !(status & VIA_DMA_CSR_DE)); 

	cur = blitq->cur;
	if (done_transfer) {

		blitq->blits[cur]->aborted = blitq->aborting;
		blitq->done_blit_handle++;
		DRM_WAKEUP(blitq->blit_queue + cur);		

		cur++;
		if (cur >= VIA_NUM_BLIT_SLOTS) 
			cur = 0;
		blitq->cur = cur;

		/*
		 * Clear transfer done flag.
		 */

		VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04,  VIA_DMA_CSR_TD);

		blitq->is_active = 0;
		blitq->aborting = 0;
		schedule_work(&blitq->wq);	

	} else if (blitq->is_active && time_after_eq(jiffies, blitq->end)) {

		/*
		 * Abort transfer after one second.
		 */

		via_abort_dmablit(dev, engine);
		blitq->aborting = 1;
		blitq->end = jiffies + DRM_HZ;
	}
	  		
	if (!blitq->is_active) {
		if (blitq->num_outstanding) {
			via_fire_dmablit(dev, blitq->blits[cur], engine);
			blitq->is_active = 1;
			blitq->cur = cur;
			blitq->num_outstanding--;
			blitq->end = jiffies + DRM_HZ;
			if (!timer_pending(&blitq->poll_timer)) {
				blitq->poll_timer.expires = jiffies+1;
				add_timer(&blitq->poll_timer);
			}
		} else {
			if (timer_pending(&blitq->poll_timer)) {
				del_timer(&blitq->poll_timer);
			}
			via_dmablit_engine_off(dev, engine);
		}
	}		

	if (from_irq) {
		spin_unlock(&blitq->blit_lock);
	} else {
		spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
	}
} 



/*
 * Check whether this blit is still active, performing necessary locking.
 */

static int
via_dmablit_active(drm_via_blitq_t *blitq, int engine, uint32_t handle, wait_queue_head_t **queue)
{
	unsigned long irqsave;
	uint32_t slot;
	int active;

	spin_lock_irqsave(&blitq->blit_lock, irqsave);

	/*
	 * Allow for handle wraparounds.
	 */

	active = ((blitq->done_blit_handle - handle) > (1 << 23)) &&
		((blitq->cur_blit_handle - handle) <= (1 << 23));

	if (queue && active) {
		slot = handle - blitq->done_blit_handle + blitq->cur -1;
		if (slot >= VIA_NUM_BLIT_SLOTS) {
			slot -= VIA_NUM_BLIT_SLOTS;
		}
		*queue = blitq->blit_queue + slot;
	}

	spin_unlock_irqrestore(&blitq->blit_lock, irqsave);

	return active;
}
	
/*
 * Sync. Wait for at least three seconds for the blit to be performed.
 */

static int
via_dmablit_sync(struct drm_device *dev, uint32_t handle, int engine) 
{

	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
	drm_via_blitq_t *blitq = dev_priv->blit_queues + engine;
	wait_queue_head_t *queue;
	int ret = 0;

	if (via_dmablit_active(blitq, engine, handle, &queue)) {
		DRM_WAIT_ON(ret, *queue, 3 * DRM_HZ, 
			    !via_dmablit_active(blitq, engine, handle, NULL));
	}
	DRM_DEBUG("DMA blit sync handle 0x%x engine %d returned %d\n",
		  handle, engine, ret);
	
	return ret;
}


/*
 * A timer that regularly polls the blit engine in cases where we don't have interrupts:
 * a) Broken hardware (typically those that don't have any video capture facility).
 * b) Blit abort. The hardware doesn't send an interrupt when a blit is aborted.
 * The timer and hardware IRQ's can and do work in parallel. If the hardware has
 * irqs, it will shorten the latency somewhat.
 */



static void
via_dmablit_timer(unsigned long data)
{
	drm_via_blitq_t *blitq = (drm_via_blitq_t *) data;
	struct drm_device *dev = blitq->dev;
	int engine = (int)
		(blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues);
		
	DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine, 
		  (unsigned long) jiffies);

	via_dmablit_handler(dev, engine, 0);
	
	if (!timer_pending(&blitq->poll_timer)) {
		blitq->poll_timer.expires = jiffies+1;
		add_timer(&blitq->poll_timer);

		/*
		 * Rerun handler to delete timer if engines are off, and
		 * to shorten abort latency. This is a little nasty.
		 */

		via_dmablit_handler(dev, engine, 0);
	}
}




/*
 * Workqueue task that frees data and mappings associated with a blit.
 * Also wakes up waiting processes. Each of these tasks handles one
 * blit engine only and may not be called on each interrupt.
 */


static void 
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
via_dmablit_workqueue(void *data)
#else
via_dmablit_workqueue(struct work_struct *work)
#endif
{
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
	drm_via_blitq_t *blitq = (drm_via_blitq_t *) data;
#else
	drm_via_blitq_t *blitq = container_of(work, drm_via_blitq_t, wq);
#endif
        struct drm_device *dev = blitq->dev;
	unsigned long irqsave;
	drm_via_sg_info_t *cur_sg;
	int cur_released;
	
	
	DRM_DEBUG("Workqueue task called for blit engine %ld\n",(unsigned long) 
		  (blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues));

	spin_lock_irqsave(&blitq->blit_lock, irqsave);
	
	while(blitq->serviced != blitq->cur) {

		cur_released = blitq->serviced++;

		DRM_DEBUG("Releasing blit slot %d\n", cur_released);

		if (blitq->serviced >= VIA_NUM_BLIT_SLOTS) 
			blitq->serviced = 0;
		
		cur_sg = blitq->blits[cur_released];
		blitq->num_free++;
				
		spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
		
		DRM_WAKEUP(&blitq->busy_queue);
		
		via_free_sg_info(dev->pdev, cur_sg);
		kfree(cur_sg);
		
		spin_lock_irqsave(&blitq->blit_lock, irqsave);
	}

	spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
}
	

/*
 * Init all blit engines. Currently we use two, but some hardware have 4.
 */


void
via_init_dmablit(struct drm_device *dev)
{
	int i,j;
	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
	drm_via_blitq_t *blitq;

	pci_set_master(dev->pdev);	
	
	for (i=0; i< VIA_NUM_BLIT_ENGINES; ++i) {
		blitq = dev_priv->blit_queues + i;
		blitq->dev = dev;
		blitq->cur_blit_handle = 0;
		blitq->done_blit_handle = 0;
		blitq->head = 0;
		blitq->cur = 0;
		blitq->serviced = 0;
		blitq->num_free = VIA_NUM_BLIT_SLOTS - 1;
		blitq->num_outstanding = 0;
		blitq->is_active = 0;
		blitq->aborting = 0;
		spin_lock_init(&blitq->blit_lock);
		for (j=0; j<VIA_NUM_BLIT_SLOTS; ++j) {
			DRM_INIT_WAITQUEUE(blitq->blit_queue + j);
		}
		DRM_INIT_WAITQUEUE(&blitq->busy_queue);
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
		INIT_WORK(&blitq->wq, via_dmablit_workqueue, blitq);
#else
		INIT_WORK(&blitq->wq, via_dmablit_workqueue);
#endif
		init_timer(&blitq->poll_timer);
		blitq->poll_timer.function = &via_dmablit_timer;
		blitq->poll_timer.data = (unsigned long) blitq;
	}	
}

/*
 * Build all info and do all mappings required for a blit.
 */
		

static int
via_build_sg_info(struct drm_device *dev, drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer)
{
	int draw = xfer->to_fb;
	int ret = 0;
	
	vsg->direction = (draw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
	vsg->bounce_buffer = NULL;

	vsg->state = dr_via_sg_init;

	if (xfer->num_lines <= 0 || xfer->line_length <= 0) {
		DRM_ERROR("Zero size bitblt.\n");
		return -EINVAL;
	}

	/*
	 * Below check is a driver limitation, not a hardware one. We
	 * don't want to lock unused pages, and don't want to incoporate the
	 * extra logic of avoiding them. Make sure there are no. 
	 * (Not a big limitation anyway.)
	 */

	if ((xfer->mem_stride - xfer->line_length) >= PAGE_SIZE) {
		DRM_ERROR("Too large system memory stride. Stride: %d, "
			  "Length: %d\n", xfer->mem_stride, xfer->line_length);
		return -EINVAL;
	}

	if ((xfer->mem_stride == xfer->line_length) &&
	    (xfer->fb_stride == xfer->line_length)) {
		xfer->mem_stride *= xfer->num_lines;
		xfer->line_length = xfer->mem_stride;
		xfer->fb_stride = xfer->mem_stride;
		xfer->num_lines = 1;
	}

	/*
	 * Don't lock an arbitrary large number of pages, since that causes a
	 * DOS security hole.
	 */

	if (xfer->num_lines > 2048 || (xfer->num_lines*xfer->mem_stride > (2048*2048*4))) {
		DRM_ERROR("Too large PCI DMA bitblt.\n");
		return -EINVAL;
	}		

	/* 
	 * we allow a negative fb stride to allow flipping of images in
	 * transfer. 
	 */

	if (xfer->mem_stride < xfer->line_length ||
	    abs(xfer->fb_stride) < xfer->line_length) {
		DRM_ERROR("Invalid frame-buffer / memory stride.\n");
		return -EINVAL;
	}

	/*
	 * A hardware bug seems to be worked around if system memory addresses start on
	 * 16 byte boundaries. This seems a bit restrictive however. VIA is contacted
	 * about this. Meanwhile, impose the following restrictions:
	 */

#ifdef VIA_BUGFREE
	if ((((unsigned long)xfer->mem_addr & 3) != ((unsigned long)xfer->fb_addr & 3)) ||
	    ((xfer->num_lines > 1) && ((xfer->mem_stride & 3) != (xfer->fb_stride & 3)))) {
		DRM_ERROR("Invalid DRM bitblt alignment.\n");
		return -EINVAL;
	}
#else
	if ((((unsigned long)xfer->mem_addr & 15) || ((unsigned long)xfer->fb_addr & 3)) ||
	    ((xfer->num_lines > 1) && ((xfer->mem_stride & 15) || (xfer->fb_stride & 3)))) {
		DRM_ERROR("Invalid DRM bitblt alignment.\n");
		return -EINVAL;
	}	
#endif

	if (0 != (ret = via_lock_all_dma_pages(vsg, xfer))) {
		DRM_ERROR("Could not lock DMA pages.\n");
		via_free_sg_info(dev->pdev, vsg);
		return ret;
	}

	via_map_blit_for_device(dev->pdev, xfer, vsg, 0);
	if (0 != (ret = via_alloc_desc_pages(vsg))) {
		DRM_ERROR("Could not allocate DMA descriptor pages.\n");
		via_free_sg_info(dev->pdev, vsg);
		return ret;
	}
	via_map_blit_for_device(dev->pdev, xfer, vsg, 1);
	
	return 0;
}
	

/*
 * Reserve one free slot in the blit queue. Will wait for one second for one
 * to become available. Otherwise -EBUSY is returned.
 */

static int 
via_dmablit_grab_slot(drm_via_blitq_t *blitq, int engine)
{
	int ret=0;
	unsigned long irqsave;

	DRM_DEBUG("Num free is %d\n", blitq->num_free);
	spin_lock_irqsave(&blitq->blit_lock, irqsave);
	while(blitq->num_free == 0) {
		spin_unlock_irqrestore(&blitq->blit_lock, irqsave);

		DRM_WAIT_ON(ret, blitq->busy_queue, DRM_HZ, blitq->num_free > 0);
		if (ret) {
			return (-EINTR == ret) ? -EAGAIN : ret;
		}
		
		spin_lock_irqsave(&blitq->blit_lock, irqsave);
	}
	
	blitq->num_free--;
	spin_unlock_irqrestore(&blitq->blit_lock, irqsave);

	return 0;
}

/*
 * Hand back a free slot if we changed our mind.
 */

static void 
via_dmablit_release_slot(drm_via_blitq_t *blitq)
{
	unsigned long irqsave;

	spin_lock_irqsave(&blitq->blit_lock, irqsave);
	blitq->num_free++;
	spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
	DRM_WAKEUP( &blitq->busy_queue );
}

/*
 * Grab a free slot. Build blit info and queue a blit.
 */


static int 
via_dmablit(struct drm_device *dev, drm_via_dmablit_t *xfer)	 
{
	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
	drm_via_sg_info_t *vsg;
	drm_via_blitq_t *blitq;
	int ret;
	int engine;
	unsigned long irqsave;

	if (dev_priv == NULL) {
		DRM_ERROR("Called without initialization.\n");
		return -EINVAL;
	}

	engine = (xfer->to_fb) ? 0 : 1;
	blitq = dev_priv->blit_queues + engine;
	if (0 != (ret = via_dmablit_grab_slot(blitq, engine))) {
		return ret;
	}
	if (NULL == (vsg = kmalloc(sizeof(*vsg), GFP_KERNEL))) {
		via_dmablit_release_slot(blitq);
		return -ENOMEM;
	}
	if (0 != (ret = via_build_sg_info(dev, vsg, xfer))) {
		via_dmablit_release_slot(blitq);
		kfree(vsg);
		return ret;
	}
	spin_lock_irqsave(&blitq->blit_lock, irqsave);

	blitq->blits[blitq->head++] = vsg;
	if (blitq->head >= VIA_NUM_BLIT_SLOTS) 
		blitq->head = 0;
	blitq->num_outstanding++;
	xfer->sync.sync_handle = ++blitq->cur_blit_handle; 

	spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
	xfer->sync.engine = engine;

       	via_dmablit_handler(dev, engine, 0);

	return 0;
}

/*
 * Sync on a previously submitted blit. Note that the X server use signals extensively, and
 * that there is a very big probability that this IOCTL will be interrupted by a signal. In that
 * case it returns with -EAGAIN for the signal to be delivered. 
 * The caller should then reissue the IOCTL. This is similar to what is being done for drmGetLock().
 */

int
via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv )
{
	drm_via_blitsync_t *sync = data;
	int err;

	if (sync->engine >= VIA_NUM_BLIT_ENGINES) 
		return -EINVAL;

	err = via_dmablit_sync(dev, sync->sync_handle, sync->engine);

	if (-EINTR == err)
		err = -EAGAIN;

	return err;
}
	

/*
 * Queue a blit and hand back a handle to be used for sync. This IOCTL may be interrupted by a signal
 * while waiting for a free slot in the blit queue. In that case it returns with -EAGAIN and should 
 * be reissued. See the above IOCTL code.
 */

int 
via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv )
{
	drm_via_dmablit_t *xfer = data;
	int err;

	err = via_dmablit(dev, xfer);

	return err;
}
hl opt">; reg = reg & 0xffff; reg = MMSELECT(reg); while (count && used) { if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 || (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 && addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || addr >= GETBUFADDR(buf) + buf->used - MACH64_DUMP_CONTEXT * 4) { DRM_INFO("%08x: 0x%04x = 0x%08x\n", addr, reg, le32_to_cpu(*p)); skipped = 0; } else { if (!skipped) { DRM_INFO(" ...\n"); skipped = 1; } } p++; addr += 4; used--; reg += 4; count--; } } DRM_INFO("\n"); } /** * Dump the ring state and contents, including the contents of the buffer being * processed by the graphics engine. */ void mach64_dump_ring_info(drm_mach64_private_t *dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; int i, skipped; DRM_INFO("\n"); DRM_INFO("ring contents:\n"); DRM_INFO(" head_addr: 0x%08x head: %u tail: %u\n\n", ring->head_addr, ring->head, ring->tail); skipped = 0; for (i = 0; i < ring->size / sizeof(u32); i += 4) { if (i <= MACH64_DUMP_CONTEXT * 4 || i >= ring->size / sizeof(u32) - MACH64_DUMP_CONTEXT * 4 || (i >= ring->tail - MACH64_DUMP_CONTEXT * 4 && i <= ring->tail + MACH64_DUMP_CONTEXT * 4) || (i >= ring->head - MACH64_DUMP_CONTEXT * 4 && i <= ring->head + MACH64_DUMP_CONTEXT * 4)) { DRM_INFO(" 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x%s%s\n", (u32)(ring->start_addr + i * sizeof(u32)), le32_to_cpu(((u32 *) ring->start)[i + 0]), le32_to_cpu(((u32 *) ring->start)[i + 1]), le32_to_cpu(((u32 *) ring->start)[i + 2]), le32_to_cpu(((u32 *) ring->start)[i + 3]), i == ring->head ? " (head)" : "", i == ring->tail ? " (tail)" : ""); skipped = 0; } else { if (!skipped) { DRM_INFO(" ...\n"); skipped = 1; } } } DRM_INFO("\n"); if (ring->head >= 0 && ring->head < ring->size / sizeof(u32)) { struct list_head *ptr; u32 addr = le32_to_cpu(((u32 *) ring->start)[ring->head + 1]); list_for_each(ptr, &dev_priv->pending) { drm_mach64_freelist_t *entry = list_entry(ptr, drm_mach64_freelist_t, list); struct drm_buf *buf = entry->buf; u32 buf_addr = GETBUFADDR(buf); if (buf_addr <= addr && addr < buf_addr + buf->used) mach64_dump_buf_info(dev_priv, buf); } } DRM_INFO("\n"); DRM_INFO(" BM_GUI_TABLE = 0x%08x\n", MACH64_READ(MACH64_BM_GUI_TABLE)); DRM_INFO("\n"); DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n", MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET)); DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n", MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR)); DRM_INFO(" BM_COMMAND = 0x%08x\n", MACH64_READ(MACH64_BM_COMMAND)); DRM_INFO("\n"); DRM_INFO(" BM_STATUS = 0x%08x\n", MACH64_READ(MACH64_BM_STATUS)); DRM_INFO(" BUS_CNTL = 0x%08x\n", MACH64_READ(MACH64_BUS_CNTL)); DRM_INFO(" FIFO_STAT = 0x%08x\n", MACH64_READ(MACH64_FIFO_STAT)); DRM_INFO(" GUI_STAT = 0x%08x\n", MACH64_READ(MACH64_GUI_STAT)); DRM_INFO(" SRC_CNTL = 0x%08x\n", MACH64_READ(MACH64_SRC_CNTL)); } /*@}*/ /*******************************************************************/ /** \name DMA descriptor ring macros */ /*@{*/ /** * Add the end mark to the ring's new tail position. * * The bus master engine will keep processing the DMA buffers listed in the ring * until it finds this mark, making it stop. * * \sa mach64_clear_dma_eol */ static __inline__ void mach64_set_dma_eol(volatile u32 *addr) { #if defined(__i386__) int nr = 31; /* Taken from include/asm-i386/bitops.h linux header */ __asm__ __volatile__("lock;" "btsl %1,%0":"=m"(*addr) :"Ir"(nr)); #elif defined(__powerpc__) u32 old; u32 mask = cpu_to_le32(MACH64_DMA_EOL); /* Taken from the include/asm-ppc/bitops.h linux header */ __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ or %0,%0,%2 \n\ stwcx. %0,0,%3 \n\ bne- 1b":"=&r"(old), "=m"(*addr) :"r"(mask), "r"(addr), "m"(*addr) :"cc"); #elif defined(__alpha__) u32 temp; u32 mask = MACH64_DMA_EOL; /* Taken from the include/asm-alpha/bitops.h linux header */ __asm__ __volatile__("1: ldl_l %0,%3\n" " bis %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous":"=&r"(temp), "=m"(*addr) :"Ir"(mask), "m"(*addr)); #else u32 mask = cpu_to_le32(MACH64_DMA_EOL); *addr |= mask; #endif } /** * Remove the end mark from the ring's old tail position. * * It should be called after calling mach64_set_dma_eol to mark the ring's new * tail position. * * We update the end marks while the bus master engine is in operation. Since * the bus master engine may potentially be reading from the same position * that we write, we must change atomically to avoid having intermediary bad * data. */ static __inline__ void mach64_clear_dma_eol(volatile u32 *addr) { #if defined(__i386__) int nr = 31; /* Taken from include/asm-i386/bitops.h linux header */ __asm__ __volatile__("lock;" "btrl %1,%0":"=m"(*addr) :"Ir"(nr)); #elif defined(__powerpc__) u32 old; u32 mask = cpu_to_le32(MACH64_DMA_EOL); /* Taken from the include/asm-ppc/bitops.h linux header */ __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ andc %0,%0,%2 \n\ stwcx. %0,0,%3 \n\ bne- 1b":"=&r"(old), "=m"(*addr) :"r"(mask), "r"(addr), "m"(*addr) :"cc"); #elif defined(__alpha__) u32 temp; u32 mask = ~MACH64_DMA_EOL; /* Taken from the include/asm-alpha/bitops.h linux header */ __asm__ __volatile__("1: ldl_l %0,%3\n" " and %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous":"=&r"(temp), "=m"(*addr) :"Ir"(mask), "m"(*addr)); #else u32 mask = cpu_to_le32(~MACH64_DMA_EOL); *addr &= mask; #endif } #define RING_LOCALS \ int _ring_tail, _ring_write; unsigned int _ring_mask; volatile u32 *_ring #define RING_WRITE_OFS _ring_write #define BEGIN_RING(n) \ do { \ if (MACH64_VERBOSE) { \ DRM_INFO( "BEGIN_RING( %d ) \n", \ (n) ); \ } \ if (dev_priv->ring.space <= (n) * sizeof(u32)) { \ int ret; \ if ((ret = mach64_wait_ring( dev_priv, (n) * sizeof(u32))) < 0 ) { \ DRM_ERROR( "wait_ring failed, resetting engine\n"); \ mach64_dump_engine_info( dev_priv ); \ mach64_do_engine_reset( dev_priv ); \ return ret; \ } \ } \ dev_priv->ring.space -= (n) * sizeof(u32); \ _ring = (u32 *) dev_priv->ring.start; \ _ring_tail = _ring_write = dev_priv->ring.tail; \ _ring_mask = dev_priv->ring.tail_mask; \ } while (0) #define OUT_RING( x ) \ do { \ if (MACH64_VERBOSE) { \ DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ (unsigned int)(x), _ring_write ); \ } \ _ring[_ring_write++] = cpu_to_le32( x ); \ _ring_write &= _ring_mask; \ } while (0) #define ADVANCE_RING() \ do { \ if (MACH64_VERBOSE) { \ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ _ring_write, _ring_tail ); \ } \ DRM_MEMORYBARRIER(); \ mach64_clear_dma_eol( &_ring[(_ring_tail - 2) & _ring_mask] ); \ DRM_MEMORYBARRIER(); \ dev_priv->ring.tail = _ring_write; \ mach64_ring_tick( dev_priv, &(dev_priv)->ring ); \ } while (0) /** * Queue a DMA buffer of registers writes into the ring buffer. */ int mach64_add_buf_to_ring(drm_mach64_private_t *dev_priv, drm_mach64_freelist_t *entry) { int bytes, pages, remainder; u32 address, page; int i; struct drm_buf *buf = entry->buf; RING_LOCALS; bytes = buf->used; address = GETBUFADDR( buf ); pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; BEGIN_RING( pages * 4 ); for ( i = 0 ; i < pages-1 ; i++ ) { page = address + i * MACH64_DMA_CHUNKSIZE; OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); OUT_RING( page ); OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); OUT_RING( 0 ); } /* generate the final descriptor for any remaining commands in this buffer */ page = address + i * MACH64_DMA_CHUNKSIZE; remainder = bytes - i * MACH64_DMA_CHUNKSIZE; /* Save dword offset of last descriptor for this buffer. * This is needed to check for completion of the buffer in freelist_get */ entry->ring_ofs = RING_WRITE_OFS; OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); OUT_RING( page ); OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); OUT_RING( 0 ); ADVANCE_RING(); return 0; } /** * Queue DMA buffer controlling host data tranfers (e.g., blit). * * Almost identical to mach64_add_buf_to_ring. */ int mach64_add_hostdata_buf_to_ring(drm_mach64_private_t *dev_priv, drm_mach64_freelist_t *entry) { int bytes, pages, remainder; u32 address, page; int i; struct drm_buf *buf = entry->buf; RING_LOCALS; bytes = buf->used - MACH64_HOSTDATA_BLIT_OFFSET; pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; address = GETBUFADDR( buf ); BEGIN_RING( 4 + pages * 4 ); OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); OUT_RING( address ); OUT_RING( MACH64_HOSTDATA_BLIT_OFFSET | MACH64_DMA_HOLD_OFFSET ); OUT_RING( 0 ); address += MACH64_HOSTDATA_BLIT_OFFSET; for ( i = 0 ; i < pages-1 ; i++ ) { page = address + i * MACH64_DMA_CHUNKSIZE; OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); OUT_RING( page ); OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); OUT_RING( 0 ); } /* generate the final descriptor for any remaining commands in this buffer */ page = address + i * MACH64_DMA_CHUNKSIZE; remainder = bytes - i * MACH64_DMA_CHUNKSIZE; /* Save dword offset of last descriptor for this buffer. * This is needed to check for completion of the buffer in freelist_get */ entry->ring_ofs = RING_WRITE_OFS; OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); OUT_RING( page ); OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); OUT_RING( 0 ); ADVANCE_RING(); return 0; } /*@}*/ /*******************************************************************/ /** \name DMA test and initialization */ /*@{*/ /** * Perform a simple DMA operation using the pattern registers to test whether * DMA works. * * \return zero if successful. * * \note This function was the testbed for many experiences regarding Mach64 * DMA operation. It is left here since it so tricky to get DMA operating * properly in some architectures and hardware. */ static int mach64_bm_dma_test(struct drm_device * dev) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_dma_handle_t *cpu_addr_dmah; u32 data_addr; u32 *table, *data; u32 expected[2]; u32 src_cntl, pat_reg0, pat_reg1; int i, count, failed; DRM_DEBUG("\n"); table = (u32 *) dev_priv->ring.start; /* FIXME: get a dma buffer from the freelist here */ DRM_DEBUG("Allocating data memory ...\n"); #ifdef __FreeBSD__ DRM_UNLOCK(); #endif cpu_addr_dmah = drm_pci_alloc(dev, 0x1000, 0x1000, 0xfffffffful); #ifdef __FreeBSD__ DRM_LOCK(); #endif if (!cpu_addr_dmah) { DRM_INFO("data-memory allocation failed!\n"); return -ENOMEM; } else { data = (u32 *) cpu_addr_dmah->vaddr; data_addr = (u32) cpu_addr_dmah->busaddr; } /* Save the X server's value for SRC_CNTL and restore it * in case our test fails. This prevents the X server * from disabling it's cache for this register */ src_cntl = MACH64_READ(MACH64_SRC_CNTL); pat_reg0 = MACH64_READ(MACH64_PAT_REG0); pat_reg1 = MACH64_READ(MACH64_PAT_REG1); mach64_do_wait_for_fifo(dev_priv, 3); MACH64_WRITE(MACH64_SRC_CNTL, 0); MACH64_WRITE(MACH64_PAT_REG0, 0x11111111); MACH64_WRITE(MACH64_PAT_REG1, 0x11111111); mach64_do_wait_for_idle(dev_priv); for (i = 0; i < 2; i++) { u32 reg; reg = MACH64_READ((MACH64_PAT_REG0 + i * 4)); DRM_DEBUG("(Before DMA Transfer) reg %d = 0x%08x\n", i, reg); if (reg != 0x11111111) { DRM_INFO("Error initializing test registers\n"); DRM_INFO("resetting engine ...\n"); mach64_do_engine_reset(dev_priv); DRM_INFO("freeing data buffer memory.\n"); drm_pci_free(dev, cpu_addr_dmah); return -EIO; } } /* fill up a buffer with sets of 2 consecutive writes starting with PAT_REG0 */ count = 0; data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16)); data[count++] = expected[0] = 0x22222222; data[count++] = expected[1] = 0xaaaaaaaa; while (count < 1020) { data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16)); data[count++] = 0x22222222; data[count++] = 0xaaaaaaaa; } data[count++] = cpu_to_le32(DMAREG(MACH64_SRC_CNTL) | (0 << 16)); data[count++] = 0; DRM_DEBUG("Preparing table ...\n"); table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR + MACH64_APERTURE_OFFSET); table[MACH64_DMA_SYS_MEM_ADDR] = cpu_to_le32(data_addr); table[MACH64_DMA_COMMAND] = cpu_to_le32(count * sizeof(u32) | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL); table[MACH64_DMA_RESERVED] = 0; DRM_DEBUG("table[0] = 0x%08x\n", table[0]); DRM_DEBUG("table[1] = 0x%08x\n", table[1]); DRM_DEBUG("table[2] = 0x%08x\n", table[2]); DRM_DEBUG("table[3] = 0x%08x\n", table[3]); for (i = 0; i < 6; i++) { DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]); } DRM_DEBUG(" ...\n"); for (i = count - 5; i < count; i++) { DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]); } DRM_MEMORYBARRIER(); DRM_DEBUG("waiting for idle...\n"); if ((i = mach64_do_wait_for_idle(dev_priv))) { DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i); DRM_INFO("resetting engine ...\n"); mach64_do_engine_reset(dev_priv); mach64_do_wait_for_fifo(dev_priv, 3); MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); DRM_INFO("freeing data buffer memory.\n"); drm_pci_free(dev, cpu_addr_dmah); return i; } DRM_DEBUG("waiting for idle...done\n"); DRM_DEBUG("BUS_CNTL = 0x%08x\n", MACH64_READ(MACH64_BUS_CNTL)); DRM_DEBUG("SRC_CNTL = 0x%08x\n", MACH64_READ(MACH64_SRC_CNTL)); DRM_DEBUG("\n"); DRM_DEBUG("data bus addr = 0x%08x\n", data_addr); DRM_DEBUG("table bus addr = 0x%08x\n", dev_priv->ring.start_addr); DRM_DEBUG("starting DMA transfer...\n"); MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, dev_priv->ring.start_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); MACH64_WRITE(MACH64_SRC_CNTL, MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | MACH64_SRC_BM_OP_SYSTEM_TO_REG); /* Kick off the transfer */ DRM_DEBUG("starting DMA transfer... done.\n"); MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0); DRM_DEBUG("waiting for idle...\n"); if ((i = mach64_do_wait_for_idle(dev_priv))) { /* engine locked up, dump register state and reset */ DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i); mach64_dump_engine_info(dev_priv); DRM_INFO("resetting engine ...\n"); mach64_do_engine_reset(dev_priv); mach64_do_wait_for_fifo(dev_priv, 3); MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); DRM_INFO("freeing data buffer memory.\n"); drm_pci_free(dev, cpu_addr_dmah); return i; } DRM_DEBUG("waiting for idle...done\n"); /* restore SRC_CNTL */ mach64_do_wait_for_fifo(dev_priv, 1); MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); failed = 0; /* Check register values to see if the GUI master operation succeeded */ for (i = 0; i < 2; i++) { u32 reg; reg = MACH64_READ((MACH64_PAT_REG0 + i * 4)); DRM_DEBUG("(After DMA Transfer) reg %d = 0x%08x\n", i, reg); if (reg != expected[i]) { failed = -1; } } /* restore pattern registers */ mach64_do_wait_for_fifo(dev_priv, 2); MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); DRM_DEBUG("freeing data buffer memory.\n"); drm_pci_free(dev, cpu_addr_dmah); DRM_DEBUG("returning ...\n"); return failed; } /** * Called during the DMA initialization ioctl to initialize all the necessary * software and hardware state for DMA operation. */ static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) { drm_mach64_private_t *dev_priv; u32 tmp; int i, ret; DRM_DEBUG("\n"); dev_priv = drm_alloc(sizeof(drm_mach64_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) return -ENOMEM; memset(dev_priv, 0, sizeof(drm_mach64_private_t)); dev_priv->is_pci = init->is_pci; dev_priv->fb_bpp = init->fb_bpp; dev_priv->front_offset = init->front_offset; dev_priv->front_pitch = init->front_pitch; dev_priv->back_offset = init->back_offset; dev_priv->back_pitch = init->back_pitch; dev_priv->depth_bpp = init->depth_bpp; dev_priv->depth_offset = init->depth_offset; dev_priv->depth_pitch = init->depth_pitch; dev_priv->front_offset_pitch = (((dev_priv->front_pitch / 8) << 22) | (dev_priv->front_offset >> 3)); dev_priv->back_offset_pitch = (((dev_priv->back_pitch / 8) << 22) | (dev_priv->back_offset >> 3)); dev_priv->depth_offset_pitch = (((dev_priv->depth_pitch / 8) << 22) | (dev_priv->depth_offset >> 3)); dev_priv->usec_timeout = 1000000; /* Set up the freelist, placeholder list and pending list */ INIT_LIST_HEAD(&dev_priv->free_list); INIT_LIST_HEAD(&dev_priv->placeholders); INIT_LIST_HEAD(&dev_priv->pending); dev_priv->sarea = drm_getsarea(dev); if (!dev_priv->sarea) { DRM_ERROR("can not find sarea!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return -EINVAL; } dev_priv->fb = drm_core_findmap(dev, init->fb_offset); if (!dev_priv->fb) { DRM_ERROR("can not find frame buffer map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return -EINVAL; } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio) { DRM_ERROR("can not find mmio map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return -EINVAL; } dev_priv->ring_map = drm_core_findmap(dev, init->ring_offset); if (!dev_priv->ring_map) { DRM_ERROR("can not find ring map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return -EINVAL; } dev_priv->sarea_priv = (drm_mach64_sarea_t *) ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); if (!dev_priv->is_pci) { drm_core_ioremap(dev_priv->ring_map, dev); if (!dev_priv->ring_map->handle) { DRM_ERROR("can not ioremap virtual address for" " descriptor ring\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return -ENOMEM; } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); if (!dev->agp_buffer_map) { DRM_ERROR("can not find dma buffer map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return -EINVAL; } /* there might be a nicer way to do this - dev isn't passed all the way though the mach64 - DA */ dev_priv->dev_buffers = dev->agp_buffer_map; drm_core_ioremap(dev->agp_buffer_map, dev); if (!dev->agp_buffer_map->handle) { DRM_ERROR("can not ioremap virtual address for" " dma buffer\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return -ENOMEM; } dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); if (!dev_priv->agp_textures) { DRM_ERROR("can not find agp texture region!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return -EINVAL; } } dev->dev_private = (void *)dev_priv; dev_priv->driver_mode = init->dma_mode; /* changing the FIFO size from the default causes problems with DMA */ tmp = MACH64_READ(MACH64_GUI_CNTL); if ((tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128) { DRM_INFO("Setting FIFO size to 128 entries\n"); /* FIFO must be empty to change the FIFO depth */ if ((ret = mach64_do_wait_for_idle(dev_priv))) { DRM_ERROR ("wait for idle failed before changing FIFO depth!\n"); mach64_do_cleanup_dma(dev); return ret; } MACH64_WRITE(MACH64_GUI_CNTL, ((tmp & ~MACH64_CMDFIFO_SIZE_MASK) | MACH64_CMDFIFO_SIZE_128)); /* need to read GUI_STAT for proper sync according to docs */ if ((ret = mach64_do_wait_for_idle(dev_priv))) { DRM_ERROR ("wait for idle failed when changing FIFO depth!\n"); mach64_do_cleanup_dma(dev); return ret; } } dev_priv->ring.size = 0x4000; /* 16KB */ dev_priv->ring.start = dev_priv->ring_map->handle; dev_priv->ring.start_addr = (u32) dev_priv->ring_map->offset; memset(dev_priv->ring.start, 0, dev_priv->ring.size); DRM_INFO("descriptor ring: cpu addr %p, bus addr: 0x%08x\n", dev_priv->ring.start, dev_priv->ring.start_addr); ret = 0; if (dev_priv->driver_mode != MACH64_MODE_MMIO) { /* enable block 1 registers and bus mastering */ MACH64_WRITE(MACH64_BUS_CNTL, ((MACH64_READ(MACH64_BUS_CNTL) | MACH64_BUS_EXT_REG_EN) & ~MACH64_BUS_MASTER_DIS)); /* try a DMA GUI-mastering pass and fall back to MMIO if it fails */ DRM_DEBUG("Starting DMA test...\n"); if ((ret = mach64_bm_dma_test(dev))) { dev_priv->driver_mode = MACH64_MODE_MMIO; } } switch (dev_priv->driver_mode) { case MACH64_MODE_MMIO: MACH64_WRITE(MACH64_BUS_CNTL, (MACH64_READ(MACH64_BUS_CNTL) | MACH64_BUS_EXT_REG_EN | MACH64_BUS_MASTER_DIS)); if (init->dma_mode == MACH64_MODE_MMIO) DRM_INFO("Forcing pseudo-DMA mode\n"); else DRM_INFO ("DMA test failed (ret=%d), using pseudo-DMA mode\n", ret); break; case MACH64_MODE_DMA_SYNC: DRM_INFO("DMA test succeeded, using synchronous DMA mode\n"); break; case MACH64_MODE_DMA_ASYNC: default: DRM_INFO("DMA test succeeded, using asynchronous DMA mode\n"); } dev_priv->ring_running = 0; /* setup offsets for physical address of table start and end */ dev_priv->ring.head_addr = dev_priv->ring.start_addr; dev_priv->ring.head = dev_priv->ring.tail = 0; dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.space = dev_priv->ring.size; /* setup physical address and size of descriptor table */ mach64_do_wait_for_fifo(dev_priv, 1); MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, (dev_priv->ring. head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB)); /* init frame counter */ dev_priv->sarea_priv->frames_queued = 0; for (i = 0; i < MACH64_MAX_QUEUED_FRAMES; i++) { dev_priv->frame_ofs[i] = ~0; /* All ones indicates placeholder */ } /* Allocate the DMA buffer freelist */ if ((ret = mach64_init_freelist(dev))) { DRM_ERROR("Freelist allocation failed\n"); mach64_do_cleanup_dma(dev); return ret; } return 0; } /*******************************************************************/ /** MMIO Pseudo-DMA (intended primarily for debugging, not performance) */ int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t *dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; volatile u32 *ring_read; struct list_head *ptr; drm_mach64_freelist_t *entry; struct drm_buf *buf = NULL; u32 *buf_ptr; u32 used, reg, target; int fifo, count, found, ret, no_idle_wait; fifo = count = reg = no_idle_wait = 0; target = MACH64_BM_ADDR; if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) { DRM_INFO("idle failed before pseudo-dma dispatch, resetting engine\n"); mach64_dump_engine_info(dev_priv); mach64_do_engine_reset(dev_priv); return ret; } ring_read = (u32 *) ring->start; while (ring->tail != ring->head) { u32 buf_addr, new_target, offset; u32 bytes, remaining, head, eol; head = ring->head; new_target = le32_to_cpu(ring_read[head++]) - MACH64_APERTURE_OFFSET; buf_addr = le32_to_cpu(ring_read[head++]); eol = le32_to_cpu(ring_read[head]) & MACH64_DMA_EOL; bytes = le32_to_cpu(ring_read[head++]) & ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL); head++; head &= ring->tail_mask; /* can't wait for idle between a blit setup descriptor * and a HOSTDATA descriptor or the engine will lock */ if (new_target == MACH64_BM_HOSTDATA && target == MACH64_BM_ADDR) no_idle_wait = 1; target = new_target; found = 0; offset = 0; list_for_each(ptr, &dev_priv->pending) { entry = list_entry(ptr, drm_mach64_freelist_t, list); buf = entry->buf; offset = buf_addr - GETBUFADDR(buf); if (offset >= 0 && offset < MACH64_BUFFER_SIZE) { found = 1; break; } } if (!found || buf == NULL) { DRM_ERROR ("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n", head, ring->tail, buf_addr, (eol ? "eol" : "")); mach64_dump_ring_info(dev_priv); mach64_do_engine_reset(dev_priv); return -EINVAL; } /* Hand feed the buffer to the card via MMIO, waiting for the fifo * every 16 writes */ DRM_DEBUG("target: (0x%08x) %s\n", target, (target == MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR")); DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes, buf->used); remaining = (buf->used - offset) >> 2; /* dwords remaining in buffer */ used = bytes >> 2; /* dwords in buffer for this descriptor */ buf_ptr = (u32 *) ((char *)GETBUFPTR(buf) + offset); while (used) { if (count == 0) { if (target == MACH64_BM_HOSTDATA) { reg = DMAREG(MACH64_HOST_DATA0); count = (remaining > 16) ? 16 : remaining; fifo = 0; } else { reg = le32_to_cpu(*buf_ptr++); used--; count = (reg >> 16) + 1; } reg = reg & 0xffff; reg = MMSELECT(reg); } while (count && used) { if (!fifo) { if (no_idle_wait) { if ((ret = mach64_do_wait_for_fifo (dev_priv, 16)) < 0) { no_idle_wait = 0; return ret; } } else { if ((ret = mach64_do_wait_for_idle (dev_priv)) < 0) { return ret; } } fifo = 16; } --fifo; MACH64_WRITE(reg, le32_to_cpu(*buf_ptr++)); used--; remaining--; reg += 4;