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path: root/linux-core/drm_irq.c
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/**
 * \file drm_irq.c
 * IRQ support
 *
 * \author Rickard E. (Rik) Faith <faith@valinux.com>
 * \author Gareth Hughes <gareth@valinux.com>
 */

/*
 * Created: Fri Mar 19 14:30:16 1999 by faith@valinux.com
 *
 * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"

#include <linux/interrupt.h>	/* For task queue support */

/**
 * Get interrupt from bus id.
 *
 * \param inode device inode.
 * \param file_priv DRM file private.
 * \param cmd command.
 * \param arg user argument, pointing to a drm_irq_busid structure.
 * \return zero on success or a negative number on failure.
 *
 * Finds the PCI device with the specified bus id and gets its IRQ number.
 * This IOCTL is deprecated, and will now return EINVAL for any busid not equal
 * to that of the device that this DRM instance attached to.
 */
int drm_irq_by_busid(struct drm_device *dev, void *data,
		     struct drm_file *file_priv)
{
	struct drm_irq_busid *p = data;

	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
		return -EINVAL;

	if ((p->busnum >> 8) != drm_get_pci_domain(dev) ||
	    (p->busnum & 0xff) != dev->pdev->bus->number ||
	    p->devnum != PCI_SLOT(dev->pdev->devfn) || p->funcnum != PCI_FUNC(dev->pdev->devfn))
		return -EINVAL;

	p->irq = dev->irq;

	DRM_DEBUG("%d:%d:%d => IRQ %d\n", p->busnum, p->devnum, p->funcnum,
		  p->irq);

	return 0;
}

/**
 * Install IRQ handler.
 *
 * \param dev DRM device.
 *
 * Initializes the IRQ related data, and setups drm_device::vbl_queue. Installs the handler, calling the driver
 * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions
 * before and after the installation.
 */
int drm_irq_install(struct drm_device * dev)
{
	int ret;
	unsigned long sh_flags = 0;

	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
		return -EINVAL;

	if (dev->irq == 0)
		return -EINVAL;

	mutex_lock(&dev->struct_mutex);

	/* Driver must have been initialized */
	if (!dev->dev_private) {
		mutex_unlock(&dev->struct_mutex);
		return -EINVAL;
	}

	if (dev->irq_enabled) {
		mutex_unlock(&dev->struct_mutex);
		return -EBUSY;
	}
	dev->irq_enabled = 1;
	mutex_unlock(&dev->struct_mutex);

	DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev->irq);

	if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) {
		init_waitqueue_head(&dev->vbl_queue);

		spin_lock_init(&dev->vbl_lock);

		INIT_LIST_HEAD(&dev->vbl_sigs);
		INIT_LIST_HEAD(&dev->vbl_sigs2);

		dev->vbl_pending = 0;
	}

	/* Before installing handler */
	dev->driver->irq_preinstall(dev);

	/* Install handler */
	if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED))
		sh_flags = IRQF_SHARED;

	ret = request_irq(dev->irq, dev->driver->irq_handler,
			  sh_flags, dev->devname, dev);
	if (ret < 0) {
		mutex_lock(&dev->struct_mutex);
		dev->irq_enabled = 0;
		mutex_unlock(&dev->struct_mutex);
		return ret;
	}

	/* After installing handler */
	dev->driver->irq_postinstall(dev);

	return 0;
}
EXPORT_SYMBOL(drm_irq_install);

/**
 * Uninstall the IRQ handler.
 *
 * \param dev DRM device.
 *
 * Calls the driver's \c drm_driver_irq_uninstall() function, and stops the irq.
 */
int drm_irq_uninstall(struct drm_device * dev)
{
	int irq_enabled;

	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
		return -EINVAL;

	mutex_lock(&dev->struct_mutex);
	irq_enabled = dev->irq_enabled;
	dev->irq_enabled = 0;
	mutex_unlock(&dev->struct_mutex);

	if (!irq_enabled)
		return -EINVAL;

	DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev->irq);

	dev->driver->irq_uninstall(dev);

	free_irq(dev->irq, dev);

	dev->locked_tasklet_func = NULL;

	return 0;
}
EXPORT_SYMBOL(drm_irq_uninstall);

/**
 * IRQ control ioctl.
 *
 * \param inode device inode.
 * \param file_priv DRM file private.
 * \param cmd command.
 * \param arg user argument, pointing to a drm_control structure.
 * \return zero on success or a negative number on failure.
 *
 * Calls irq_install() or irq_uninstall() according to \p arg.
 */
int drm_control(struct drm_device *dev, void *data,
		struct drm_file *file_priv)
{
	struct drm_control *ctl = data;

	/* if we haven't irq we fallback for compatibility reasons - this used to be a separate function in drm_dma.h */


	switch (ctl->func) {
	case DRM_INST_HANDLER:
		if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
			return 0;
		if (dev->if_version < DRM_IF_VERSION(1, 2) &&
		    ctl->irq != dev->irq)
			return -EINVAL;
		return drm_irq_install(dev);
	case DRM_UNINST_HANDLER:
		if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
			return 0;
		return drm_irq_uninstall(dev);
	default:
		return -EINVAL;
	}
}

/**
 * Wait for VBLANK.
 *
 * \param inode device inode.
 * \param file_priv DRM file private.
 * \param cmd command.
 * \param data user argument, pointing to a drm_wait_vblank structure.
 * \return zero on success or a negative number on failure.
 *
 * Verifies the IRQ is installed.
 *
 * If a signal is requested checks if this task has already scheduled the same signal
 * for the same vblank sequence number - nothing to be done in
 * that case. If the number of tasks waiting for the interrupt exceeds 100 the
 * function fails. Otherwise adds a new entry to drm_device::vbl_sigs for this
 * task.
 *
 * If a signal is not requested, then calls vblank_wait().
 */
int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	union drm_wait_vblank *vblwait = data;
	struct timeval now;
	int ret = 0;
	unsigned int flags, seq;

	if ((!dev->irq) || (!dev->irq_enabled))
		return -EINVAL;

	if (vblwait->request.type &
	    ~(_DRM_VBLANK_TYPES_MASK | _DRM_VBLANK_FLAGS_MASK)) {
		DRM_ERROR("Unsupported type value 0x%x, supported mask 0x%x\n",
			  vblwait->request.type,
			  (_DRM_VBLANK_TYPES_MASK | _DRM_VBLANK_FLAGS_MASK));
		return -EINVAL;
	}

	flags = vblwait->request.type & _DRM_VBLANK_FLAGS_MASK;

	if (!drm_core_check_feature(dev, (flags & _DRM_VBLANK_SECONDARY) ?
				    DRIVER_IRQ_VBL2 : DRIVER_IRQ_VBL))
		return -EINVAL;

	seq = atomic_read((flags & _DRM_VBLANK_SECONDARY) ? &dev->vbl_received2
			  : &dev->vbl_received);

	switch (vblwait->request.type & _DRM_VBLANK_TYPES_MASK) {
	case _DRM_VBLANK_RELATIVE:
		vblwait->request.sequence += seq;
		vblwait->request.type &= ~_DRM_VBLANK_RELATIVE;
	case _DRM_VBLANK_ABSOLUTE:
		break;
	default:
		return -EINVAL;
	}

	if ((flags & _DRM_VBLANK_NEXTONMISS) &&
	    (seq - vblwait->request.sequence) <= (1<<23)) {
		vblwait->request.sequence = seq + 1;
	}

	if (flags & _DRM_VBLANK_SIGNAL) {
		unsigned long irqflags;
		struct list_head *vbl_sigs = (flags & _DRM_VBLANK_SECONDARY)
				      ? &dev->vbl_sigs2 : &dev->vbl_sigs;
		struct drm_vbl_sig *vbl_sig;

		spin_lock_irqsave(&dev->vbl_lock, irqflags);

		/* Check if this task has already scheduled the same signal
		 * for the same vblank sequence number; nothing to be done in
		 * that case
		 */
		list_for_each_entry(vbl_sig, vbl_sigs, head) {
			if (vbl_sig->sequence == vblwait->request.sequence
			    && vbl_sig->info.si_signo ==
			    vblwait->request.signal
			    && vbl_sig->task == current) {
				spin_unlock_irqrestore(&dev->vbl_lock,
						       irqflags);
				vblwait->reply.sequence = seq;
				goto done;
			}
		}

		if (dev->vbl_pending >= 100) {
			spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
			return -EBUSY;
		}

		dev->vbl_pending++;

		spin_unlock_irqrestore(&dev->vbl_lock, irqflags);

		if (!
		    (vbl_sig =
		     drm_alloc(sizeof(struct drm_vbl_sig), DRM_MEM_DRIVER))) {
			return -ENOMEM;
		}

		memset((void *)vbl_sig, 0, sizeof(*vbl_sig));

		vbl_sig->sequence = vblwait->request.sequence;
		vbl_sig->info.si_signo = vblwait->request.signal;
		vbl_sig->task = current;

		spin_lock_irqsave(&dev->vbl_lock, irqflags);

		list_add_tail(&vbl_sig->head, vbl_sigs);

		spin_unlock_irqrestore(&dev->vbl_lock, irqflags);

		vblwait->reply.sequence = seq;
	} else {
		if (flags & _DRM_VBLANK_SECONDARY) {
			if (dev->driver->vblank_wait2)
				ret = dev->driver->vblank_wait2(dev, &vblwait->request.sequence);
		} else if (dev->driver->vblank_wait)
			ret =
			    dev->driver->vblank_wait(dev,
						     &vblwait->request.sequence);

		do_gettimeofday(&now);
		vblwait->reply.tval_sec = now.tv_sec;
		vblwait->reply.tval_usec = now.tv_usec;
	}

      done:
	return ret;
}

/**
 * Send the VBLANK signals.
 *
 * \param dev DRM device.
 *
 * Sends a signal for each task in drm_device::vbl_sigs and empties the list.
 *
 * If a signal is not requested, then calls vblank_wait().
 */
void drm_vbl_send_signals(struct drm_device * dev)
{
	unsigned long flags;
	int i;

	spin_lock_irqsave(&dev->vbl_lock, flags);

	for (i = 0; i < 2; i++) {
		struct drm_vbl_sig *vbl_sig, *tmp;
		struct list_head *vbl_sigs = i ? &dev->vbl_sigs2 : &dev->vbl_sigs;
		unsigned int vbl_seq = atomic_read(i ? &dev->vbl_received2 :
						   &dev->vbl_received);

		list_for_each_entry_safe(vbl_sig, tmp, vbl_sigs, head) {
			if ((vbl_seq - vbl_sig->sequence) <= (1 << 23)) {
				vbl_sig->info.si_code = vbl_seq;
				send_sig_info(vbl_sig->info.si_signo,
					      &vbl_sig->info, vbl_sig->task);

				list_del(&vbl_sig->head);

				drm_free(vbl_sig, sizeof(*vbl_sig),
					 DRM_MEM_DRIVER);

				dev->vbl_pending--;
			}
		}
	}

	spin_unlock_irqrestore(&dev->vbl_lock, flags);
}
EXPORT_SYMBOL(drm_vbl_send_signals);

/**
 * Tasklet wrapper function.
 *
 * \param data DRM device in disguise.
 *
 * Attempts to grab the HW lock and calls the driver callback on success. On
 * failure, leave the lock marked as contended so the callback can be called
 * from drm_unlock().
 */
static void drm_locked_tasklet_func(unsigned long data)
{
	struct drm_device *dev = (struct drm_device*)data;
	unsigned long irqflags;

	spin_lock_irqsave(&dev->tasklet_lock, irqflags);

	if (!dev->locked_tasklet_func ||
	    !drm_lock_take(&dev->lock,
			   DRM_KERNEL_CONTEXT)) {
		spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
		return;
	}

	dev->lock.lock_time = jiffies;
	atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);

	dev->locked_tasklet_func(dev);

	drm_lock_free(&dev->lock,
		      DRM_KERNEL_CONTEXT);

	dev->locked_tasklet_func = NULL;

	spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
}

/**
 * Schedule a tasklet to call back a driver hook with the HW lock held.
 *
 * \param dev DRM device.
 * \param func Driver callback.
 *
 * This is intended for triggering actions that require the HW lock from an
 * interrupt handler. The lock will be grabbed ASAP after the interrupt handler
 * completes. Note that the callback may be called from interrupt or process
 * context, it must not make any assumptions about this. Also, the HW lock will
 * be held with the kernel context or any client context.
 */
void drm_locked_tasklet(struct drm_device *dev, void (*func)(struct drm_device*))
{
	unsigned long irqflags;
	static DECLARE_TASKLET(drm_tasklet, drm_locked_tasklet_func, 0);

	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ) ||
	    test_bit(TASKLET_STATE_SCHED, &drm_tasklet.state))
		return;

	spin_lock_irqsave(&dev->tasklet_lock, irqflags);

	if (dev->locked_tasklet_func) {
		spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
		return;
	}

	dev->locked_tasklet_func = func;

	spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);

	drm_tasklet.data = (unsigned long)dev;

	tasklet_hi_schedule(&drm_tasklet);
}
EXPORT_SYMBOL(drm_locked_tasklet);
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/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
/*
 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Kevin E. Martin <martin@valinux.com>
 *    Gareth Hughes <gareth@valinux.com>
 */

#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include "r300_reg.h"

#define RADEON_FIFO_DEBUG	0

static int radeon_do_cleanup_cp(struct drm_device * dev);

/* CP microcode (from ATI) */
static const u32 R200_cp_microcode[][2] = {
	{0x21007000, 0000000000},
	{0x20007000, 0000000000},
	{0x000000ab, 0x00000004},
	{0x000000af, 0x00000004},
	{0x66544a49, 0000000000},
	{0x49494174, 0000000000},
	{0x54517d83, 0000000000},
	{0x498d8b64, 0000000000},
	{0x49494949, 0000000000},
	{0x49da493c, 0000000000},
	{0x49989898, 0000000000},
	{0xd34949d5, 0000000000},
	{0x9dc90e11, 0000000000},
	{0xce9b9b9b, 0000000000},
	{0x000f0000, 0x00000016},
	{0x352e232c, 0000000000},
	{0x00000013, 0x00000004},
	{0x000f0000, 0x00000016},
	{0x352e272c, 0000000000},
	{0x000f0001, 0x00000016},
	{0x3239362f, 0000000000},
	{0x000077ef, 0x00000002},
	{0x00061000, 0x00000002},
	{0x00000020, 0x0000001a},
	{0x00004000, 0x0000001e},
	{0x00061000, 0x00000002},
	{0x00000020, 0x0000001a},
	{0x00004000, 0x0000001e},
	{0x00061000, 0x00000002},
	{0x00000020, 0x0000001a},
	{0x00004000, 0x0000001e},
	{0x00000016, 0x00000004},
	{0x0003802a, 0x00000002},
	{0x040067e0, 0x00000002},
	{0x00000016, 0x00000004},
	{0x000077e0, 0x00000002},
	{0x00065000, 0x00000002},
	{0x000037e1, 0x00000002},
	{0x040067e1, 0x00000006},
	{0x000077e0, 0x00000002},
	{0x000077e1, 0x00000002},
	{0x000077e1, 0x00000006},
	{0xffffffff, 0000000000},
	{0x10000000, 0000000000},
	{0x0003802a, 0x00000002},
	{0x040067e0, 0x00000006},
	{0x00007675, 0x00000002},
	{0x00007676, 0x00000002},
	{0x00007677, 0x00000002},
	{0x00007678, 0x00000006},
	{0x0003802b, 0x00000002},
	{0x04002676, 0x00000002},
	{0x00007677, 0x00000002},
	{0x00007678, 0x00000006},
	{0x0000002e, 0x00000018},
	{0x0000002e, 0x00000018},
	{0000000000, 0x00000006},
	{0x0000002f, 0x00000018},
	{0x0000002f, 0x00000018},
	{0000000000, 0x00000006},
	{0x01605000, 0x00000002},
	{0x00065000, 0x00000002},
	{0x00098000, 0x00000002},
	{0x00061000, 0x00000002},
	{0x64c0603d, 0x00000004},
	{0x00080000, 0x00000016},
	{0000000000, 0000000000},
	{0x0400251d, 0x00000002},
	{0x00007580, 0x00000002},
	{0x00067581, 0x00000002},
	{0x04002580, 0x00000002},
	{0x00067581, 0x00000002},
	{0x00000046, 0x00000004},
	{0x00005000, 0000000000},
	{0x00061000, 0x00000002},
	{0x0000750e, 0x00000002},
	{0x00019000, 0x00000002},
	{0x00011055, 0x00000014},
	{0x00000055, 0x00000012},
	{0x0400250f, 0x00000002},
	{0x0000504a, 0x00000004},
	{0x00007565, 0x00000002},
	{0x00007566, 0x00000002},
	{0x00000051, 0x00000004},
	{0x01e655b4, 0x00000002},
	{0x4401b0dc, 0x00000002},
	{0x01c110dc, 0x00000002},
	{0x2666705d, 0x00000018},
	{0x040c2565, 0x00000002},
	{0x0000005d, 0x00000018},
	{0x04002564, 0x00000002},
	{0x00007566, 0x00000002},
	{0x00000054, 0x00000004},
	{0x00401060, 0x00000008},
	{0x00101000, 0x00000002},
	{0x000d80ff, 0x00000002},
	{0x00800063, 0x00000008},
	{0x000f9000, 0x00000002},
	{0x000e00ff, 0x00000002},
	{0000000000, 0x00000006},
	{0x00000080, 0x00000018},
	{0x00000054, 0x00000004},
	{0x00007576, 0x00000002},
	{0x00065000, 0x00000002},
	{0x00009000, 0x00000002},
	{0x00041000, 0x00000002},
	{0x0c00350e, 0x00000002},
	{0x00049000, 0x00000002},
	{0x00051000, 0x00000002},
	{0x01e785f8, 0x00000002},
	{0x00200000, 0x00000002},
	{0x00600073, 0x0000000c},
	{0x00007563, 0x00000002},
	{0x006075f0, 0x00000021},
	{0x20007068, 0x00000004},
	{0x00005068, 0x00000004},
	{0x00007576, 0x00000002},
	{0x00007577, 0x00000002},
	{0x0000750e, 0x00000002},
	{0x0000750f, 0x00000002},
	{0x00a05000, 0x00000002},
	{0x00600076, 0x0000000c},
	{0x006075f0, 0x00000021},
	{0x000075f8, 0x00000002},
	{0x00000076, 0x00000004},
	{0x000a750e, 0x00000002},
	{0x0020750f, 0x00000002},
	{0x00600079, 0x00000004},
	{0x00007570, 0x00000002},
	{0x00007571, 0x00000002},
	{0x00007572, 0x00000006},
	{0x00005000, 0x00000002},
	{0x00a05000, 0x00000002},
	{0x00007568, 0x00000002},
	{0x00061000, 0x00000002},
	{0x00000084, 0x0000000c},
	{0x00058000, 0x00000002},
	{0x0c607562, 0x00000002},
	{0x00000086, 0x00000004},
	{0x00600085, 0x00000004},
	{0x400070dd, 0000000000},
	{0x000380dd, 0x00000002},
	{0x00000093, 0x0000001c},
	{0x00065095, 0x00000018},
	{0x040025bb, 0x00000002},
	{0x00061096, 0x00000018},
	{0x040075bc, 0000000000},
	{0x000075bb, 0x00000002},
	{0x000075bc, 0000000000},
	{0x00090000, 0x00000006},
	{0x00090000, 0x00000002},
	{0x000d8002, 0x00000006},
	{0x00005000, 0x00000002},
	{0x00007821, 0x00000002},
	{0x00007800, 0000000000},
	{0x00007821, 0x00000002},
	{0x00007800, 0000000000},
	{0x01665000, 0x00000002},
	{0x000a0000, 0x00000002},
	{0x000671cc, 0x00000002},
	{0x0286f1cd, 0x00000002},
	{0x000000a3, 0x00000010},
	{0x21007000, 0000000000},
	{0x000000aa, 0x0000001c},
	{0x00065000, 0x00000002},
	{0x000a0000, 0x00000002},
	{0x00061000, 0x00000002},
	{0x000b0000, 0x00000002},
	{0x38067000, 0x00000002},
	{0x000a00a6, 0x00000004},
	{0x20007000, 0000000000},
	{0x01200000, 0x00000002},
	{0x20077000, 0x00000002},
	{0x01200000, 0x00000002},
	{0x20007000, 0000000000},
	{0x00061000, 0x00000002},
	{0x0120751b, 0x00000002},
	{0x8040750a, 0x00000002},
	{0x8040750b, 0x00000002},
	{0x00110000, 0x00000002},
	{0x000380dd, 0x00000002},
	{0x000000bd, 0x0000001c},
	{0x00061096, 0x00000018},
	{0x844075bd, 0x00000002},
	{0x00061095, 0x00000018},
	{0x840075bb, 0x00000002},
	{0x00061096, 0x00000018},
	{0x844075bc, 0x00000002},
	{0x000000c0, 0x00000004},
	{0x804075bd, 0x00000002},
	{0x800075bb, 0x00000002},
	{0x804075bc, 0x00000002},
	{0x00108000, 0x00000002},
	{0x01400000, 0x00000002},
	{0x006000c4, 0x0000000c},
	{0x20c07000, 0x00000020},
	{0x000000c6, 0x00000012},
	{0x00800000, 0x00000006},
	{0x0080751d, 0x00000006},
	{0x000025bb, 0x00000002},
	{0x000040c0, 0x00000004},
	{0x0000775c, 0x00000002},
	{0x00a05000, 0x00000002},
	{0x00661000, 0x00000002},
	{0x0460275d, 0x00000020},
	{0x00004000, 0000000000},
	{0x00007999, 0x00000002},
	{0x00a05000, 0x00000002},
	{0x00661000, 0x00000002},
	{0x0460299b, 0x00000020},
	{0x00004000, 0000000000},
	{0x01e00830, 0x00000002},
	{0x21007000, 0000000000},
	{0x00005000, 0x00000002},
	{0x00038042, 0x00000002},
	{0x040025e0, 0x00000002},
	{0x000075e1, 0000000000},
	{0x00000001, 0000000000},
	{0x000380d9, 0x00000002},
	{0x04007394, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
};

static const u32 radeon_cp_microcode[][2] = {
	{0x21007000, 0000000000},
	{0x20007000, 0000000000},
	{0x000000b4, 0x00000004},
	{0x000000b8, 0x00000004},
	{0x6f5b4d4c, 0000000000},
	{0x4c4c427f, 0000000000},
	{0x5b568a92, 0000000000},
	{0x4ca09c6d, 0000000000},
	{0xad4c4c4c, 0000000000},
	{0x4ce1af3d, 0000000000},
	{0xd8afafaf, 0000000000},
	{0xd64c4cdc, 0000000000},
	{0x4cd10d10, 0000000000},
	{0x000f0000, 0x00000016},
	{0x362f242d, 0000000000},
	{0x00000012, 0x00000004},
	{0x000f0000, 0x00000016},
	{0x362f282d, 0000000000},
	{0x000380e7, 0x00000002},
	{0x04002c97, 0x00000002},
	{0x000f0001, 0x00000016},
	{0x333a3730, 0000000000},
	{0x000077ef, 0x00000002},
	{0x00061000, 0x00000002},
	{0x00000021, 0x0000001a},
	{0x00004000, 0x0000001e},
	{0x00061000, 0x00000002},
	{0x00000021, 0x0000001a},
	{0x00004000, 0x0000001e},
	{0x00061000, 0x00000002},
	{0x00000021, 0x0000001a},
	{0x00004000, 0x0000001e},
	{0x00000017, 0x00000004},
	{0x0003802b, 0x00000002},
	{0x040067e0, 0x00000002},
	{0x00000017, 0x00000004},
	{0x000077e0, 0x00000002},
	{0x00065000, 0x00000002},
	{0x000037e1, 0x00000002},
	{0x040067e1, 0x00000006},
	{0x000077e0, 0x00000002},
	{0x000077e1, 0x00000002},
	{0x000077e1, 0x00000006},
	{0xffffffff, 0000000000},
	{0x10000000, 0000000000},
	{0x0003802b, 0x00000002},
	{0x040067e0, 0x00000006},
	{0x00007675, 0x00000002},
	{0x00007676, 0x00000002},
	{0x00007677, 0x00000002},
	{0x00007678, 0x00000006},
	{0x0003802c, 0x00000002},
	{0x04002676, 0x00000002},
	{0x00007677, 0x00000002},
	{0x00007678, 0x00000006},
	{0x0000002f, 0x00000018},
	{0x0000002f, 0x00000018},
	{0000000000, 0x00000006},
	{0x00000030, 0x00000018},
	{0x00000030, 0x00000018},
	{0000000000, 0x00000006},
	{0x01605000, 0x00000002},
	{0x00065000, 0x00000002},
	{0x00098000, 0x00000002},
	{0x00061000, 0x00000002},
	{0x64c0603e, 0x00000004},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x00080000, 0x00000016},
	{0000000000, 0000000000},
	{0x0400251d, 0x00000002},
	{0x00007580, 0x00000002},
	{0x00067581, 0x00000002},
	{0x04002580, 0x00000002},
	{0x00067581, 0x00000002},
	{0x00000049, 0x00000004},
	{0x00005000, 0000000000},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x00061000, 0x00000002},
	{0x0000750e, 0x00000002},
	{0x00019000, 0x00000002},
	{0x00011055, 0x00000014},
	{0x00000055, 0x00000012},
	{0x0400250f, 0x00000002},
	{0x0000504f, 0x00000004},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x00007565, 0x00000002},
	{0x00007566, 0x00000002},
	{0x00000058, 0x00000004},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x01e655b4, 0x00000002},
	{0x4401b0e4, 0x00000002},
	{0x01c110e4, 0x00000002},
	{0x26667066, 0x00000018},
	{0x040c2565, 0x00000002},
	{0x00000066, 0x00000018},
	{0x04002564, 0x00000002},
	{0x00007566, 0x00000002},
	{0x0000005d, 0x00000004},
	{0x00401069, 0x00000008},
	{0x00101000, 0x00000002},
	{0x000d80ff, 0x00000002},
	{0x0080006c, 0x00000008},
	{0x000f9000, 0x00000002},
	{0x000e00ff, 0x00000002},
	{0000000000, 0x00000006},
	{0x0000008f, 0x00000018},
	{0x0000005b, 0x00000004},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x00007576, 0x00000002},
	{0x00065000, 0x00000002},
	{0x00009000, 0x00000002},
	{0x00041000, 0x00000002},
	{0x0c00350e, 0x00000002},
	{0x00049000, 0x00000002},
	{0x00051000, 0x00000002},
	{0x01e785f8, 0x00000002},
	{0x00200000, 0x00000002},
	{0x0060007e, 0x0000000c},
	{0x00007563, 0x00000002},
	{0x006075f0, 0x00000021},
	{0x20007073, 0x00000004},
	{0x00005073, 0x00000004},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x00007576, 0x00000002},
	{0x00007577, 0x00000002},
	{0x0000750e, 0x00000002},
	{0x0000750f, 0x00000002},
	{0x00a05000, 0x00000002},
	{0x00600083, 0x0000000c},
	{0x006075f0, 0x00000021},
	{0x000075f8, 0x00000002},
	{0x00000083, 0x00000004},
	{0x000a750e, 0x00000002},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x0020750f, 0x00000002},
	{0x00600086, 0x00000004},
	{0x00007570, 0x00000002},
	{0x00007571, 0x00000002},
	{0x00007572, 0x00000006},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x00005000, 0x00000002},
	{0x00a05000, 0x00000002},
	{0x00007568, 0x00000002},
	{0x00061000, 0x00000002},
	{0x00000095, 0x0000000c},
	{0x00058000, 0x00000002},
	{0x0c607562, 0x00000002},
	{0x00000097, 0x00000004},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x00600096, 0x00000004},
	{0x400070e5, 0000000000},
	{0x000380e6, 0x00000002},
	{0x040025c5, 0x00000002},
	{0x000380e5, 0x00000002},
	{0x000000a8, 0x0000001c},
	{0x000650aa, 0x00000018},
	{0x040025bb, 0x00000002},
	{0x000610ab, 0x00000018},
	{0x040075bc, 0000000000},
	{0x000075bb, 0x00000002},
	{0x000075bc, 0000000000},
	{0x00090000, 0x00000006},
	{0x00090000, 0x00000002},
	{0x000d8002, 0x00000006},
	{0x00007832, 0x00000002},
	{0x00005000, 0x00000002},
	{0x000380e7, 0x00000002},
	{0x04002c97, 0x00000002},
	{0x00007820, 0x00000002},
	{0x00007821, 0x00000002},
	{0x00007800, 0000000000},
	{0x01200000, 0x00000002},
	{0x20077000, 0x00000002},
	{0x01200000, 0x00000002},
	{0x20007000, 0x00000002},
	{0x00061000, 0x00000002},
	{0x0120751b, 0x00000002},
	{0x8040750a, 0x00000002},
	{0x8040750b, 0x00000002},
	{0x00110000, 0x00000002},
	{0x000380e5, 0x00000002},
	{0x000000c6, 0x0000001c},
	{0x000610ab, 0x00000018},
	{0x844075bd, 0x00000002},
	{0x000610aa, 0x00000018},
	{0x840075bb, 0x00000002},
	{0x000610ab, 0x00000018},
	{0x844075bc, 0x00000002},
	{0x000000c9, 0x00000004},
	{0x804075bd, 0x00000002},
	{0x800075bb, 0x00000002},
	{0x804075bc, 0x00000002},
	{0x00108000, 0x00000002},
	{0x01400000, 0x00000002},
	{0x006000cd, 0x0000000c},
	{0x20c07000, 0x00000020},
	{0x000000cf, 0x00000012},
	{0x00800000, 0x00000006},
	{0x0080751d, 0x00000006},
	{0000000000, 0000000000},
	{0x0000775c, 0x00000002},
	{0x00a05000, 0x00000002},
	{0x00661000, 0x00000002},
	{0x0460275d, 0x00000020},
	{0x00004000, 0000000000},
	{0x01e00830, 0x00000002},
	{0x21007000, 0000000000},
	{0x6464614d, 0000000000},
	{0x69687420, 0000000000},
	{0x00000073, 0000000000},
	{0000000000, 0000000000},
	{0x00005000, 0x00000002},
	{0x000380d0, 0x00000002},
	{0x040025e0, 0x00000002},
	{0x000075e1, 0000000000},
	{0x00000001, 0000000000},
	{0x000380e0, 0x00000002},
	{0x04002394, 0x00000002},
	{0x00005000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0x00000008, 0000000000},
	{0x00000004, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
	{0000000000, 0000000000},
};

static const u32 R300_cp_microcode[][2] = {
	{ 0x4200e000, 0000000000 },
	{ 0x4000e000, 0000000000 },
	{ 0x000000af, 0x00000008 },
	{ 0x000000b3, 0x00000008 },
	{ 0x6c5a504f, 0000000000 },
	{ 0x4f4f497a, 0000000000 },
	{ 0x5a578288, 0000000000 },
	{ 0x4f91906a, 0000000000 },
	{ 0x4f4f4f4f, 0000000000 },
	{ 0x4fe24f44, 0000000000 },
	{ 0x4f9c9c9c, 0000000000 },
	{ 0xdc4f4fde, 0000000000 },
	{ 0xa1cd4f4f, 0000000000 },
	{ 0xd29d9d9d, 0000000000 },
	{ 0x4f0f9fd7, 0000000000 },
	{ 0x000ca000, 0x00000004 },
	{ 0x000d0012, 0x00000038 },
	{ 0x0000e8b4, 0x00000004 },
	{ 0x000d0014, 0x00000038 },
	{ 0x0000e8b6, 0x00000004 },
	{ 0x000d0016, 0x00000038 },
	{ 0x0000e854, 0x00000004 },
	{ 0x000d0018, 0x00000038 },
	{ 0x0000e855, 0x00000004 },
	{ 0x000d001a, 0x00000038 },
	{ 0x0000e856, 0x00000004 },
	{ 0x000d001c, 0x00000038 },
	{ 0x0000e857, 0x00000004 },
	{ 0x000d001e, 0x00000038 },
	{ 0x0000e824, 0x00000004 },
	{ 0x000d0020, 0x00000038 },
	{ 0x0000e825, 0x00000004 },
	{ 0x000d0022, 0x00000038 },
	{ 0x0000e830, 0x00000004 },
	{ 0x000d0024, 0x00000038 },
	{ 0x0000f0c0, 0x00000004 },
	{ 0x000d0026, 0x00000038 },
	{ 0x0000f0c1, 0x00000004 },
	{ 0x000d0028, 0x00000038 },
	{ 0x0000f041, 0x00000004 },
	{ 0x000d002a, 0x00000038 },
	{ 0x0000f184, 0x00000004 },
	{ 0x000d002c, 0x00000038 },
	{ 0x0000f185, 0x00000004 },
	{ 0x000d002e, 0x00000038 },
	{ 0x0000f186, 0x00000004 },
	{ 0x000d0030, 0x00000038 },
	{ 0x0000f187, 0x00000004 },
	{ 0x000d0032, 0x00000038 },
	{ 0x0000f180, 0x00000004 },
	{ 0x000d0034, 0x00000038 },
	{ 0x0000f393, 0x00000004 },
	{ 0x000d0036, 0x00000038 },
	{ 0x0000f38a, 0x00000004 },
	{ 0x000d0038, 0x00000038 },
	{ 0x0000f38e, 0x00000004 },
	{ 0x0000e821, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x00000043, 0x00000018 },
	{ 0x00cce800, 0x00000004 },
	{ 0x001b0001, 0x00000004 },
	{ 0x08004800, 0x00000004 },
	{ 0x001b0001, 0x00000004 },
	{ 0x08004800, 0x00000004 },
	{ 0x001b0001, 0x00000004 },
	{ 0x08004800, 0x00000004 },
	{ 0x0000003a, 0x00000008 },
	{ 0x0000a000, 0000000000 },
	{ 0x02c0a000, 0x00000004 },
	{ 0x000ca000, 0x00000004 },
	{ 0x00130000, 0x00000004 },
	{ 0x000c2000, 0x00000004 },
	{ 0xc980c045, 0x00000008 },
	{ 0x2000451d, 0x00000004 },
	{ 0x0000e580, 0x00000004 },
	{ 0x000ce581, 0x00000004 },
	{ 0x08004580, 0x00000004 },
	{ 0x000ce581, 0x00000004 },
	{ 0x0000004c, 0x00000008 },
	{ 0x0000a000, 0000000000 },
	{ 0x000c2000, 0x00000004 },
	{ 0x0000e50e, 0x00000004 },
	{ 0x00032000, 0x00000004 },
	{ 0x00022056, 0x00000028 },
	{ 0x00000056, 0x00000024 },
	{ 0x0800450f, 0x00000004 },
	{ 0x0000a050, 0x00000008 },
	{ 0x0000e565, 0x00000004 },
	{ 0x0000e566, 0x00000004 },
	{ 0x00000057, 0x00000008 },
	{ 0x03cca5b4, 0x00000004 },
	{ 0x05432000, 0x00000004 },
	{ 0x00022000, 0x00000004 },
	{ 0x4ccce063, 0x00000030 },
	{ 0x08274565, 0x00000004 },
	{ 0x00000063, 0x00000030 },
	{ 0x08004564, 0x00000004 },
	{ 0x0000e566, 0x00000004 },
	{ 0x0000005a, 0x00000008 },
	{ 0x00802066, 0x00000010 },
	{ 0x00202000, 0x00000004 },
	{ 0x001b00ff, 0x00000004 },
	{ 0x01000069, 0x00000010 },
	{ 0x001f2000, 0x00000004 },
	{ 0x001c00ff, 0x00000004 },
	{ 0000000000, 0x0000000c },
	{ 0x00000085, 0x00000030 },
	{ 0x0000005a, 0x00000008 },
	{ 0x0000e576, 0x00000004 },
	{ 0x000ca000, 0x00000004 },
	{ 0x00012000, 0x00000004 },
	{ 0x00082000, 0x00000004 },
	{ 0x1800650e, 0x00000004 },
	{ 0x00092000, 0x00000004 },
	{ 0x000a2000, 0x00000004 },
	{ 0x000f0000, 0x00000004 },
	{ 0x00400000, 0x00000004 },
	{ 0x00000079, 0x00000018 },
	{ 0x0000e563, 0x00000004 },
	{ 0x00c0e5f9, 0x000000c2 },
	{ 0x0000006e, 0x00000008 },
	{ 0x0000a06e, 0x00000008 },
	{ 0x0000e576, 0x00000004 },
	{ 0x0000e577, 0x00000004 },
	{ 0x0000e50e, 0x00000004 },
	{ 0x0000e50f, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x0000007c, 0x00000018 },
	{ 0x00c0e5f9, 0x000000c2 },
	{ 0x0000007c, 0x00000008 },
	{ 0x0014e50e, 0x00000004 },
	{ 0x0040e50f, 0x00000004 },
	{ 0x00c0007f, 0x00000008 },
	{ 0x0000e570, 0x00000004 },
	{ 0x0000e571, 0x00000004 },
	{ 0x0000e572, 0x0000000c },
	{ 0x0000a000, 0x00000004 },
	{ 0x0140a000, 0x00000004 }, 
	{ 0x0000e568, 0x00000004 },
	{ 0x000c2000, 0x00000004 },
	{ 0x00000089, 0x00000018 },
	{ 0x000b0000, 0x00000004 },
	{ 0x18c0e562, 0x00000004 },
	{ 0x0000008b, 0x00000008 },
	{ 0x00c0008a, 0x00000008 },
	{ 0x000700e4, 0x00000004 },
	{ 0x00000097, 0x00000038 },
	{ 0x000ca099, 0x00000030 },
	{ 0x080045bb, 0x00000004 },
	{ 0x000c209a, 0x00000030 },
	{ 0x0800e5bc, 0000000000 },
	{ 0x0000e5bb, 0x00000004 },
	{ 0x0000e5bc, 0000000000 },
	{ 0x00120000, 0x0000000c },
	{ 0x00120000, 0x00000004 },
	{ 0x001b0002, 0x0000000c },
	{ 0x0000a000, 0x00000004 },
	{ 0x0000e821, 0x00000004 },
	{ 0x0000e800, 0000000000 },
	{ 0x0000e821, 0x00000004 },
	{ 0x0000e82e, 0000000000 },
	{ 0x02cca000, 0x00000004 },
	{ 0x00140000, 0x00000004 },
	{ 0x000ce1cc, 0x00000004 },
	{ 0x050de1cd, 0x00000004 },
	{ 0x000000a7, 0x00000020 },
	{ 0x4200e000, 0000000000 },
	{ 0x000000ae, 0x00000038 },
	{ 0x000ca000, 0x00000004 },
	{ 0x00140000, 0x00000004 },
	{ 0x000c2000, 0x00000004 },
	{ 0x00160000, 0x00000004 },
	{ 0x700ce000, 0x00000004 },
	{ 0x001400aa, 0x00000008 },
	{ 0x4000e000, 0000000000 },
	{ 0x02400000, 0x00000004 },
	{ 0x400ee000, 0x00000004 },
	{ 0x02400000, 0x00000004 },
	{ 0x4000e000, 0000000000 },
	{ 0x000c2000, 0x00000004 },
	{ 0x0240e51b, 0x00000004 },
	{ 0x0080e50a, 0x00000005 },
	{ 0x0080e50b, 0x00000005 },
	{ 0x00220000, 0x00000004 },
	{ 0x000700e4, 0x00000004 },
	{ 0x000000c1, 0x00000038 },
	{ 0x000c209a, 0x00000030 },
	{ 0x0880e5bd, 0x00000005 },
	{ 0x000c2099, 0x00000030 },
	{ 0x0800e5bb, 0x00000005 },
	{ 0x000c209a, 0x00000030 },
	{ 0x0880e5bc, 0x00000005 },
	{ 0x000000c4, 0x00000008 },
	{ 0x0080e5bd, 0x00000005 },
	{ 0x0000e5bb, 0x00000005 },
	{ 0x0080e5bc, 0x00000005 },
	{ 0x00210000, 0x00000004 },
	{ 0x02800000, 0x00000004 },
	{ 0x00c000c8, 0x00000018 },
	{ 0x4180e000, 0x00000040 },
	{ 0x000000ca, 0x00000024 },
	{ 0x01000000, 0x0000000c },
	{ 0x0100e51d, 0x0000000c },
	{ 0x000045bb, 0x00000004 },
	{ 0x000080c4, 0x00000008 },
	{ 0x0000f3ce, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x00cc2000, 0x00000004 },
	{ 0x08c053cf, 0x00000040 },
	{ 0x00008000, 0000000000 },
	{ 0x0000f3d2, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x00cc2000, 0x00000004 },
	{ 0x08c053d3, 0x00000040 },
	{ 0x00008000, 0000000000 },
	{ 0x0000f39d, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x00cc2000, 0x00000004 },
	{ 0x08c0539e, 0x00000040 },
	{ 0x00008000, 0000000000 },
	{ 0x03c00830, 0x00000004 },
	{ 0x4200e000, 0000000000 },
	{ 0x0000a000, 0x00000004 },
	{ 0x200045e0, 0x00000004 },
	{ 0x0000e5e1, 0000000000 },
	{ 0x00000001, 0000000000 },
	{ 0x000700e1, 0x00000004 },
	{ 0x0800e394, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
};

static int RADEON_READ_PLL(struct drm_device * dev, int addr)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;

	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
}

static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
{
	RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
	return RADEON_READ(RADEON_PCIE_DATA);
}

static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
{
	u32 ret;
	RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
	ret = RADEON_READ(RADEON_IGPGART_DATA);
	RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
	return ret;
}

#if RADEON_FIFO_DEBUG
static void radeon_status(drm_radeon_private_t * dev_priv)
{
	printk("%s:\n", __FUNCTION__);
	printk("RBBM_STATUS = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
	printk("CP_RB_RTPR = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
	printk("CP_RB_WTPR = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
	printk("AIC_CNTL = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
	printk("AIC_STAT = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_STAT));
	printk("AIC_PT_BASE = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
	printk("TLB_ADDR = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
	printk("TLB_DATA = 0x%08x\n",
	       (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
}
#endif

/* ================================================================
 * Engine, FIFO control
 */

static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
{
	u32 tmp;
	int i;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
	tmp |= RADEON_RB3D_DC_FLUSH_ALL;
	RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);

	for (i = 0; i < dev_priv->usec_timeout; i++) {
		if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
		      & RADEON_RB3D_DC_BUSY)) {
			return 0;
		}
		DRM_UDELAY(1);
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR("failed!\n");
	radeon_status(dev_priv);
#endif
	return -EBUSY;
}

static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
{
	int i;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	for (i = 0; i < dev_priv->usec_timeout; i++) {
		int slots = (RADEON_READ(RADEON_RBBM_STATUS)
			     & RADEON_RBBM_FIFOCNT_MASK);
		if (slots >= entries)
			return 0;
		DRM_UDELAY(1);
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR("failed!\n");
	radeon_status(dev_priv);
#endif
	return -EBUSY;
}

static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
{
	int i, ret;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	ret = radeon_do_wait_for_fifo(dev_priv, 64);
	if (ret)
		return ret;

	for (i = 0; i < dev_priv->usec_timeout; i++) {
		if (!(RADEON_READ(RADEON_RBBM_STATUS)
		      & RADEON_RBBM_ACTIVE)) {
			radeon_do_pixcache_flush(dev_priv);
			return 0;
		}
		DRM_UDELAY(1);
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR("failed!\n");
	radeon_status(dev_priv);
#endif
	return -EBUSY;
}

/* ================================================================
 * CP control, initialization
 */

/* Load the microcode for the CP */
static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
{
	int i;
	DRM_DEBUG("\n");

	radeon_do_wait_for_idle(dev_priv);

	RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);

	if (dev_priv->microcode_version == UCODE_R200) {
		DRM_INFO("Loading R200 Microcode\n");
		for (i = 0; i < 256; i++) {
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
				     R200_cp_microcode[i][1]);
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
				     R200_cp_microcode[i][0]);
		}
	} else if (dev_priv->microcode_version == UCODE_R300) {
		DRM_INFO("Loading R300 Microcode\n");
		for (i = 0; i < 256; i++) {
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
				     R300_cp_microcode[i][1]);
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
				     R300_cp_microcode[i][0]);
		}
	} else {
		for (i = 0; i < 256; i++) {
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
				     radeon_cp_microcode[i][1]);
			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
				     radeon_cp_microcode[i][0]);
		}
	}
}

/* Flush any pending commands to the CP.  This should only be used just
 * prior to a wait for idle, as it informs the engine that the command
 * stream is ending.
 */
static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
{
	DRM_DEBUG("\n");
#if 0
	u32 tmp;

	tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
	RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
#endif
}

/* Wait for the CP to go idle.
 */
int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
{
	RING_LOCALS;
	DRM_DEBUG("\n");

	BEGIN_RING(6);

	RADEON_PURGE_CACHE();
	RADEON_PURGE_ZCACHE();
	RADEON_WAIT_UNTIL_IDLE();

	ADVANCE_RING();
	COMMIT_RING();

	return radeon_do_wait_for_idle(dev_priv);
}

/* Start the Command Processor.
 */
static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
{
	RING_LOCALS;
	DRM_DEBUG("\n");

	radeon_do_wait_for_idle(dev_priv);

	RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);

	dev_priv->cp_running = 1;

	BEGIN_RING(6);

	RADEON_PURGE_CACHE();
	RADEON_PURGE_ZCACHE();
	RADEON_WAIT_UNTIL_IDLE();

	ADVANCE_RING();
	COMMIT_RING();
}

/* Reset the Command Processor.  This will not flush any pending
 * commands, so you must wait for the CP command stream to complete
 * before calling this routine.
 */
static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
{
	u32 cur_read_ptr;
	DRM_DEBUG("\n");

	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
	SET_RING_HEAD(dev_priv, cur_read_ptr);
	dev_priv->ring.tail = cur_read_ptr;
}

/* Stop the Command Processor.  This will not flush any pending
 * commands, so you must flush the command stream and wait for the CP
 * to go idle before calling this routine.
 */
static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
{
	DRM_DEBUG("\n");

	RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);

	dev_priv->cp_running = 0;
}

/* Reset the engine.  This will stop the CP if it is running.
 */
static int radeon_do_engine_reset(struct drm_device * dev)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
	DRM_DEBUG("\n");

	radeon_do_pixcache_flush(dev_priv);

	clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
	mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);

	RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
					    RADEON_FORCEON_MCLKA |
					    RADEON_FORCEON_MCLKB |
					    RADEON_FORCEON_YCLKA |
					    RADEON_FORCEON_YCLKB |
					    RADEON_FORCEON_MC |
					    RADEON_FORCEON_AIC));

	rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);

	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
					      RADEON_SOFT_RESET_CP |
					      RADEON_SOFT_RESET_HI |
					      RADEON_SOFT_RESET_SE |
					      RADEON_SOFT_RESET_RE |
					      RADEON_SOFT_RESET_PP |
					      RADEON_SOFT_RESET_E2 |
					      RADEON_SOFT_RESET_RB));
	RADEON_READ(RADEON_RBBM_SOFT_RESET);
	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
					      ~(RADEON_SOFT_RESET_CP |
						RADEON_SOFT_RESET_HI |
						RADEON_SOFT_RESET_SE |
						RADEON_SOFT_RESET_RE |
						RADEON_SOFT_RESET_PP |
						RADEON_SOFT_RESET_E2 |
						RADEON_SOFT_RESET_RB)));
	RADEON_READ(RADEON_RBBM_SOFT_RESET);

	RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
	RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);

	/* Reset the CP ring */
	radeon_do_cp_reset(dev_priv);

	/* The CP is no longer running after an engine reset */
	dev_priv->cp_running = 0;

	/* Reset any pending vertex, indirect buffers */
	radeon_freelist_reset(dev);

	return 0;
}

static void radeon_cp_init_ring_buffer(struct drm_device * dev,
				       drm_radeon_private_t * dev_priv)
{
	u32 ring_start, cur_read_ptr;
	u32 tmp;
	
	/* Initialize the memory controller. With new memory map, the fb location
	 * is not changed, it should have been properly initialized already. Part
	 * of the problem is that the code below is bogus, assuming the GART is
	 * always appended to the fb which is not necessarily the case
	 */
	if (!dev_priv->new_memmap)
		RADEON_WRITE(RADEON_MC_FB_LOCATION,
			     ((dev_priv->gart_vm_start - 1) & 0xffff0000)
			     | (dev_priv->fb_location >> 16));

#if __OS_HAS_AGP
	if (dev_priv->flags & RADEON_IS_AGP) {
		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
		RADEON_WRITE(RADEON_MC_AGP_LOCATION,
			     (((dev_priv->gart_vm_start - 1 +
				dev_priv->gart_size) & 0xffff0000) |
			      (dev_priv->gart_vm_start >> 16)));

		ring_start = (dev_priv->cp_ring->offset
			      - dev->agp->base
			      + dev_priv->gart_vm_start);
	} else
#endif
		ring_start = (dev_priv->cp_ring->offset
			      - (unsigned long)dev->sg->virtual
			      + dev_priv->gart_vm_start);

	RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);

	/* Set the write pointer delay */
	RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);

	/* Initialize the ring buffer's read and write pointers */
	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
	SET_RING_HEAD(dev_priv, cur_read_ptr);
	dev_priv->ring.tail = cur_read_ptr;

#if __OS_HAS_AGP
	if (dev_priv->flags & RADEON_IS_AGP) {
		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
			     dev_priv->ring_rptr->offset
			     - dev->agp->base + dev_priv->gart_vm_start);
	} else
#endif
	{
		struct drm_sg_mem *entry = dev->sg;
		unsigned long tmp_ofs, page_ofs;

		tmp_ofs = dev_priv->ring_rptr->offset -
				(unsigned long)dev->sg->virtual;
		page_ofs = tmp_ofs >> PAGE_SHIFT;

		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
		DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
			  (unsigned long)entry->busaddr[page_ofs],
			  entry->handle + tmp_ofs);
	}

	/* Set ring buffer size */
#ifdef __BIG_ENDIAN
	RADEON_WRITE(RADEON_CP_RB_CNTL,
		     RADEON_BUF_SWAP_32BIT |
		     (dev_priv->ring.fetch_size_l2ow << 18) |
		     (dev_priv->ring.rptr_update_l2qw << 8) |
		     dev_priv->ring.size_l2qw);
#else
	RADEON_WRITE(RADEON_CP_RB_CNTL,
		     (dev_priv->ring.fetch_size_l2ow << 18) |
		     (dev_priv->ring.rptr_update_l2qw << 8) |
		     dev_priv->ring.size_l2qw);
#endif

	/* Start with assuming that writeback doesn't work */
	dev_priv->writeback_works = 0;

	/* Initialize the scratch register pointer.  This will cause
	 * the scratch register values to be written out to memory
	 * whenever they are updated.
	 *
	 * We simply put this behind the ring read pointer, this works
	 * with PCI GART as well as (whatever kind of) AGP GART
	 */
	RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
		     + RADEON_SCRATCH_REG_OFFSET);

	dev_priv->scratch = ((__volatile__ u32 *)
			     dev_priv->ring_rptr->handle +
			     (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));

	RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);

	/* Turn on bus mastering */
	tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
	RADEON_WRITE(RADEON_BUS_CNTL, tmp);

	dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
	RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);

	dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
	RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
		     dev_priv->sarea_priv->last_dispatch);

	dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
	RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);

	radeon_do_wait_for_idle(dev_priv);

	/* Sync everything up */
	RADEON_WRITE(RADEON_ISYNC_CNTL,
		     (RADEON_ISYNC_ANY2D_IDLE3D |
		      RADEON_ISYNC_ANY3D_IDLE2D |
		      RADEON_ISYNC_WAIT_IDLEGUI |
		      RADEON_ISYNC_CPSCRATCH_IDLEGUI));

}

static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
{
	u32 tmp;

	/* Writeback doesn't seem to work everywhere, test it here and possibly
	 * enable it if it appears to work
	 */
	DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
	RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);

	for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
		if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
		    0xdeadbeef)
			break;
		DRM_UDELAY(1);
	}

	if (tmp < dev_priv->usec_timeout) {
		dev_priv->writeback_works = 1;
		DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
	} else {
		dev_priv->writeback_works = 0;
		DRM_INFO("writeback test failed\n");
	}
	if (radeon_no_wb == 1) {
		dev_priv->writeback_works = 0;
		DRM_INFO("writeback forced off\n");
	}

	if (!dev_priv->writeback_works) {
		/* Disable writeback to avoid unnecessary bus master transfers */
		RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
		RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
	}
}

/* Enable or disable IGP GART on the chip */
static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
{
	u32 temp, tmp;

	tmp = RADEON_READ(RADEON_AIC_CNTL);
	DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp);
	if (on) {
		DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
			 dev_priv->gart_vm_start,
			 (long)dev_priv->gart_info.bus_addr,
			 dev_priv->gart_size);

		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
		RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
		RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
		RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
				     dev_priv->gart_info.bus_addr);

		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);

		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
		dev_priv->gart_size = 32*1024*1024;
		RADEON_WRITE(RADEON_MC_AGP_LOCATION,
			     (((dev_priv->gart_vm_start - 1 +
			       dev_priv->gart_size) & 0xffff0000) |
			     (dev_priv->gart_vm_start >> 16)));

		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
		RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);

		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
		RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
		RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
       }
}

static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
{
	u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
	if (on) {

		DRM_DEBUG("programming pcie %08X %08lX %08X\n",
			  dev_priv->gart_vm_start,
			  (long)dev_priv->gart_info.bus_addr,
			  dev_priv->gart_size);
		RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
				  dev_priv->gart_vm_start);
		RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
				  dev_priv->gart_info.bus_addr);
		RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
				  dev_priv->gart_vm_start);
		RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
				  dev_priv->gart_vm_start +
				  dev_priv->gart_size - 1);

		RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);	/* ?? */

		RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
				  RADEON_PCIE_TX_GART_EN);
	} else {
		RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
				  tmp & ~RADEON_PCIE_TX_GART_EN);
	}
}

/* Enable or disable PCI GART on the chip */
static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
{
	u32 tmp;

	if (dev_priv->flags & RADEON_IS_IGPGART) {
		radeon_set_igpgart(dev_priv, on);
		return;
	}

	if (dev_priv->flags & RADEON_IS_PCIE) {
		radeon_set_pciegart(dev_priv, on);
		return;
	}

 	tmp = RADEON_READ(RADEON_AIC_CNTL);

	if (on) {
		RADEON_WRITE(RADEON_AIC_CNTL,
			     tmp | RADEON_PCIGART_TRANSLATE_EN);

		/* set PCI GART page-table base address
		 */
		RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);

		/* set address range for PCI address translate
		 */
		RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
		RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
			     + dev_priv->gart_size - 1);

		/* Turn off AGP aperture -- is this required for PCI GART?
		 */
		RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);	/* ?? */
		RADEON_WRITE(RADEON_AGP_COMMAND, 0);	/* clear AGP_COMMAND */