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path: root/shared-core/savage_bci.c
AgeCommit message (Expand)Author
2007-11-22drm: major whitespace/coding style realignment with kernelDave Airlie
2007-11-05drm: remove lots of spurious whitespace.Dave Airlie
2007-07-20Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.Eric Anholt
2007-07-20Replace filp in ioctl arguments with drm_file *file_priv.Eric Anholt
2007-07-20Remove DRM_ERR OS macro.Eric Anholt
2007-07-16drm: remove drm_buf_tDave Airlie
2007-07-16drm: remove drmP.h internal typedefsDave Airlie
2007-07-16drm: detypedef drm.h and fixup all problemsDave Airlie
2007-04-28remove DRM_GETSAREA and replace with drm_getsarea functionDave Airlie
2006-12-19make a savage function static from kernelDave Airlie
2006-10-16dev->agp_buffer_map is not initialized for AGP DMA on savagesMichael Karcher
2006-04-09Revert a change that accidentally went in with whitespace changes fromEric Anholt
2006-01-02whitespace cleanup/aligment with kernelDave Airlie
2005-11-08Initial port of savage to FreeBSD for the AGP and !ShadowStatus case. AddsEric Anholt
2005-09-03convert ioctl flags to use flags instead of separate intsDave Airlie
2005-08-09Make sure savage has 3rd ioctl parameterJon Smirl
2005-08-07make some functions static in the savage drm driverDave Airlie
2005-08-05Rename the driver hooks in the DRM to something a little moreEric Anholt
2005-06-28- Remove drm_initmap and replace its usage with drm_addmap. This reducesEric Anholt
2005-06-21Change initialization of savage register access to _DRM_READ_ONLY. Flags ofJon Smirl
2005-06-04Remove warnings about code mixed with declerations..Dave Airlie
2005-03-13Command DMA optimizations:Felix Kuehling
2005-03-07Tracked down random lockups related to command DMA that occurred in Quake3Felix Kuehling
2005-03-06Added support for command DMA on Savage4-based hardware. UnfortunatelyFelix Kuehling
2005-02-23Use wrap counter to extend 16-bit hardware event tags to 32-bit logicalFelix Kuehling
2005-02-05- Implement drm_initmap, and extend it with the resource number to helpEric Anholt
2005-01-15Setup MTRRs for frame buffer and aperture manually on Savage3D andFelix Kuehling
2005-01-10Only try to find the agp_buffer_map if dma_type is AGP. This is all that'sFelix Kuehling
2005-01-08Fixed off-by-one error in savage_bci_wait_fifo_shadow.Felix Kuehling
2005-01-053D scissor regs are now managed by the DRM to iterate over clip rectsFelix Kuehling
2005-01-01Completeley rewritten Savage DRM which can be considered secure (moduloFelix Kuehling
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-05 10:36:45 +0000
n class="hl opt">->dev_private; int ret; if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0, NV04_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, NULL, &chan->ramfc))) return ret; /* Setup initial state */ RAMFC_WR(DMA_PUT, chan->pushbuf_base); RAMFC_WR(DMA_GET, chan->pushbuf_base); RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4); RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | #ifdef __BIG_ENDIAN NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0)); /* enable the fifo dma operation */ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE) | (1<<chan->id)); return 0; } void nv04_fifo_destroy_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id)); nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int nv04_fifo_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t tmp; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id); NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT)); tmp = RAMFC_RD(DMA_INSTANCE); NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF); NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16); NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH)); NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE)); NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE)); /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); return 0; } int nv04_fifo_save_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t tmp; RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT); RAMFC_WR(DMA_GET, NV04_PFIFO_CACHE1_DMA_GET); tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16; tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE); RAMFC_WR(DMA_INSTANCE, tmp); RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE)); RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1)); return 0; }
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-05 10:36:44 +0000