index : renesas/drm.git	android live master
	libdrm, cloned from git://anongit.freedesktop.org/mesa/drm	Laurent Pinchart

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log msg author committer range

path: root/shared-core/radeon_cp.c

Age	Commit message (Expand)	Author
2006-09-12	drm: use radeon specific names for radeon flags	Dave Airlie
2006-07-26	Revert "Make sure busmastering gets disabled on module unload."	Michel Dänzer
2006-07-26	Bug #7629: Fix for CHIP_IS_AGP getting 'restored' with non-AGP cards	Michel Dänzer
2006-07-19	Make sure busmastering gets disabled on module unload.	Adam Jackson
2006-07-19	Use RADEON_RB3D_DSTCACHE_CTLSTAT instead of RADEON_RB2D_DSTCACHE_CTLSTAT.	Michel Dänzer
2006-07-19	Make sure CHIP_IS_AGP flag is set when not overriding to PCI mode.	Michel Dänzer
2006-07-19	When writeback isn't used, actually disable it in the hardware.	Michel Dänzer
2006-05-18	add consts to radeon microcode.	Dave Airlie
2006-03-25	radeon fix up the PCI ids for new memory map like the kernel one.. not	Dave Airlie
2006-02-25	Add all radeon pci ids known by ddx, but only r350/rv350 and below (new	Roland Scheidegger
2006-02-18	add benh's memory management patch	Dave Airlie
2006-02-18	major realigment of DRM CVS with kernel code, makes integration much easier	Dave Airlie
2005-12-28	step back one reported bugs against that patch	Dave Airlie
2005-12-16	fix radeon memory mapping from Ben Herrenschmidt	Dave Airlie
2005-11-28	Assert an MIT copyright on sis_drm.h, since one was lacking and I created	Eric Anholt
2005-11-08	Catch FreeBSD up to the pcie gart changes. Required minor modification to	Eric Anholt
2005-09-30	Add support to turn writeback off via radeon module option	Dave Airlie
2005-09-30	fix pci overriding from userspace	Dave Airlie
2005-09-25	hopefully fix server recycling on PCIE	Dave Airlie
2005-09-12	make PCI Express work on 64-bit machines, thanks to Alex Deucher (agd5f)	Dave Airlie
2005-09-11	Add GART in FB support for ati pcigart, and PCIE support for r300	Dave Airlie
2005-08-16	add Egberts 32/64 bit patch (its in kernel already...)	Dave Airlie
2005-08-05	Rename the driver hooks in the DRM to something a little more	Eric Anholt
2005-08-04	Mark some radeon init variables deprecated. These used to be passed in but	Jon Smirl
2005-07-20	Add latest r300 support from r300.sf.net CVS. Patch submitted by volodya,	Eric Anholt
2005-06-28	- Remove drm_initmap and replace its usage with drm_addmap. This reduces	Eric Anholt
2005-06-20	Change initialization of radeon register access to _DRM_READ_ONLY. Flags of	Jon Smirl
2005-06-19	Remove I2C support from radeon driver. Same support is available from	Jon Smirl
2005-04-26	Use msleep instead of tsleep to drop the DRM device lock and avoid a	Eric Anholt
2005-02-07	fix agp detection on linux	Dave Airlie
2005-02-05	- Implement drm_initmap, and extend it with the resource number to help	Eric Anholt
2005-02-01	cleanup patch from Adrian Bunk <bunk@stusta.de>	Dave Airlie
2005-01-26	(Stephane Marchesin,me) Add radeon framebuffer tiling support to radeon	Roland Scheidegger
2005-01-26	replace magic number with macro constant RADEON_ZBLOCK16	Roland Scheidegger
2004-12-08	(Stephane Marchesin, me) add hyperz support to radeon drm. Only fast z	Roland Scheidegger
2004-11-06	Commit WIP of BSD conversion to core model. Compiles for r128, radeon, but	Eric Anholt
2004-10-10	Vladimir requested support so we can at least load r300 microcode for	Dave Airlie
2004-10-06	Revert back to drm_order() instead of using kernel get_order(). The	Jon Smirl
2004-09-30	Lindent of core build. Drivers checked for no binary diffs. A few files	Jon Smirl
2004-09-30	Move things around to reduce public symbols and even out files. Switch to	Jon Smirl
2004-09-27	First check in for DRM that splits core from personality modules	Jon Smirl
2004-09-22	Remove hotplug reset support from DRM driver. This will be handled by the	Jon Smirl
2004-09-20	Remove size restriction on permanent addmap	Jon Smirl
2004-09-17	Add linux sysfs i2c support to radeon driver. This patch adds GPL licensed	Jon Smirl
2004-09-10	More general patch to mark resources in use by all DRM drivers. Makes the	Jon Smirl
2004-08-24	Merged drmfntbl-0-0-2	Dave Airlie
2004-08-23	set pointers to NULL after freeing, remove some extra debugging	Dave Airlie
2004-08-17	Merged drmfntbl-0-0-1	Dave Airlie
2004-08-17	preparation patch for radeon permanent mapping registers/framebuffer makes	Dave Airlie
2004-07-25	sync up with current 2.6 kernel bk tree - mostly __user annotations	Dave Airlie

• [next]

generated by cgit v1.2.3 (git 2.25.1) at 2025-12-08 12:09:34 +0000

/*
 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_drv.h"

/* old legacy ATI BIOS routines */

/* COMBIOS table offsets */
enum radeon_combios_table_offset
{
	/* absolute offset tables */
	COMBIOS_ASIC_INIT_1_TABLE,
	COMBIOS_BIOS_SUPPORT_TABLE,
	COMBIOS_DAC_PROGRAMMING_TABLE,
	COMBIOS_MAX_COLOR_DEPTH_TABLE,
	COMBIOS_CRTC_INFO_TABLE,
	COMBIOS_PLL_INFO_TABLE,
	COMBIOS_TV_INFO_TABLE,
	COMBIOS_DFP_INFO_TABLE,
	COMBIOS_HW_CONFIG_INFO_TABLE,
	COMBIOS_MULTIMEDIA_INFO_TABLE,
	COMBIOS_TV_STD_PATCH_TABLE,
	COMBIOS_LCD_INFO_TABLE,
	COMBIOS_MOBILE_INFO_TABLE,
	COMBIOS_PLL_INIT_TABLE,
	COMBIOS_MEM_CONFIG_TABLE,
	COMBIOS_SAVE_MASK_TABLE,
	COMBIOS_HARDCODED_EDID_TABLE,
	COMBIOS_ASIC_INIT_2_TABLE,
	COMBIOS_CONNECTOR_INFO_TABLE,
	COMBIOS_DYN_CLK_1_TABLE,
	COMBIOS_RESERVED_MEM_TABLE,
	COMBIOS_EXT_TMDS_INFO_TABLE,
	COMBIOS_MEM_CLK_INFO_TABLE,
	COMBIOS_EXT_DAC_INFO_TABLE,
	COMBIOS_MISC_INFO_TABLE,
	COMBIOS_CRT_INFO_TABLE,
	COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
	COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
	COMBIOS_FAN_SPEED_INFO_TABLE,
	COMBIOS_OVERDRIVE_INFO_TABLE,
	COMBIOS_OEM_INFO_TABLE,
	COMBIOS_DYN_CLK_2_TABLE,
	COMBIOS_POWER_CONNECTOR_INFO_TABLE,
	COMBIOS_I2C_INFO_TABLE,
	/* relative offset tables */
	COMBIOS_ASIC_INIT_3_TABLE,	/* offset from misc info */
	COMBIOS_ASIC_INIT_4_TABLE,	/* offset from misc info */
	COMBIOS_ASIC_INIT_5_TABLE,	/* offset from misc info */
	COMBIOS_RAM_RESET_TABLE,	/* offset from mem config */
	COMBIOS_POWERPLAY_INFO_TABLE,	/* offset from mobile info */
	COMBIOS_GPIO_INFO_TABLE,	/* offset from mobile info */
	COMBIOS_LCD_DDC_INFO_TABLE,	/* offset from mobile info */
	COMBIOS_TMDS_POWER_TABLE,	/* offset from mobile info */
	COMBIOS_TMDS_POWER_ON_TABLE,	/* offset from tmds power */
	COMBIOS_TMDS_POWER_OFF_TABLE,	/* offset from tmds power */
};

enum radeon_combios_ddc
{
    DDC_NONE_DETECTED,
    DDC_MONID,
    DDC_DVI,
    DDC_VGA,
    DDC_CRT2,
    DDC_LCD,
    DDC_GPIO,
};

enum radeon_combios_connector
{
    CONNECTOR_NONE_LEGACY,
    CONNECTOR_PROPRIETARY_LEGACY,
    CONNECTOR_CRT_LEGACY,
    CONNECTOR_DVI_I_LEGACY,
    CONNECTOR_DVI_D_LEGACY,
    CONNECTOR_CTV_LEGACY,
    CONNECTOR_STV_LEGACY,
    CONNECTOR_UNSUPPORTED_LEGACY
};

static uint16_t combios_get_table_offset(struct drm_device *dev, enum radeon_combios_table_offset table)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	int rev;
	uint16_t offset = 0, check_offset;

	switch (table) {
	/* absolute offset tables */
	case COMBIOS_ASIC_INIT_1_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0xc);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_BIOS_SUPPORT_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x14);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_DAC_PROGRAMMING_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2a);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MAX_COLOR_DEPTH_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2c);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_CRTC_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_PLL_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x30);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_TV_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x32);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_DFP_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_HW_CONFIG_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x36);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MULTIMEDIA_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x38);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_TV_STD_PATCH_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x3e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_LCD_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x40);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MOBILE_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x42);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_PLL_INIT_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x46);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MEM_CONFIG_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x48);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_SAVE_MASK_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4a);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_HARDCODED_EDID_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4c);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_ASIC_INIT_2_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_CONNECTOR_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x50);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_DYN_CLK_1_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x52);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_RESERVED_MEM_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x54);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_EXT_TMDS_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x58);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MEM_CLK_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5a);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_EXT_DAC_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5c);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MISC_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_CRT_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x60);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x62);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x64);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_FAN_SPEED_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x66);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_OVERDRIVE_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x68);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_OEM_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6a);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_DYN_CLK_2_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6c);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_I2C_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x70);
		if (check_offset)
			offset = check_offset;
		break;
	/* relative offset tables */
	case COMBIOS_ASIC_INIT_3_TABLE:	/* offset from misc info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = radeon_bios8(dev_priv, check_offset);
			if (rev > 0) {
				check_offset = radeon_bios16(dev_priv, check_offset + 0x3);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_ASIC_INIT_4_TABLE:	/* offset from misc info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = radeon_bios8(dev_priv, check_offset);
			if (rev > 0) {
				check_offset = radeon_bios16(dev_priv, check_offset + 0x5);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_ASIC_INIT_5_TABLE:	/* offset from misc info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = radeon_bios8(dev_priv, check_offset);
			if (rev == 2) {
				check_offset = radeon_bios16(dev_priv, check_offset + 0x9);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_RAM_RESET_TABLE:	/* offset from mem config */
		check_offset = combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		if (check_offset) {
			while (radeon_bios8(dev_priv, check_offset++));
			check_offset += 2;
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_POWERPLAY_INFO_TABLE:	/* offset from mobile info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x11);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_GPIO_INFO_TABLE:	/* offset from mobile info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x13);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_LCD_DDC_INFO_TABLE:	/* offset from mobile info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x15);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_TMDS_POWER_TABLE:	        /* offset from mobile info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x17);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_TMDS_POWER_ON_TABLE:	/* offset from tmds power */
		check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x2);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_TMDS_POWER_OFF_TABLE:	/* offset from tmds power */
		check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x4);
			if (check_offset)
				offset = check_offset;
		}
		break;
	default:
		break;
	}

	return offset;

}

struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
{
	struct radeon_i2c_bus_rec i2c;

	i2c.hw_line = 0;
	i2c.hw_capable = false; // actually depends on chip
	i2c.mask_clk_mask = RADEON_GPIO_EN_1;
	i2c.mask_data_mask = RADEON_GPIO_EN_0;
	i2c.a_clk_mask = RADEON_GPIO_A_1;
	i2c.a_data_mask = RADEON_GPIO_A_0;
	i2c.put_clk_mask = RADEON_GPIO_EN_1;
	i2c.put_data_mask = RADEON_GPIO_EN_0;
	i2c.get_clk_mask = RADEON_GPIO_Y_1;
	i2c.get_data_mask = RADEON_GPIO_Y_0;
	if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
	    (ddc_line == RADEON_MDGPIO_EN_REG)) {
		i2c.mask_clk_reg = ddc_line;
		i2c.mask_data_reg = ddc_line;
		i2c.a_clk_reg = ddc_line;
		i2c.a_data_reg = ddc_line;
		i2c.put_clk_reg = ddc_line;
		i2c.put_data_reg = ddc_line;
		i2c.get_clk_reg = ddc_line + 4;
		i2c.get_data_reg = ddc_line + 4;
	} else {
		i2c.mask_clk_reg = ddc_line;
		i2c.mask_data_reg = ddc_line;
		i2c.a_clk_reg = ddc_line;
		i2c.a_data_reg = ddc_line;
		i2c.put_clk_reg = ddc_line;
		i2c.put_data_reg = ddc_line;
		i2c.get_clk_reg = ddc_line;
		i2c.get_data_reg = ddc_line;
	}

	if (ddc_line)
		i2c.valid = true;
	else
		i2c.valid = false;

	return i2c;
}

bool radeon_combios_get_clock_info(struct drm_device *dev)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct radeon_mode_info *mode_info = &dev_priv->mode_info;
	uint16_t pll_info;
	struct radeon_pll *p1pll = &mode_info->p1pll;
	struct radeon_pll *p2pll = &mode_info->p2pll;
	struct radeon_pll *spll = &mode_info->spll;
	struct radeon_pll *mpll = &mode_info->mpll;
	int8_t rev;
	uint16_t sclk, mclk;

	pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
	if (pll_info) {
		rev = radeon_bios8(dev_priv, pll_info);

		/* pixel clocks */
		p1pll->reference_freq = radeon_bios16(dev_priv, pll_info + 0xe);
		p1pll->reference_div = radeon_bios16(dev_priv, pll_info + 0x10);
		p1pll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x12);
		p1pll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x16);

		if (rev > 9) {
			p1pll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x36);
			p1pll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x3a);
		} else {
			p1pll->pll_in_min = 40;
			p1pll->pll_in_max = 500;
		}
		*p2pll = *p1pll;

		/* system clock */
		spll->reference_freq = radeon_bios16(dev_priv, pll_info + 0x1a);
		spll->reference_div = radeon_bios16(dev_priv, pll_info + 0x1c);
		spll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x1e);
		spll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x22);

		if (rev > 10) {
			spll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x48);
			spll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x4c);
		} else {
			/* ??? */
			spll->pll_in_min = 40;
			spll->pll_in_max = 500;
		}

		/* memory clock */
		mpll->reference_freq = radeon_bios16(dev_priv, pll_info + 0x26);
		mpll->reference_div = radeon_bios16(dev_priv, pll_info + 0x28);
		mpll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x2a);
		mpll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x2e);

		if (rev > 10) {
			mpll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x5a);
			mpll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x5e);
		} else {
			/* ??? */
			mpll->pll_in_min = 40;
			mpll->pll_in_max = 500;
		}

		/* default sclk/mclk */
		sclk = radeon_bios16(dev_priv, pll_info + 0x8);
		mclk = radeon_bios16(dev_priv, pll_info + 0xa);
		if (sclk == 0)
			sclk = 200;
		if (mclk == 0)
			mclk = 200;

		mode_info->sclk = sclk;
		mode_info->mclk = mclk;

		return true;
	}
	return false;
}

bool radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint16_t dac_info;
	uint8_t rev, bg, dac;

	/* check CRT table */
	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
	if (dac_info) {
		rev = radeon_bios8(dev_priv, dac_info) & 0x3;
		if (rev < 2) {
			bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0x2) >> 4) & 0xf;
			encoder->ps2_pdac_adj = (bg << 8) | (dac);

			return true;
		} else {
			bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
			encoder->ps2_pdac_adj = (bg << 8) | (dac);

			return true;
		}

	}

	return false;
}

bool radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint16_t dac_info;
	uint8_t rev, bg, dac;

	/* first check TV table */
	dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
	if (dac_info) {
		rev = radeon_bios8(dev_priv, dac_info + 0x3);
		if (rev > 4) {
			bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
			encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);

			bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0xf) & 0xf;
			encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);

			bg = radeon_bios8(dev_priv, dac_info + 0x10) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0x11) & 0xf;
			encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);

			return true;
		} else if (rev > 1) {
			bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0xc) >> 4) & 0xf;
			encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);

			bg = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0xd) >> 4) & 0xf;
			encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);

			bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0xe) >> 4) & 0xf;
			encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);

			return true;
		}
	}

	/* then check CRT table */
	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
	if (dac_info) {
		rev = radeon_bios8(dev_priv, dac_info) & 0x3;
		if (rev < 2) {
			bg = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0x3) >> 4) & 0xf;
			encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
			encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
			encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;

			return true;
		} else {
			bg = radeon_bios8(dev_priv, dac_info + 0x4) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0x5) & 0xf;
			encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
			encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
			encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;

			return true;
		}

	}

	return false;