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path: root/shared-core/nouveau_reg.h
AgeCommit message (Expand)Author
2008-04-05nv50: primitive i2c interrupt handlerMaarten Maathuis
2008-04-03nv50: primitive display interrupt handler.Maarten Maathuis
2008-02-16nv40: actually init all tile regs.Ben Skeggs
2008-02-02nouveau: NV40 can/should now be able to run after the blob.Maarten Maathuis
2008-01-04[PATCH] nouveau: reset AGP on init for < nv40Stuart Bennett
2007-11-14nouveau: Also wait until CACHE1 gets emptied.Ben Skeggs
2007-11-14nouveau: store user control reg offsets in channel structBen Skeggs
2007-11-14nouveau: funcs to determine active channel on PFIFO.Ben Skeggs
2007-11-05drm: remove lots of spurious whitespace.Dave Airlie
2007-10-10nouveau : nv10 and nv04 PGRAPH_NSTATUS are differentMatthieu Castet
2007-10-10nouveau: try to fix big endian.Stephane Marchesin
2007-09-30nouveau : nv20_graph replace nouveau_graph_wait_idle by nouveau_wait_for_idleMatthieu Castet
2007-09-10nouveau: nv10: add combiner registersPatrice Mandin
2007-08-26nouveau : add NV04_PGRAPH_TRAPPED_ADDR definitionMatthieu Castet
2007-08-22nouveau/nv40: Dump extra info on ucode state if ctx switch fails.Ben Skeggs
2007-08-10nouveau/nv50: demagic instmem setup.Ben Skeggs
2007-07-18nouveau: Add bitfield names for NSOURCE and NSTATUS.Pekka Paalanen
2007-07-18nouveau: Replace 0x00400104 and 0x00400108 with names.Pekka Paalanen
2007-07-11Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.Arthur Huillet
2007-07-09nouveau/nv50: Initial channel/object supportBen Skeggs
2007-06-28nouveau: name some regsBen Skeggs
2007-06-24nouveau: NV04 PFIFO engtab functionsBen Skeggs
2007-06-24nouveau: NV4X PFIFO engtab functionsBen Skeggs
2007-04-06nouveau: make a note about a bit that breaks some cardsBen Skeggs
2007-03-26nouveau: move card initialisation into the drmBen Skeggs
2007-03-07nouveau: remove a hack that's not needed since the last interface change.Ben Skeggs
2007-02-28nouveau: intrusive drm interface changesBen Skeggs
2007-02-06nouveau: more work on the nv04 context switch code.Stephane Marchesin
2007-02-03nouveau: cleanup the nv04 pgraph save/restore mechanism.Stephane Marchesin
2007-02-03nouveau: rename registers to their proper names.Stephane Marchesin
2007-02-03nouveau: add NV04 registers required for PGRAPH context switching.Stephane Marchesin
2007-01-26nouveau: add extra pgraph registersPatrice Mandin
2007-01-13nouveau: nv20 graph ctx switch.Matthieu Castet
2007-01-13nouveau: add and indent pgraph regsMatthieu Castet
2007-01-13nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.Stephane Marchesin
2007-01-12nouveau: get nv30 context switching to work.Jeremy Kolb
2007-01-06nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.Ben Skeggs
2007-01-05Cleanup the nv04 fifo code a bit.Stephane Marchesin
2006-11-28For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.Matthieu Castet
2006-11-14Completely untested NV10/20/30 FIFO context switching changes.Ben Skeggs
2006-11-14Restructure initialisation a bit.Ben Skeggs
2006-11-06fixup fifo size so it is page alignedDave Airlie
2006-10-18Remove hack which delays activation of a additional channel. The previously ...Ben Skeggs
2006-10-17Useful output on a FIFO error interrupt.Ben Skeggs
2006-10-17Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ...Ben Skeggs
2006-10-17Some info on NV40's RAMFCBen Skeggs
2006-10-12Still more work on the context switching code.Stephane Marchesin
2006-10-11Context switching work.Stephane Marchesin
2006-08-27initial import of nouveau code from nouveau CVSDave Airlie
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-22 06:16:22 +0000
class="hl kwb">int y, int cpp, uint32_t *tiling_mode, unsigned long *pitch, unsigned long flags) { return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp, tiling_mode, pitch, flags); } void drm_intel_bo_reference(drm_intel_bo *bo) { bo->bufmgr->bo_reference(bo); } void drm_intel_bo_unreference(drm_intel_bo *bo) { if (bo == NULL) return; bo->bufmgr->bo_unreference(bo); } int drm_intel_bo_map(drm_intel_bo *buf, int write_enable) { return buf->bufmgr->bo_map(buf, write_enable); } int drm_intel_bo_unmap(drm_intel_bo *buf) { return buf->bufmgr->bo_unmap(buf); } int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, unsigned long size, const void *data) { int ret; if (bo->bufmgr->bo_subdata) return bo->bufmgr->bo_subdata(bo, offset, size, data); if (size == 0 || data == NULL) return 0; ret = drm_intel_bo_map(bo, 1); if (ret) return ret; memcpy((unsigned char *)bo->virtual + offset, data, size); drm_intel_bo_unmap(bo); return 0; } int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, unsigned long size, void *data) { int ret; if (bo->bufmgr->bo_subdata) return bo->bufmgr->bo_get_subdata(bo, offset, size, data); if (size == 0 || data == NULL) return 0; ret = drm_intel_bo_map(bo, 0); if (ret) return ret; memcpy(data, (unsigned char *)bo->virtual + offset, size); drm_intel_bo_unmap(bo); return 0; } void drm_intel_bo_wait_rendering(drm_intel_bo *bo) { bo->bufmgr->bo_wait_rendering(bo); } void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr) { bufmgr->destroy(bufmgr); } int drm_intel_bo_exec(drm_intel_bo *bo, int used, drm_clip_rect_t * cliprects, int num_cliprects, int DR4) { return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4); } void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug) { bufmgr->debug = enable_debug; } int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count) { return bo_array[0]->bufmgr->check_aperture_space(bo_array, count); } int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name) { if (bo->bufmgr->bo_flink) return bo->bufmgr->bo_flink(bo, name); return -ENODEV; } int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, drm_intel_bo *target_bo, uint32_t target_offset, uint32_t read_domains, uint32_t write_domain) { return bo->bufmgr->bo_emit_reloc(bo, offset, target_bo, target_offset, read_domains, write_domain); } int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment) { if (bo->bufmgr->bo_pin) return bo->bufmgr->bo_pin(bo, alignment); return -ENODEV; } int drm_intel_bo_unpin(drm_intel_bo *bo) { if (bo->bufmgr->bo_unpin) return bo->bufmgr->bo_unpin(bo); return -ENODEV; } int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, uint32_t stride) { if (bo->bufmgr->bo_set_tiling) return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride); *tiling_mode = I915_TILING_NONE; return 0; } int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, uint32_t * swizzle_mode) { if (bo->bufmgr->bo_get_tiling) return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); *tiling_mode = I915_TILING_NONE; *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; return 0; } int drm_intel_bo_disable_reuse(drm_intel_bo *bo) { if (bo->bufmgr->bo_disable_reuse) return bo->bufmgr->bo_disable_reuse(bo); return 0; } int drm_intel_bo_busy(drm_intel_bo *bo) { if (bo->bufmgr->bo_busy) return bo->bufmgr->bo_busy(bo); return 0; } int drm_intel_bo_madvise(drm_intel_bo *bo, int madv) { if (bo->bufmgr->bo_madvise) return bo->bufmgr->bo_madvise(bo, madv); return -1; } int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) { return bo->bufmgr->bo_references(bo, target_bo); } int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id) { if (bufmgr->get_pipe_from_crtc_id) return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id); return -1; }
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-22 06:16:21 +0000