index : renesas/drm.git	android live master
	libdrm, cloned from git://anongit.freedesktop.org/mesa/drm	Laurent Pinchart

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log msg author committer range

path: root/shared-core/i915_dma.c

Age	Commit message (Expand)	Author
2007-09-28	Revert drm_i915_flip_t braindamage	Jesse Barnes
2007-09-11	Disambiguate planes & pipes for swap operations	Jesse Barnes
2007-08-11	i915: i965 non-secure batchbuffer bit has moved.	Dave Airlie
2007-07-20	Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.	Eric Anholt
2007-07-20	Replace filp in ioctl arguments with drm_file *file_priv.	Eric Anholt
2007-07-20	Remove DRM_ERR OS macro.	Eric Anholt
2007-07-19	Merge branch 'origin'	Eric Anholt
2007-07-18	fix some missing whitespace/tab	Dave Airlie
2007-07-16	Fix FreeBSD build.	Eric Anholt
2007-07-16	drm: remove drmP.h internal typedefs	Dave Airlie
2007-07-16	drm: detypedef drm.h and fixup all problems	Dave Airlie
2007-06-15	i915: Fix handling of breadcrumb counter wraparounds.	Michel Dänzer
2007-06-05	Add support for the G33, Q33, and Q35 chipsets.	Wang Zhenyu
2007-05-31	i915: Add support for 965GME/GLE chip.	Wang Zhenyu
2007-05-29	Update a bunch of FreeBSD port code.	Jung-uk Kim
2007-05-10	Allow vblank interrupts to remain disabled across VT switch.	Keith Packard
2007-04-28	remove DRM_GETSAREA and replace with drm_getsarea function	Dave Airlie
2007-04-06	i915: use breadcrumb macro everywhere	Dave Airlie
2007-03-30	Merge branch 'crestline-qa', adding support for the 965GM chipset.	Eric Anholt
2007-03-27	drm/i915: set the bo up at firstopen time not after DMA init	Dave Airlie
2007-03-12	Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline	Nian Wu
2007-02-25	Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline	Nian Wu
2007-02-15	Initial support for fence object classes.	Thomas Hellstrom
2007-02-13	i915: Add 965GM pci id update	Wang Zhenyu
2007-03-10	i915: Only wait for pending flips before asynchronous flips again.	Michel Dänzer
2007-03-09	i915: Do not wait for pending flips on both pipes at the same time.	Michel Dänzer
2007-02-28	i915: Eliminate dev_priv->current_page.	Michel Dänzer
2007-02-28	i915: Only clean up page flipping when the last client goes away, not any one.	Michel Dänzer
2007-02-28	i915: Don't emit waits for pending flips before emitting synchronous flips.	Michel Dänzer
2007-02-22	i915: Add support for scheduled buffer swaps to be done as flips.	Michel Dänzer
2007-02-19	i915: Improved page flipping support, including triple buffering.	Michel Dänzer
2007-02-19	i915: Page flipping enhancements.	Michel Dänzer
2007-02-19	i915: Unify breadcrumb emission.	Michel Dänzer
2007-02-07	Warning fix: correct type of i915_mmio argument.	Eric Anholt
2007-01-12	Delay for a usec while spinning waiting for ring buffer space.	Haihao Xiang
2007-01-06	i915: ARB_Occlusion_query(MMIO ioctl) support.	Zou Nan hai
2006-12-19	fixup i915 return values from kernel	Dave Airlie
2006-10-18	Merging drm-ttm-0-2-branch	Thomas Hellstrom
2006-10-17	Extend generality for more memory types.	Thomas Hellstrom
2006-09-29	i915: Add ioctl for scheduling buffer swaps at vertical blanks.	Michel Dänzer
2006-09-28	i915: Add ioctl for scheduling buffer swaps at vertical blanks.	Michel Dänzer
2006-09-06	Put the PCI device/vendor id in the drm_device_t.	Eric Anholt
2006-08-31	Validation and fencing.	Thomas Hellstrom
2006-08-29	Checkpoint commit. Buffer object flags and IOCTL argument list.	Thomas Hellstrom
2006-08-27	Initialize i915 saved flush flags.	Thomas Hellstrom
2006-08-21	i915 fence object driver implementing 2 fence object types:	Thomas Hellstrom
2006-08-10	i965 code and Linux coding style < 0	Dave Airlie
2006-08-08	Add support for Intel i965G chipsets.	Alan Hourihane
2006-06-19	Add i915 ioctls to configure pipes for vblank interrupt.	Keith Packard
2006-01-24	fix an error message typo Unkown -> Unknown	Alan Hourihane

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generated by cgit v1.2.3 (git 2.25.1) at 2025-12-08 12:18:39 +0000

/*
 * Copyright (C) 2005-2006 Erik Waling
 * Copyright (C) 2006 Stephane Marchesin
 * Copyright (C) 2007-2008 Stuart Bennett
 * Copyright (C) 2008 Maarten Maathuis.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <asm/byteorder.h>
#include "nouveau_bios.h"
#include "nouveau_drv.h"

/* returns true if it mismatches */
static bool nv_checksum(const uint8_t *data, unsigned int length)
{
	/* there's a few checksums in the BIOS, so here's a generic checking function */
	int i;
	uint8_t sum = 0;

	for (i = 0; i < length; i++)
		sum += data[i];

	if (sum)
		return true;

	return false;
}

static int nv_valid_bios(struct drm_device *dev, uint8_t *data)
{
	/* check for BIOS signature */
	if (!(data[0] == 0x55 && data[1] == 0xAA)) {
		DRM_ERROR("BIOS signature not found.\n");
		return 0;
	}

	if (nv_checksum(data, data[2] * 512)) {
		DRM_ERROR("BIOS checksum invalid.\n");
		return 1;
	}

	return 2;
}

static void nv_shadow_bios_rom(struct drm_device *dev, uint8_t *data)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	/* enable access to rom */
	NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);

	/* This is also valid for pre-NV50, it just happened to be the only define already present. */
	for (i=0; i < NV50_PROM__ESIZE; i++) {
		/* Appearantly needed for a 6600GT/6800LE bug. */
		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
	}

	/* disable access to rom */
	NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
}

static void nv_shadow_bios_ramin(struct drm_device *dev, uint8_t *data)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t old_bar0_pramin = 0;
	int i;

	/* Move the bios copy to the start of ramin? */
	if (dev_priv->card_type >= NV_50) {
		uint32_t vbios_vram = (NV_READ(0x619f04) & ~0xff) << 8;

		if (!vbios_vram)
			vbios_vram = (NV_READ(0x1700) << 16) + 0xf0000;

		old_bar0_pramin = NV_READ(0x1700);
		NV_WRITE(0x1700, vbios_vram >> 16);
	}

	for (i=0; i < NV50_PROM__ESIZE; i++)
		data[i] = DRM_READ8(dev_priv->mmio, NV04_PRAMIN + i);

	if (dev_priv->card_type >= NV_50)
		NV_WRITE(0x1700, old_bar0_pramin);
}

static bool nv_shadow_bios(struct drm_device *dev, uint8_t *data)
{
	nv_shadow_bios_rom(dev, data);
	if (nv_valid_bios(dev, data) == 2)
		return true;

	nv_shadow_bios_ramin(dev, data);
	if (nv_valid_bios(dev, data))
		return true;

	return false;
}

struct bit_entry {
	uint8_t id[2];
	uint16_t length;
	uint16_t offset;
};

static int parse_bit_A_tbl_entry(struct drm_device *dev, struct bios *bios, struct bit_entry *bitentry)
{
	/* Parses the load detect value table.
	 *
	 * Starting at bitentry->offset:
	 *
	 * offset + 0 (16 bits): table pointer
	 */

	uint16_t load_table_pointer;

	if (bitentry->length != 3) {
		DRM_ERROR("Do not understand BIT loadval table\n");
		return 0;
	}

	load_table_pointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));

	if (load_table_pointer == 0x0) {
		DRM_ERROR("Pointer to loadval table invalid\n");
		return 0;
	}

	/* Some kind of signature */
	if (bios->data[load_table_pointer] != 16 || bios->data[load_table_pointer + 1] != 4 || 
		bios->data[load_table_pointer + 2] != 4 || bios->data[load_table_pointer + 3] != 2)
		return 0;

	bios->dactestval = le32_to_cpu(*((uint32_t *)&bios->data[load_table_pointer + 4])) & 0x3FF;

	return 1;
}

static int parse_bit_C_tbl_entry(struct drm_device *dev, struct bios *bios, struct bit_entry *bitentry)
{
	/* offset + 8  (16 bits): PLL limits table pointer
	 *
	 * There's more in here, but that's unknown.
	 */

	if (bitentry->length < 10) {
		DRM_ERROR("Do not understand BIT C table\n");
		return 0;
	}

	bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));

	return 1;
}

static void parse_bit_structure(struct drm_device *dev, struct bios *bios, const uint16_t bitoffset)
{
	int entries = bios->data[bitoffset + 4];
	/* parse i first, I next (which needs C & M before it), and L before D */
	char parseorder[] = "iCMILDTA";
	struct bit_entry bitentry;
	int i, j, offset;

	for (i = 0; i < sizeof(parseorder); i++) {
		for (j = 0, offset = bitoffset + 6; j < entries; j++, offset += 6) {
			bitentry.id[0] = bios->data[offset];
			bitentry.id[1] = bios->data[offset + 1];
			bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
			bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));

			if (bitentry.id[0] != parseorder[i])
				continue;

			switch (bitentry.id[0]) {
			case 'A':
				parse_bit_A_tbl_entry(dev, bios, &bitentry);
				break;
			case 'C':
				parse_bit_C_tbl_entry(dev, bios, &bitentry);
				break;
			}
		}
	}
}

static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
{
	int i, j;

	for (i = 0; i <= (n - len); i++) {
		for (j = 0; j < len; j++)
			if (data[i + j] != str[j])
				break;
		if (j == len)
			return i;
	}

	return 0;
}

static void
read_dcb_i2c_entry(struct drm_device *dev, uint8_t dcb_version, uint16_t i2ctabptr, int index)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct bios *bios = &dev_priv->bios;
	uint8_t *i2ctable = &bios->data[i2ctabptr];
	uint8_t headerlen = 0;
	int i2c_entries = MAX_NUM_DCB_ENTRIES;
	int recordoffset = 0, rdofs = 1, wrofs = 0;

	if (!i2ctabptr)
		return;

	if (dcb_version >= 0x30) {
		if (i2ctable[0] != dcb_version) /* necessary? */
			DRM_ERROR(
				   "DCB I2C table version mismatch (%02X vs %02X)\n",
				   i2ctable[0], dcb_version);
		headerlen = i2ctable[1];
		i2c_entries = i2ctable[2];

		/* same address offset used for read and write for C51 and G80 */
		if (bios->chip_version == 0x51)
			rdofs = wrofs = 1;
		if (i2ctable[0] >= 0x40)
			rdofs = wrofs = 0;
	}
	/* it's your own fault if you call this function on a DCB 1.1 BIOS --
	 * the test below is for DCB 1.2
	 */
	if (dcb_version < 0x14) {
		recordoffset = 2;
		rdofs = 0;
		wrofs = 1;
	}

	if (index == 0xf)
		return;
	if (index > i2c_entries) {
		DRM_ERROR(
			   "DCB I2C index too big (%d > %d)\n",
			   index, i2ctable[2]);
		return;
	}
	if (i2ctable[headerlen + 4 * index + 3] == 0xff) {
		DRM_ERROR(
			   "DCB I2C entry invalid\n");
		return;
	}

	if (bios->chip_version == 0x51) {
		int port_type = i2ctable[headerlen + 4 * index + 3];

		if (port_type != 4)
			DRM_ERROR(
				   "DCB I2C table has port type %d\n", port_type);
	}
	if (i2ctable[0] >= 0x40) {
		int port_type = i2ctable[headerlen + 4 * index + 3];

		if (port_type != 5)
			DRM_ERROR(
				   "DCB I2C table has port type %d\n", port_type);
	}

	dev_priv->dcb_table.i2c_read[index] = i2ctable[headerlen + recordoffset + rdofs + 4 * index];
	dev_priv->dcb_table.i2c_write[index] = i2ctable[headerlen + recordoffset + wrofs + 4 * index];
}

static bool
parse_dcb_entry(struct drm_device *dev, int index, uint8_t dcb_version, uint16_t i2ctabptr, uint32_t conn, uint32_t conf)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct dcb_entry *entry = &dev_priv->dcb_table.entry[index];

	memset(entry, 0, sizeof (struct dcb_entry));

	entry->index = index;
	/* safe defaults for a crt */
	entry->type = 0;
	entry->i2c_index = 0;
	entry->heads = 1;
	entry->bus = 0;
	entry->location = LOC_ON_CHIP;
	entry->or = 1;
	entry->duallink_possible = false;

	if (dcb_version >= 0x20) {
		entry->type = conn & 0xf;
		entry->i2c_index = (conn >> 4) & 0xf;
		entry->heads = (conn >> 8) & 0xf;
		entry->bus = (conn >> 16) & 0xf;
		entry->location = (conn >> 20) & 0xf;
		entry->or = (conn >> 24) & 0xf;
		/* Normal entries consist of a single bit, but dual link has the
		 * adjacent more significant bit set too
		 */
		if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
			entry->duallink_possible = true;

		switch (entry->type) {
		case DCB_OUTPUT_LVDS:
			{
			uint32_t mask;
			if (conf & 0x1)
				entry->lvdsconf.use_straps_for_mode = true;
			if (dcb_version < 0x22) {
				mask = ~0xd;
				/* both 0x4 and 0x8 show up in v2.0 tables; assume they mean
				 * the same thing, which is probably wrong, but might work */
				if (conf & 0x4 || conf & 0x8)
					entry->lvdsconf.use_power_scripts = true;
			} else {
				mask = ~0x5;
				if (conf & 0x4)
					entry->lvdsconf.use_power_scripts = true;
			}
			if (conf & mask) {
				if (dcb_version < 0x40) { /* we know g80 cards have unknown bits */
					DRM_ERROR("Unknown LVDS configuration bits, please report\n");
					/* cause output setting to fail, so message is seen */
					dev_priv->dcb_table.entries = 0;
					return false;
				}
			}
			break;
			}
		case 0xe:
			/* weird type that appears on g80 mobile bios; nv driver treats it as a terminator */
			return false;
		}
		read_dcb_i2c_entry(dev, dcb_version, i2ctabptr, entry->i2c_index);
	} else if (dcb_version >= 0x14 ) {