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path: root/linux-core/i915_fence.c
AgeCommit message (Expand)Author
2007-09-25Merge branch 'master' into pre-superioctl-branchThomas Hellstrom
2007-09-25drm/ttm: fixup fence class naming and interfacesDave Airlie
2007-09-22Add fence error member.Thomas Hellstrom
2007-07-16drm: detypedef ttm/bo/fence codeDave Airlie
2007-07-16drm: remove drmP.h internal typedefsDave Airlie
2007-06-15i915: Fix handling of breadcrumb counter wraparounds.Michel Dänzer
2007-02-22Some fencing cleanup.Thomas Hellstrom
2007-02-15Initial support for fence object classes.Thomas Hellstrom
2007-02-14Remove an intel-specific hack and replace it with a fence driver callback.Thomas Hellstrom
2006-10-19Make sure delayed delete list is empty on lastclose.Thomas Hellstrom
2006-10-17Lindent.Thomas Hellstrom
2006-09-25Add /proc filesystem buffer / fence object accounting.Thomas Hellstrom
2006-09-18Alternative implementation of page table zeroing using zap page_range.Thomas Hellstrom
2006-09-15Allow a "native type" to be associated with a fence sequence.Thomas Hellstrom
2006-09-15Some bugfixes.Thomas Hellstrom
2006-09-08Various bugfixes.Thomas Hellstrom
2006-09-05i915: Only turn on user IRQs when they are needed.Thomas Hellstrom
2006-08-31Validation and fencing.Thomas Hellstrom
2006-08-29Checkpoint commit. Buffer object flags and IOCTL argument list.Thomas Hellstrom
2006-08-21i915 fence object driver implementing 2 fence object types:Thomas Hellstrom
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-11 02:33:00 +0000
Software. */ /* * Authors: * Jérôme Glisse <jglisse@redhat.com> */ #ifndef RADEON_SURFACE_H #define RADEON_SURFACE_H /* Note : * * For texture array, the n layer are stored one after the other within each * mipmap level. 0 value for field than can be hint is always valid. */ #define RADEON_SURF_MAX_LEVEL 32 #define RADEON_SURF_TYPE_MASK 0xFF #define RADEON_SURF_TYPE_SHIFT 0 #define RADEON_SURF_TYPE_1D 0 #define RADEON_SURF_TYPE_2D 1 #define RADEON_SURF_TYPE_3D 2 #define RADEON_SURF_TYPE_CUBEMAP 3 #define RADEON_SURF_TYPE_1D_ARRAY 4 #define RADEON_SURF_TYPE_2D_ARRAY 5 #define RADEON_SURF_MODE_MASK 0xFF #define RADEON_SURF_MODE_SHIFT 8 #define RADEON_SURF_MODE_LINEAR 0 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1 #define RADEON_SURF_MODE_1D 2 #define RADEON_SURF_MODE_2D 3 #define RADEON_SURF_SCANOUT (1 << 16) #define RADEON_SURF_ZBUFFER (1 << 17) #define RADEON_SURF_SBUFFER (1 << 18) #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT)) /* first field up to mode need to match r6 struct so that we can reuse * same function for linear & linear aligned */ struct radeon_surface_level { uint64_t offset; uint64_t slice_size; uint32_t npix_x; uint32_t npix_y; uint32_t npix_z; uint32_t nblk_x; uint32_t nblk_y; uint32_t nblk_z; uint32_t pitch_bytes; uint32_t mode; }; struct radeon_surface { uint32_t npix_x; uint32_t npix_y; uint32_t npix_z; uint32_t blk_w; uint32_t blk_h; uint32_t blk_d; uint32_t array_size; uint32_t last_level; uint32_t bpe; uint32_t nsamples; uint32_t flags; /* Following is updated/fill by the allocator. It's allowed to * set some of the value but they are use as hint and can be * overridden (things lile bankw/bankh on evergreen for * instance). */ uint64_t bo_size; uint64_t bo_alignment; /* apply to eg */ uint32_t bankw; uint32_t bankh; uint32_t mtilea; uint32_t tile_split; uint32_t stencil_tile_split; uint64_t stencil_offset; struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL]; }; struct radeon_surface_manager *radeon_surface_manager_new(int fd); void radeon_surface_manager_free(struct radeon_surface_manager *surf_man); int radeon_surface_init(struct radeon_surface_manager *surf_man, struct radeon_surface *surf); int radeon_surface_best(struct radeon_surface_manager *surf_man, struct radeon_surface *surf); #endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-11 02:32:59 +0000