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| author | Alan Hourihane <alanh@tungstengraphics.com> | 2008-05-28 21:01:18 +0100 |
|---|---|---|
| committer | Alan Hourihane <alanh@tungstengraphics.com> | 2008-05-28 21:01:18 +0100 |
| commit | 3a3f39d144c47ce937d6924d344a9ad3d82a2db5 (patch) | |
| tree | 109faf867b2e5774d54fe9499dbfebd3f26f014f /linux-core/ati_pcigart.c | |
| parent | 070755af3fecefb6b09e8ef98738e4926e4148a7 (diff) | |
| parent | 5b86823fa36513f521412a38c240cb18f02dcc9a (diff) | |
Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into modesetting-101
Conflicts:
shared-core/i915_dma.c
shared-core/i915_drv.h
Diffstat (limited to 'linux-core/ati_pcigart.c')
| -rw-r--r-- | linux-core/ati_pcigart.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/linux-core/ati_pcigart.c b/linux-core/ati_pcigart.c index beaa4424..09251ac3 100644 --- a/linux-core/ati_pcigart.c +++ b/linux-core/ati_pcigart.c @@ -34,6 +34,11 @@ #include "drmP.h" # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ +# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) + +#define ATI_PCIE_WRITE 0x4 +#define ATI_PCIE_READ 0x8 + static int drm_ati_alloc_pcigart_table(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) { @@ -103,6 +108,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga dma_addr_t bus_address = 0; int i, j, ret = 0; int max_pages; + dma_addr_t entry_addr; if (!entry) { DRM_ERROR("no scatter/gather memory!\n"); @@ -148,23 +154,27 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga bus_address = 0; goto done; } - page_base = (u32) entry->busaddr[i]; + entry_addr = entry->busaddr[i]; for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { + page_base = (u32) entry_addr & ATI_PCIGART_PAGE_MASK; switch(gart_info->gart_reg_if) { case DRM_ATI_GART_IGP: - *pci_gart = cpu_to_le32((page_base) | 0xc); + page_base |= (upper_32_bits(entry_addr) & 0xff) << 4; + page_base |= 0xc; break; case DRM_ATI_GART_PCIE: - *pci_gart = cpu_to_le32((page_base >> 8) | 0xc); + page_base >>= 8; + page_base |= (upper_32_bits(entry_addr) & 0xff) << 24; + page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE; break; default: case DRM_ATI_GART_PCI: - *pci_gart = cpu_to_le32(page_base); break; } + *pci_gart = cpu_to_le32(page_base); pci_gart++; - page_base += ATI_PCIGART_PAGE_SIZE; + entry_addr += ATI_PCIGART_PAGE_SIZE; } } |