diff options
| author | Eric Anholt <eric@anholt.net> | 2012-01-03 14:32:18 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2012-01-04 14:49:44 -0800 |
| commit | 683855f65523c978562ead56f9d68f50ffdca1a2 (patch) | |
| tree | 078e74f9858d18f63d55d23ce3592a15ddfc540d /intel/tests | |
| parent | ccbc40340b7b472939a90ae8afc0a82b358ce189 (diff) | |
intel: Add regression tests for batch decode.
The .batch was generated using the dump-a-batch branch of
git://people.freedesktop.org/~anholt/mesa
using glxgears on gen7 hardware, using INTEL_DEVID_OVERRIDE for
non-gen7 (this means that offsets in the buffers for non-gen7 are 0!).
The .ref was generated by:
./test_decode tests/gen7-3d.batch -dump.
The .sh exists because you can't supply arguments to tests using the
simple automake tests driver. Something reasonable could be done
using automake's parallel-tests driver (in fact, a previous version of
the patch did that), but I was concerned that:
1) The parallel-tests driver is documented to be unstable -- they may
change interfaces on us later.
2) The parallel-tests driver hides the output of tests in .log files
scattered all over the tree, which was ugly and more painful to
work with.
v2: Actually add the batch files, add a .gitignore for the *-new.txt
files added after failures, and fix failure mode for undetected
chipset name.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1)
Diffstat (limited to 'intel/tests')
| -rw-r--r-- | intel/tests/.gitignore | 1 | ||||
| -rw-r--r-- | intel/tests/gen4-3d.batch | bin | 0 -> 1952 bytes | |||
| -rw-r--r-- | intel/tests/gen4-3d.batch-ref.txt | 488 | ||||
| l--------- | intel/tests/gen4-3d.batch.sh | 1 | ||||
| -rw-r--r-- | intel/tests/gen5-3d.batch | bin | 0 -> 2048 bytes | |||
| -rw-r--r-- | intel/tests/gen5-3d.batch-ref.txt | 512 | ||||
| l--------- | intel/tests/gen5-3d.batch.sh | 1 | ||||
| -rw-r--r-- | intel/tests/gen6-3d.batch | bin | 0 -> 3960 bytes | |||
| -rw-r--r-- | intel/tests/gen6-3d.batch-ref.txt | 990 | ||||
| l--------- | intel/tests/gen6-3d.batch.sh | 1 | ||||
| -rw-r--r-- | intel/tests/gen7-3d.batch | bin | 0 -> 4504 bytes | |||
| -rw-r--r-- | intel/tests/gen7-3d.batch-ref.txt | 1350 | ||||
| l--------- | intel/tests/gen7-3d.batch.sh | 1 | ||||
| -rw-r--r-- | intel/tests/gm45-3d.batch | bin | 0 -> 1952 bytes | |||
| -rw-r--r-- | intel/tests/gm45-3d.batch-ref.txt | 488 | ||||
| l--------- | intel/tests/gm45-3d.batch.sh | 1 | ||||
| -rwxr-xr-x | intel/tests/test-batch.sh | 20 |
17 files changed, 3854 insertions, 0 deletions
diff --git a/intel/tests/.gitignore b/intel/tests/.gitignore new file mode 100644 index 00000000..e9d01ecb --- /dev/null +++ b/intel/tests/.gitignore @@ -0,0 +1 @@ +*-new.txt diff --git a/intel/tests/gen4-3d.batch b/intel/tests/gen4-3d.batch Binary files differnew file mode 100644 index 00000000..e6911a43 --- /dev/null +++ b/intel/tests/gen4-3d.batch diff --git a/intel/tests/gen4-3d.batch-ref.txt b/intel/tests/gen4-3d.batch-ref.txt new file mode 100644 index 00000000..20aa1d4e --- /dev/null +++ b/intel/tests/gen4-3d.batch-ref.txt @@ -0,0 +1,488 @@ +0x12300000: 0x61040000: 3DSTATE_PIPELINE_SELECT +0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP +0x12300008: 0x00000000: dword 1 +0x1230000c: 0x61020000: STATE_SIP +0x12300010: 0x00000000: dword 1 +0x12300014: 0x780b0000: 3DSTATE_VF_STATISTICS +0x12300018: 0x61010004: STATE_BASE_ADDRESS +0x1230001c: 0x00000001: general state base address 0x00000000 +0x12300020: 0x00000001: surface state base address 0x00000000 +0x12300024: 0x00000001: indirect state base address 0x00000000 +0x12300028: 0x00000001: general state upper bound disabled +0x1230002c: 0x00000001: indirect state upper bound disabled +0x12300030: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x12300034: 0x00007e20: VS binding table +0x12300038: 0x00000000: GS binding table +0x1230003c: 0x00000000: Clip binding table +0x12300040: 0x00000000: SF binding table +0x12300044: 0x00007e20: WM binding table +0x12300048: 0x79010003: 3DSTATE_CONSTANT_COLOR +0x1230004c: 0x00000000: dword 1 +0x12300050: 0x00000000: dword 2 +0x12300054: 0x00000000: dword 3 +0x12300058: 0x00000000: dword 4 +0x1230005c: 0x79050003: 3DSTATE_DEPTH_BUFFER +0x12300060: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled +0x12300064: 0x00000000: depth offset +0x12300068: 0x09584ac0: 300x300 +0x1230006c: 0x00000000: volume depth +0x12300070: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300074: 0x00007d60: VS state +0x12300078: 0x00000000: GS state +0x1230007c: 0x00007d21: Clip state +0x12300080: 0x00007d80: SF state +0x12300084: 0x00007de0: WM state +0x12300088: 0x00007fc0: CC state +0x1230008c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300090: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300094: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300098: 0x60010000: CS_URB_STATE +0x1230009c: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 +0x123000a0: 0x79000002: 3DSTATE_DRAWING_RECTANGLE +0x123000a4: 0x00000000: top left: 0,0 +0x123000a8: 0x012b012b: bottom right: 299,299 +0x123000ac: 0x00000000: origin: 0,0 +0x123000b0: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123000b4: 0x0000000c: buffer 0: sequential, pitch 12b +0x123000b8: 0x00000000: buffer address +0x123000bc: 0x00000000: max index +0x123000c0: 0x00000000: mbz +0x123000c4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123000c8: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123000cc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123000d0: 0x60020100: CONSTANT_BUFFER: valid +0x123000d4: 0x00000001: offset: 0x00000000, length: 128 bytes +0x123000d8: 0x7b001804: 3DPRIMITIVE: tri fan sequential +0x123000dc: 0x00000004: vertex count +0x123000e0: 0x00000000: start vertex +0x123000e4: 0x00000001: instance count +0x123000e8: 0x00000000: start instance +0x123000ec: 0x00000000: index bias +0x123000f0: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x123000f4: 0x00007b40: VS binding table +0x123000f8: 0x00000000: GS binding table +0x123000fc: 0x00000000: Clip binding table +0x12300100: 0x00000000: SF binding table +0x12300104: 0x00007b40: WM binding table +0x12300108: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x1230010c: 0x00007aa0: VS state +0x12300110: 0x00007a41: GS state +0x12300114: 0x00007a61: Clip state +0x12300118: 0x00007ac0: SF state +0x1230011c: 0x00007b00: WM state +0x12300120: 0x00007cc0: CC state +0x12300124: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300128: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x1230012c: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300130: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300134: 0x0000000c: buffer 0: sequential, pitch 12b +0x12300138: 0x00000000: buffer address +0x1230013c: 0x00000000: max index +0x12300140: 0x00000000: mbz +0x12300144: 0x60020100: CONSTANT_BUFFER: valid +0x12300148: 0x00000082: offset: 0x00000080, length: 192 bytes +0x1230014c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300150: 0x00000052: vertex count +0x12300154: 0x00000000: start vertex +0x12300158: 0x00000001: instance count +0x1230015c: 0x00000000: start instance +0x12300160: 0x00000000: index bias +0x12300164: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300168: 0x00007aa0: VS state +0x1230016c: 0x00007a21: GS state +0x12300170: 0x00007a61: Clip state +0x12300174: 0x00007ac0: SF state +0x12300178: 0x00007b00: WM state +0x1230017c: 0x00007cc0: CC state +0x12300180: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300184: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300188: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230018c: 0x60020100: CONSTANT_BUFFER: valid +0x12300190: 0x00000082: offset: 0x00000080, length: 192 bytes +0x12300194: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300198: 0x00000050: vertex count +0x1230019c: 0x00000052: start vertex +0x123001a0: 0x00000001: instance count +0x123001a4: 0x00000000: start instance +0x123001a8: 0x00000000: index bias +0x123001ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001b0: 0x00007aa0: VS state +0x123001b4: 0x00007a01: GS state +0x123001b8: 0x00007a61: Clip state +0x123001bc: 0x00007ac0: SF state +0x123001c0: 0x00007b00: WM state +0x123001c4: 0x00007cc0: CC state +0x123001c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123001cc: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123001d0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123001d4: 0x60020100: CONSTANT_BUFFER: valid +0x123001d8: 0x00000142: offset: 0x00000140, length: 192 bytes +0x123001dc: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123001e0: 0x00000052: vertex count +0x123001e4: 0x000000a2: start vertex +0x123001e8: 0x00000001: instance count +0x123001ec: 0x00000000: start instance +0x123001f0: 0x00000000: index bias +0x123001f4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001f8: 0x00007aa0: VS state +0x123001fc: 0x000079e1: GS state +0x12300200: 0x00007a61: Clip state +0x12300204: 0x00007ac0: SF state +0x12300208: 0x00007b00: WM state +0x1230020c: 0x00007cc0: CC state +0x12300210: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300214: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300218: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230021c: 0x60020100: CONSTANT_BUFFER: valid +0x12300220: 0x00000142: offset: 0x00000140, length: 1
static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
static unsigned time_diff(struct timeval *now,struct timeval *then)
{
return (now->tv_usec >= then->tv_usec) ?
now->tv_usec - then->tv_usec :
1000000 - (then->tv_usec - now->tv_usec);
}
u32 via_get_vblank_counter(struct drm_device *dev, int crtc)
{
drm_via_private_t *dev_priv = dev->dev_private;
if (crtc != 0)
return 0;
return atomic_read(&dev_priv->vbl_received);
}
irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
{
struct drm_device *dev = (struct drm_device *) arg;
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
u32 status;
int handled = 0;
struct timeval cur_vblank;
drm_via_irq_t *cur_irq = dev_priv->via_irqs;
int i;
status = VIA_READ(VIA_REG_INTERRUPT);
if (status & VIA_IRQ_VBLANK_PENDING) {
atomic_inc(&dev_priv->vbl_received);
if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
#ifdef __linux__
do_gettimeofday(&cur_vblank);
#else
microtime(&cur_vblank);
#endif
if (dev_priv->last_vblank_valid) {
dev_priv->usec_per_vblank =
time_diff(&cur_vblank,
&dev_priv->last_vblank) >> 4;
}
dev_priv->last_vblank = cur_vblank;
dev_priv->last_vblank_valid = 1;
}
if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
DRM_DEBUG("US per vblank is: %u\nreturn IRQ_NONE;
}
static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
{
u32 status;
if (dev_priv) {
/* Acknowlege interrupts */
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status |
dev_priv->irq_pending_mask);
}
}
int via_enable_vblank(struct drm_device *dev, int crtc)
{
drm_via_private_t *dev_priv = dev->dev_private;
u32 status;
if (crtc != 0) {
DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);
return -EINVAL;
}
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status & VIA_IRQ_VBLANK_ENABLE);
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
return 0;
}
void via_disable_vblank(struct drm_device *dev, int crtc)
{
drm_via_private_t *dev_priv = dev->dev_private;
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
if (crtc != 0)
DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);
}
static int
via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence,
unsigned int *sequence)
{
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
unsigned int cur_irq_sequence;
drm_via_irq_t *cur_irq;
int ret = 0;
maskarray_t *masks;
int real_irq;
DRM_DEBUG("\n");
if (!dev_priv) {
DRM_ERROR("called with no initialization\n");
return -EINVAL;
}
if (irq >= drm_via_irq_num) {
DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
return -EINVAL;
}
real_irq = dev_priv->irq_map[irq];
if (real_irq < 0) {
DRM_ERROR("Video IRQ %d not available on this hardware.\n",
irq);
return -EINVAL;
}
masks = dev_priv->irq_masks;
cur_irq = dev_priv->via_irqs + real_irq;
if (masks[real_irq][2] && !force_sequence) {
DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
masks[irq][4]));
cur_irq_sequence = atomic_read(&cur_irq->irq_received);
} else {
DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
(((cur_irq_sequence =
atomic_read(&cur_irq->irq_received)) -
*sequence) <= (1 << 23)));
}
*sequence = cur_irq_sequence;
return ret;
}
/*
* drm_dma.h hooks
*/
void via_driver_irq_preinstall(struct drm_device * dev)
{
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
u32 status;
drm_via_irq_t *cur_irq;
int i;
DRM_DEBUG("dev_priv: %p\n", dev_priv);
if (dev_priv) {
cur_irq = dev_priv->via_irqs;
dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
if (dev_priv->chipset == VIA_PRO_GROUP_A ||
dev_priv->chipset == VIA_DX9_0) {
dev_priv->irq_masks = via_pro_group_a_irqs;
dev_priv->num_irqs = via_num_pro_group_a;
dev_priv->irq_map = via_irqmap_pro_group_a;
} else {
dev_priv->irq_masks = via_unichrome_irqs;
dev_priv->num_irqs = via_num_unichrome;
dev_priv->irq_map = via_irqmap_unichrome;
}
for (i = 0; i < dev_priv->num_irqs; ++i) {
atomic_set(&cur_irq->irq_received, 0);
cur_irq->enable_mask = dev_priv->irq_masks[i][0];
cur_irq->pending_mask = dev_priv->irq_masks[i][1];
DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);
dev_priv->irq_enable_mask |= cur_irq->enable_mask;
dev_priv->irq_pending_mask |= cur_irq->pending_mask;
cur_irq++;
DRM_DEBUG("Initializing IRQ %d\n", i);
}
dev_priv->last_vblank_valid = 0;
/* Clear VSync interrupt regs */
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status &
~(dev_priv->irq_enable_mask));
/* Clear bits if they're already high */
viadrv_acknowledge_irqs(dev_priv);
}
}
int via_driver_irq_postinstall(struct drm_device * dev)
{
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
u32 status;
DRM_DEBUG("via_driver_irq_postinstall\n");
if (!dev_priv)
return -EINVAL;
drm_vblank_init(dev, 1);
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
| dev_priv->irq_enable_mask);
/* Some magic, oh for some data sheets ! */
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
return 0;
}
void via_driver_irq_uninstall(struct drm_device * dev)
{
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
u32 status;
DRM_DEBUG("\n");
if (dev_priv) {
/* Some more magic, oh for some data sheets ! */
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
status = VIA_READ(VIA_REG_INTERRUPT);
VIA_WRITE(VIA_REG_INTERRUPT, status &
~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
}
}
int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_via_irqwait_t *irqwait = data;
struct timeval now;
int ret = 0;
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
drm_via_irq_t *cur_irq = dev_priv->via_irqs;
int force_sequence;
if (!dev->irq)
return -EINVAL;
if (irqwait->request.irq >= dev_priv->num_irqs) {
DRM_ERROR("Trying to wait on unknown irq %d\n",
irqwait->request.irq);
return -EINVAL;
}
cur_irq += irqwait->request.irq;
switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
case VIA_IRQ_RELATIVE:
irqwait->request.sequence +=
atomic_read(&cur_irq->irq_received);
irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
case VIA_IRQ_ABSOLUTE:
break;
default:
return -EINVAL;
}
if (irqwait->request.type & VIA_IRQ_SIGNAL) {
DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
return -EINVAL;
}
force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
&irqwait->request.sequence);
#ifdef __linux__
do_gettimeofday(&now);
#else
microtime(&now);
#endif
irqwait->reply.tval_sec = now.tv_sec;
irqwait->reply.tval_usec = now.tv_usec;
return ret;
}
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