From ed5fcb75d027a1e84223fd0fe9363d70f45bf230 Mon Sep 17 00:00:00 2001
From: mstsirkin <mstsirkin@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652>
Date: Wed, 12 Feb 2014 11:22:00 +0000
Subject: PCI: minor wording change

Since access width requirement is a confirmance clause, make it
explicit that it applies to 4,2 and 1 byte fields.
Also explain what happens to fields of other widths (such as
the 6 byte MAC).

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

git-svn-id: https://tools.oasis-open.org/version-control/svn/virtio@248 0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652
---
 content.tex | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'content.tex')

diff --git a/content.tex b/content.tex
index aa191a3..0aed373 100644
--- a/content.tex
+++ b/content.tex
@@ -844,8 +844,12 @@ These regions contain the virtio header registers, the notification register, th
 ISR status register and device specific registers, as specified by Virtio
 Structure PCI Capabilities.
 
-There may be different widths of accesses to the I/O region; the driver
-MUST access each field using the “natural” access method (i.e. 32-bit accesses for 32-bit fields, etc).  All multi-byte fields are little-endian.
+Fields of different sizes are present in the device
+configuration regions; the driver
+MUST access each field using the “natural” access method, i.e.
+32-bit accesses for 32-bit fields, 16-bit accesses for 16-bit
+fields and 8-bit accesses for 8-bit fields.
+All 32-bit and 16-bit fields are little-endian.
 
 \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities}
 
-- 
cgit v1.2.3

