From b60e6fee3a1f457930e3978ded317608d71de052 Mon Sep 17 00:00:00 2001
From: rusty <rusty@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652>
Date: Mon, 10 Feb 2014 10:33:05 +0000
Subject: patch feedback-8-6.patch

git-svn-id: https://tools.oasis-open.org/version-control/svn/virtio@222 0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652
---
 content.tex | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'content.tex')

diff --git a/content.tex b/content.tex
index 1a86bf9..69f11a6 100644
--- a/content.tex
+++ b/content.tex
@@ -1094,7 +1094,13 @@ Queue Notify address.
 \subsubsection{ISR status capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / ISR status capability}
 
 The device MUST present at least one VIRTIO_PCI_CAP_ISR_CFG capability.  This
-refers to at least a single byte, which contains the 8-bit ISR status field.
+refers to at least a single byte, which contains the 8-bit ISR status field:
+\begin{lstlisting}
+#define VIRTIO_PCI_ISR_VQ       0x1
+#define VIRTIO_PCI_ISR_CONFIG   0x2
+\end{lstlisting}
+
+See sections \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Virtqueue Interrupts From The Device} and \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes} for how this is used.
 
 \subsubsection{Device specific structure}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Device specific structure}
 
-- 
cgit v1.2.3

