From 3df7d74aa4b6cb35aba210d1c4ed5bbbdf179aaf Mon Sep 17 00:00:00 2001
From: rusty <rusty@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652>
Date: Wed, 12 Feb 2014 03:17:30 +0000
Subject: PCI: explicitly document ISR status field

Feedback on ISR status register:
	It would be helpful if this section provided the meaning of each
	bit in the register.

ISR use is scattered all around the place.
Add a section describing the format and semantics.

[ Merged to combine with new ISR-specific section --RR ]

As per minutes:
        https://lists.oasis-open.org/archives/virtio/201402/msg00121.html

Cc: Arun Subbarao <asubbarao@lnxw.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Rusty Russell <rusty@au1.ibm.com>

git-svn-id: https://tools.oasis-open.org/version-control/svn/virtio@241 0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652
---
 content.tex | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

(limited to 'content.tex')

diff --git a/content.tex b/content.tex
index d43decd..5abc79e 100644
--- a/content.tex
+++ b/content.tex
@@ -1121,15 +1121,32 @@ cap.length >= queue_notify_off * notify_off_multiplier + 2
 \subsubsection{ISR status capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / ISR status capability}
 
 The device MUST present at least one VIRTIO_PCI_CAP_ISR_CFG capability.  This
-refers to at least a single byte, which contains the 8-bit ISR status field:
-\begin{lstlisting}
-#define VIRTIO_PCI_ISR_VQ       0x1
-#define VIRTIO_PCI_ISR_CONFIG   0x2
-\end{lstlisting}
+refers to at least a single byte, which contains the 8-bit ISR status field.
+
+The \field{offset} for the ISR status field has no specific alignment requirements.
+
+The ISR status field is used for INT\#x interrupt handling.
+The driver MUST NOT access the ISR field when MSI-X capability
+is enabled.
+
+\begin{tabular}{ |l||l|l|l| }
+\hline
+Bits       & 0                               & 1               &  2 to 31 \\
+\hline
+Purpose    & Device Configuration Interrupt  & Queue Interrupt & Reserved \\
+\hline
+\end{tabular}
+
+If MSI-X capability is disabled, device MUST set Interrupt Status
+bit in the PCI Status register in the PCI Configuration Header of
+the device to the logical OR of all bits in ISR status field of
+the device.  Device then asserts/deasserts INT\#x interrupts unless masked
+according to standard PCI rules \hyperref[intro:PCI]{[PCI]}.
 
-See sections \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Virtqueue Interrupts From The Device} and \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes} for how this is used.
+Device MUST reset the ISR status field to 0 on read.
 
-The \field{offset} for the ISR status has no specific alignment requirements.
+In this way, driver read of ISR status causes the device to de-assert
+an interrupt.
 
 \subsubsection{Device specific structure}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Device specific structure}
 
-- 
cgit v1.2.3

