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2014-02-26Feedback: console & entropy: separate normative and descriptive texts.rusty
2014-02-26Feedback: block: separate normative and descriptive text.rusty
2014-02-26Feedback: net: separate normative and instructional text.rusty
2014-02-26Feedback: CCW: Separate normative and descriptive sections.rusty
2014-02-26Feedback: MMIO: Separate normative and descriptive text.rusty
2014-02-26Feedback: PCI: Separate explanatory and normative text.rusty
2014-02-26Feedback: Separate the rest of chapter 2 into normative vs explanatory.rusty
2014-02-26Feedback: Normative split for Basic Facilities of a Virtio Device / Virtqueue...rusty
2014-02-26Feedback: Normative split in Basic Facilities of a Virtio Device / Virtqueuesrusty
2014-02-26Feedback: split Basic Facilities feature bits and config space into normative.rusty
2014-02-26Feedback: add normative marker.rusty
2014-02-26Feedback: 2.1 Device Status field: Separate description from normative.rusty
2014-02-26Feedback: move legacy/transitional definitions into terminology.rusty
2014-02-26Feedback: hoist the one legacy-related requirement out of legacy section.rusty
2014-02-26Feedback: add old draft to normative references (VIRTIO-77)rusty
2014-02-26Feedback: use proper list in introduction (VIRTIO-82)rusty
2014-02-26Feedback: move new device design section to Appendix.rusty
2014-02-26Feedback: Bug TAB-553 (VIRTIO-76)rusty
2014-02-26Feedback: TAB-555 Bad sub-sectioning (VIRTIO-80)rusty
2014-02-26Feedback: TAB-557 Spelling errors, etc (VIRTIO-75)rusty
2014-02-26PCI: better document driver and device requirementsrusty
2014-02-26feedback: minor wording cleanupsrusty
2014-02-26SCSI: fix up more fields.rusty
2014-02-20SCSI: missing space.rusty
2014-02-19Gratuitous Packet Sending: clarify wording.rusty
2014-02-19net: fix incorrect reference.rusty
2014-02-13ccw: padding annotationscornelia.huck
2014-02-12PCI: minor wording changemstsirkin
2014-02-12content: more strict confirmance languagemstsirkin
2014-02-12introduction: address lnovich commentsmstsirkin
2014-02-12abstract: address lnovich commentmstsirkin
2014-02-12VIRTIO-55: Add a reserved ID for GPU devicesrusty
2014-02-12Fix S390 normative references.rusty
2014-02-12ccw: Further use of RFC2119 language.rusty
2014-02-12PCI: explicitly document ISR status fieldrusty
2014-02-12PCI: consistent device/PCI configuration spacerusty
2014-02-12Feedback #8: Applied.rusty
2014-02-12Feedback #7: Appliedrusty
2014-02-12Feedback #6: Appliedrusty
2014-02-12Feedback #5: Applied.rusty
2014-02-12Feedback #4: applied.rusty
2014-02-12PCI: minor changes for previous patch.rusty
2014-02-12PCI: rearrange it allrusty
2014-02-12PCI: rearrange it allrusty
2014-02-12C struct specifications.rusty
2014-02-11feedback: add more replacements of read-only.rusty
2014-02-11Feedback: minor clarity update from Thomas.rusty
2014-02-11Feedback: fix formatting typo.rusty
2014-02-10Merge together all feedback from Arun.rusty
2014-02-10Feedback: update so it applies sequentially.rusty
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-20 19:36:05 +0000
an> #define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ #define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ #define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ #define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ #define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ #define I810_CTX_SETUP_SIZE 20 /* Texture state (per tex unit) */ #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ #define I810_TEXREG_MI1 1 #define I810_TEXREG_MI2 2 #define I810_TEXREG_MI3 3 #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ #define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ #define I810_TEX_SETUP_SIZE 8 /* Flags for clear ioctl */ #define I810_FRONT 0x1 #define I810_BACK 0x2 #define I810_DEPTH 0x4 typedef struct _drm_i810_init { enum { I810_INIT_DMA = 0x01, I810_CLEANUP_DMA = 0x02 } func; #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) int ring_map_idx; int buffer_map_idx; #else unsigned int mmio_offset; unsigned int buffers_offset; #endif int sarea_priv_offset; unsigned int ring_start; unsigned int ring_end; unsigned int ring_size; unsigned int front_offset; unsigned int back_offset; unsigned int depth_offset; unsigned int overlay_offset; unsigned int overlay_physical; unsigned int w; unsigned int h; unsigned int pitch; unsigned int pitch_bits; } drm_i810_init_t; /* Warning: If you change the SAREA structure you must change the Xserver * structure as well */ typedef struct _drm_i810_tex_region { unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i810_tex_region_t; typedef struct _drm_i810_sarea { unsigned int ContextState[I810_CTX_SETUP_SIZE]; unsigned int BufferState[I810_DEST_SETUP_SIZE]; unsigned int TexState[2][I810_TEX_SETUP_SIZE]; unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; /* Maintain an LRU of contiguous regions of texture space. If * you think you own a region of texture memory, and it has an * age different to the one you set, then you are mistaken and * it has been stolen by another client. If global texAge * hasn't changed, there is no need to walk the list. * * These regions can be used as a proxy for the fine-grained * texture information of other clients - by maintaining them * in the same lru which is used to age their own textures, * clients have an approximate lru for the whole of global * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject * them all in LRU order. */ drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; /* Last elt is sentinal */ int texAge; /* last time texture was uploaded */ int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; int pf_enabled; /* is pageflipping allowed? */ int pf_active; int pf_current_page; /* which buffer is being displayed? */ } drm_i810_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmMga.h) */ /* i810 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) #define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) #define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) #define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) #define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) #define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) #define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) #define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) #define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) #define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) #define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) #define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) #define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) #define DRM_IOCTL_I810_FLIP DRM_IO ( 0x4e ) typedef struct _drm_i810_clear { int clear_color; int clear_depth; int flags; } drm_i810_clear_t; /* These may be placeholders if we have more cliprects than * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a * new set of cliprects. */ typedef struct _drm_i810_vertex { int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i810_vertex_t; typedef struct _drm_i810_copy_t { int idx; /* buffer index */ int used; /* nr bytes in use */ void *address; /* Address to copy from */ } drm_i810_copy_t; #define PR_TRIANGLES (0x0<<18) #define PR_TRISTRIP_0 (0x1<<18) #define PR_TRISTRIP_1 (0x2<<18) #define PR_TRIFAN (0x3<<18) #define PR_POLYGON (0x4<<18) #define PR_LINES (0x5<<18) #define PR_LINESTRIP (0x6<<18) #define PR_RECTS (0x7<<18) #define PR_MASK (0x7<<18) typedef struct drm_i810_dma { void *virtual; int request_idx; int request_size; int granted; } drm_i810_dma_t; typedef struct _drm_i810_overlay_t { unsigned int offset; /* Address of the Overlay Regs */ unsigned int physical; } drm_i810_overlay_t; typedef struct _drm_i810_mc { int idx; /* buffer index */ int used; /* nr bytes in use */ int num_blocks; /* number of GFXBlocks */ int *length; /* List of lengths for GFXBlocks (FUTURE)*/ unsigned int last_render; /* Last Render Request */ } drm_i810_mc_t; #endif /* _I810_DRM_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-20 19:36:05 +0000