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-rwxr-xr-xpy/tests/rottest.py182
1 files changed, 182 insertions, 0 deletions
diff --git a/py/tests/rottest.py b/py/tests/rottest.py
new file mode 100755
index 0000000..4dae95e
--- /dev/null
+++ b/py/tests/rottest.py
@@ -0,0 +1,182 @@
+#!/usr/bin/python3
+
+import pykms
+from enum import Enum
+
+import termios, sys, os, tty
+
+card = pykms.OmapCard()
+
+res = pykms.ResourceManager(card)
+conn = res.reserve_connector()
+crtc = res.reserve_crtc(conn)
+mode = conn.get_default_mode()
+modeb = mode.to_blob(card)
+rootplane = res.reserve_primary_plane(crtc, pykms.PixelFormat.XRGB8888)
+plane = res.reserve_overlay_plane(crtc, pykms.PixelFormat.NV12)
+
+card.disable_planes()
+
+req = pykms.AtomicReq(card)
+
+req.add(conn, "CRTC_ID", crtc.id)
+
+req.add(crtc, {"ACTIVE": 1,
+ "MODE_ID": modeb.id})
+
+# This enables the root plane
+
+#rootfb = pykms.OmapFramebuffer(card, mode.hdisplay, mode.vdisplay, "XR24");
+#pykms.draw_test_pattern(rootfb);
+#
+#req.add(rootplane, {"FB_ID": rootfb.id,
+# "CRTC_ID": crtc.id,
+# "SRC_X": 0 << 16,
+# "SRC_Y": 0 << 16,
+# "SRC_W": mode.hdisplay << 16,
+# "SRC_H": mode.vdisplay << 16,
+# "CRTC_X": 0,
+# "CRTC_Y": 0,
+# "CRTC_W": mode.hdisplay,
+# "CRTC_H": mode.vdisplay,
+# "zorder": 0})
+
+req.commit_sync(allow_modeset = True)
+
+class Rotation(int, Enum):
+ ROTATE_0 = 1 << 0
+ ROTATE_90 = 1 << 1
+ ROTATE_180 = 1 << 2
+ ROTATE_270 = 1 << 3
+ ROTATE_MASK = ROTATE_0 | ROTATE_90 | ROTATE_180 | ROTATE_270
+ REFLECT_X = 1 << 4
+ REFLECT_Y = 1 << 5
+ REFLECT_MASK = REFLECT_X | REFLECT_Y
+
+
+def show_rot_plane(crtc, plane, fb, rot, x_scale, y_scale):
+
+ crtc_w = int(fb_w * x_scale)
+ crtc_h = int(fb_h * y_scale)
+
+ if (rot & Rotation.ROTATE_90) or (rot & Rotation.ROTATE_270):
+ tmp = crtc_w
+ crtc_w = crtc_h
+ crtc_h = tmp
+
+ crtc_x = int(mode.hdisplay / 2 - crtc_w / 2)
+ crtc_y = int(mode.vdisplay / 2 - crtc_h / 2)
+
+ req = pykms.AtomicReq(card)
+
+ src_x = 0
+ src_y = 0
+ src_w = fb_w - src_x
+ src_h = fb_h - src_y
+
+ print("SRC {},{}-{}x{} DST {},{}-{}x{}".format(
+ src_x, src_y, src_w, src_h,
+ crtc_x, crtc_y, crtc_w, crtc_h))
+
+ angle_str = Rotation(rot & Rotation.ROTATE_MASK).name
+ reflect_x_str = "REFLECT_X" if rot & Rotation.REFLECT_X else ""
+ reflect_y_str = "REFLECT_Y" if rot & Rotation.REFLECT_Y else ""
+
+ print("{} {} {}".format(angle_str, reflect_x_str, reflect_y_str))
+
+ sys.stdout.flush()
+
+ req.add(plane, {"FB_ID": fb.id,
+ "CRTC_ID": crtc.id,
+ "SRC_X": src_x << 16,
+ "SRC_Y": src_y << 16,
+ "SRC_W": src_w << 16,
+ "SRC_H": src_h << 16,
+ "CRTC_X": crtc_x,
+ "CRTC_Y": crtc_y,
+ "CRTC_W": crtc_w,
+ "CRTC_H": crtc_h,
+ "rotation": rot,
+ "zorder": 2})
+
+ req.commit_sync(allow_modeset = True)
+
+
+fb_w = 480
+fb_h = 150
+x_scale = 1
+y_scale = 1
+
+fb = pykms.OmapFramebuffer(card, fb_w, fb_h, "NV12", tiled = True);
+#fb = pykms.DumbFramebuffer(card, fb_w, fb_h, "NV12")
+pykms.draw_test_pattern(fb);
+
+def even(i):
+ return i & ~1
+
+pykms.draw_text(fb, even((fb_w // 2) - (8 * 3) // 2), 4, "TOP", pykms.white)
+pykms.draw_text(fb, even((fb_w // 2) - (8 * 6) // 2), fb_h - 8 - 4, "BOTTOM", pykms.white)
+pykms.draw_text(fb, 4, even(((fb_h // 2) - 4)), "L", pykms.white)
+pykms.draw_text(fb, fb_w - 8 - 4, even(((fb_h // 2) - 4)), "R", pykms.white)
+
+rots = [ Rotation.ROTATE_0, Rotation.ROTATE_90, Rotation.ROTATE_180, Rotation.ROTATE_270 ]
+cursors = [ "A", "D", "B", "C" ]
+
+print("Use the cursor keys, x and y to change rotation. Press q to quit.")
+
+fd = sys.stdin.fileno()
+oldterm = termios.tcgetattr(fd)
+tty.setcbreak(fd)
+
+try:
+ esc_seq = 0
+
+ current_rot = Rotation.ROTATE_0
+
+ show_rot_plane(crtc, plane, fb, current_rot, x_scale, y_scale)
+
+ while True:
+ c = sys.stdin.read(1)
+ #print("Got character {}".format(repr(c)))
+
+ changed = False
+ handled = False
+
+ if esc_seq == 0:
+ if c == "\x1b":
+ esc_seq = 1
+ handled = True
+ elif esc_seq == 1:
+ if c == "[":
+ esc_seq = 2
+ handled = True
+ else:
+ esc_seq = 0
+ elif esc_seq == 2:
+ esc_seq = 0
+
+ if c in cursors:
+ handled = True
+
+ rot = rots[cursors.index(c)]
+
+ current_rot &= ~Rotation.ROTATE_MASK
+ current_rot |= rot
+
+ changed = True
+
+ if not handled:
+ if c == "q":
+ break
+ elif c == "x":
+ current_rot ^= Rotation.REFLECT_X
+ changed = True
+ elif c == "y":
+ current_rot ^= Rotation.REFLECT_Y
+ changed = True
+
+ if changed:
+ show_rot_plane(crtc, plane, fb, current_rot, x_scale, y_scale)
+
+finally:
+ termios.tcsetattr(fd, termios.TCSAFLUSH, oldterm)
> 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751
/*
 * Copyright 2005 Stephane Marchesin
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "drm.h"
#include "drm_sarea.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"
#include "nv50_kms_wrapper.h"
#include "nv50_fbcon.h"

static int nouveau_init_card_mappings(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int ret;

	/* resource 0 is mmio regs */
	/* resource 1 is linear FB */
	/* resource 2 is RAMIN (mmio regs + 0x1000000) */
	/* resource 6 is bios */

	/* map the mmio regs */
	ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
			      drm_get_resource_len(dev, 0),
			      _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
	if (ret) {
		DRM_ERROR("Unable to initialize the mmio mapping (%d). "
			  "Please report your setup to " DRIVER_EMAIL "\n",
			  ret);
		return -EINVAL;
	}
	DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset);

	/* map larger RAMIN aperture on NV40 cards */
	dev_priv->ramin = NULL;
	if (dev_priv->card_type >= NV_40) {
		int ramin_resource = 2;
		if (drm_get_resource_len(dev, ramin_resource) == 0)
			ramin_resource = 3;

		ret = drm_addmap(dev,
				 drm_get_resource_start(dev, ramin_resource),
				 drm_get_resource_len(dev, ramin_resource),
				 _DRM_REGISTERS, _DRM_READ_ONLY,
				 &dev_priv->ramin);
		if (ret) {
			DRM_ERROR("Failed to init RAMIN mapping, "
				  "limited instance memory available\n");
			dev_priv->ramin = NULL;
		}
	}

	/* On older cards (or if the above failed), create a map covering
	 * the BAR0 PRAMIN aperture */
	if (!dev_priv->ramin) {
		ret = drm_addmap(dev,
				 drm_get_resource_start(dev, 0) + NV_RAMIN,
				 (1*1024*1024),
				 _DRM_REGISTERS, _DRM_READ_ONLY,
				 &dev_priv->ramin);
		if (ret) {
			DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret);
			return ret;
		}
	}

	return 0;
}

static int nouveau_stub_init(struct drm_device *dev) { return 0; }
static void nouveau_stub_takedown(struct drm_device *dev) {}

static int nouveau_init_engine_ptrs(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;

	switch (dev_priv->chipset & 0xf0) {
	case 0x00:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv04_mc_init;
		engine->mc.takedown	= nv04_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv04_fb_init;
		engine->fb.takedown	= nv04_fb_takedown;
		engine->graph.init	= nv04_graph_init;
		engine->graph.takedown	= nv04_graph_takedown;
		engine->graph.create_context	= nv04_graph_create_context;
		engine->graph.destroy_context	= nv04_graph_destroy_context;
		engine->graph.load_context	= nv04_graph_load_context;
		engine->graph.save_context	= nv04_graph_save_context;
		engine->fifo.channels	= 16;
		engine->fifo.init	= nouveau_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv04_fifo_channel_id;
		engine->fifo.create_context	= nv04_fifo_create_context;
		engine->fifo.destroy_context	= nv04_fifo_destroy_context;
		engine->fifo.load_context	= nv04_fifo_load_context;
		engine->fifo.save_context	= nv04_fifo_save_context;
		break;
	case 0x10:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv04_mc_init;
		engine->mc.takedown	= nv04_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv10_fb_init;
		engine->fb.takedown	= nv10_fb_takedown;
		engine->graph.init	= nv10_graph_init;
		engine->graph.takedown	= nv10_graph_takedown;
		engine->graph.create_context	= nv10_graph_create_context;
		engine->graph.destroy_context	= nv10_graph_destroy_context;
		engine->graph.load_context	= nv10_graph_load_context;
		engine->graph.save_context	= nv10_graph_save_context;
		engine->fifo.channels	= 32;
		engine->fifo.init	= nouveau_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv10_fifo_channel_id;
		engine->fifo.create_context	= nv10_fifo_create_context;
		engine->fifo.destroy_context	= nv10_fifo_destroy_context;
		engine->fifo.load_context	= nv10_fifo_load_context;
		engine->fifo.save_context	= nv10_fifo_save_context;
		break;
	case 0x20:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv04_mc_init;
		engine->mc.takedown	= nv04_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv10_fb_init;
		engine->fb.takedown	= nv10_fb_takedown;
		engine->graph.init	= nv20_graph_init;
		engine->graph.takedown	= nv20_graph_takedown;
		engine->graph.create_context	= nv20_graph_create_context;
		engine->graph.destroy_context	= nv20_graph_destroy_context;
		engine->graph.load_context	= nv20_graph_load_context;
		engine->graph.save_context	= nv20_graph_save_context;
		engine->fifo.channels	= 32;
		engine->fifo.init	= nouveau_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv10_fifo_channel_id;
		engine->fifo.create_context	= nv10_fifo_create_context;
		engine->fifo.destroy_context	= nv10_fifo_destroy_context;
		engine->fifo.load_context	= nv10_fifo_load_context;
		engine->fifo.save_context	= nv10_fifo_save_context;
		break;
	case 0x30:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv04_mc_init;
		engine->mc.takedown	= nv04_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv10_fb_init;
		engine->fb.takedown	= nv10_fb_takedown;
		engine->graph.init	= nv30_graph_init;
		engine->graph.takedown	= nv20_graph_takedown;
		engine->graph.create_context	= nv20_graph_create_context;
		engine->graph.destroy_context	= nv20_graph_destroy_context;
		engine->graph.load_context	= nv20_graph_load_context;
		engine->graph.save_context	= nv20_graph_save_context;
		engine->fifo.channels	= 32;
		engine->fifo.init	= nouveau_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv10_fifo_channel_id;
		engine->fifo.create_context	= nv10_fifo_create_context;
		engine->fifo.destroy_context	= nv10_fifo_destroy_context;
		engine->fifo.load_context	= nv10_fifo_load_context;
		engine->fifo.save_context	= nv10_fifo_save_context;
		break;
	case 0x40:
	case 0x60:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv40_mc_init;
		engine->mc.takedown	= nv40_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv40_fb_init;
		engine->fb.takedown	= nv40_fb_takedown;
		engine->graph.init	= nv40_graph_init;
		engine->graph.takedown	= nv40_graph_takedown;
		engine->graph.create_context	= nv40_graph_create_context;
		engine->graph.destroy_context	= nv40_graph_destroy_context;
		engine->graph.load_context	= nv40_graph_load_context;
		engine->graph.save_context	= nv40_graph_save_context;
		engine->fifo.channels	= 32;
		engine->fifo.init	= nv40_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv10_fifo_channel_id;
		engine->fifo.create_context	= nv40_fifo_create_context;
		engine->fifo.destroy_context	= nv40_fifo_destroy_context;
		engine->fifo.load_context	= nv40_fifo_load_context;
		engine->fifo.save_context	= nv40_fifo_save_context;
		break;
	case 0x50:
	case 0x80: /* gotta love NVIDIA's consistency.. */
	case 0x90:
		engine->instmem.init	= nv50_instmem_init;
		engine->instmem.takedown= nv50_instmem_takedown;
		engine->instmem.populate	= nv50_instmem_populate;
		engine->instmem.clear		= nv50_instmem_clear;
		engine->instmem.bind		= nv50_instmem_bind;
		engine->instmem.unbind		= nv50_instmem_unbind;
		engine->mc.init		= nv50_mc_init;
		engine->mc.takedown	= nv50_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nouveau_stub_init;
		engine->fb.takedown	= nouveau_stub_takedown;
		engine->graph.init	= nv50_graph_init;
		engine->graph.takedown	= nv50_graph_takedown;
		engine->graph.create_context	= nv50_graph_create_context;
		engine->graph.destroy_context	= nv50_graph_destroy_context;
		engine->graph.load_context	= nv50_graph_load_context;
		engine->graph.save_context	= nv50_graph_save_context;
		engine->fifo.channels	= 128;
		engine->fifo.init	= nv50_fifo_init;
		engine->fifo.takedown	= nv50_fifo_takedown;
		engine->fifo.channel_id		= nv50_fifo_channel_id;
		engine->fifo.create_context	= nv50_fifo_create_context;
		engine->fifo.destroy_context	= nv50_fifo_destroy_context;
		engine->fifo.load_context	= nv50_fifo_load_context;
		engine->fifo.save_context	= nv50_fifo_save_context;
		break;
	default:
		DRM_ERROR("NV%02x unsupported\n", dev_priv->chipset);
		return 1;
	}

	return 0;
}

int
nouveau_card_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine;
	int ret;

	DRM_DEBUG("prev state = %d\n", dev_priv->init_state);

	if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
		return 0;
	dev_priv->ttm = 0;

	/* Determine exact chipset we're running on */
	if (dev_priv->card_type < NV_10)
		dev_priv->chipset = dev_priv->card_type;
	else
		dev_priv->chipset =
			(NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;

	/* Initialise internal driver API hooks */
	ret = nouveau_init_engine_ptrs(dev);
	if (ret) return ret;
	engine = &dev_priv->Engine;
	dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;

	ret = nouveau_gpuobj_early_init(dev);
	if (ret) return ret;

	/* Initialise instance memory, must happen before mem_init so we
	 * know exactly how much VRAM we're able to use for "normal"
	 * purposes.
	 */
	ret = engine->instmem.init(dev);
	if (ret) return ret;

	/* Setup the memory manager */
	if (dev_priv->ttm) {
		ret = nouveau_mem_init_ttm(dev);
		if (ret) return ret;
	} else {
		ret = nouveau_mem_init(dev);
		if (ret) return ret;
	}

	ret = nouveau_gpuobj_init(dev);
	if (ret) return ret;

	/* Parse BIOS tables / Run init tables? */

	/* PMC */
	ret = engine->mc.init(dev);
	if (ret) return ret;

	/* PTIMER */
	ret = engine->timer.init(dev);
	if (ret) return ret;

	/* PFB */
	ret = engine->fb.init(dev);
	if (ret) return ret;

	/* PGRAPH */
	ret = engine->graph.init(dev);
	if (ret) return ret;

	/* PFIFO */
	ret = engine->fifo.init(dev);
	if (ret) return ret;

	/* this call irq_preinstall, register irq handler and
	 * call irq_postinstall
	 */
	ret = drm_irq_install(dev);
	if (ret) return ret;

	/* what about PVIDEO/PCRTC/PRAMDAC etc? */

	ret = nouveau_dma_channel_init(dev);
	if (ret) return ret;

	dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;

	if (drm_core_check_feature(dev, DRIVER_MODESET))
		if (dev_priv->card_type >= NV_50) {
			nv50_kms_init(dev);
			//nv50_kms_connector_detect_all(dev);
			nv50_fbcon_init(dev);
		}

	return 0;
}

static void nouveau_card_takedown(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;

	DRM_DEBUG("prev state = %d\n", dev_priv->init_state);

	if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
		nouveau_dma_channel_takedown(dev);

		engine->fifo.takedown(dev);
		engine->graph.takedown(dev);
		engine->fb.takedown(dev);
		engine->timer.takedown(dev);
		engine->mc.takedown(dev);

		nouveau_sgdma_nottm_hack_takedown(dev);
		nouveau_sgdma_takedown(dev);

		nouveau_gpuobj_takedown(dev);
		nouveau_gpuobj_del(dev, &dev_priv->vm_vram_pt);

		nouveau_mem_close(dev);
		engine->instmem.takedown(dev);

		drm_irq_uninstall(dev);

		nouveau_gpuobj_late_takedown(dev);

		dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
	}
}

/* here a client dies, release the stuff that was allocated for its
 * file_priv */
void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nouveau_fifo_cleanup(dev, file_priv);
	nouveau_mem_release(file_priv,dev_priv->fb_heap);
	nouveau_mem_release(file_priv,dev_priv->agp_heap);
	nouveau_mem_release(file_priv,dev_priv->pci_heap);
}

int nouveau_setup_mappings(struct drm_device *dev)
{
#if defined(__powerpc__)
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct device_node *dn;
#endif
	int ret;
	/* Map any PCI resources we need on the card */
	ret = nouveau_init_card_mappings(dev);
	if (ret) return ret;

#if defined(__powerpc__)
	/* Put the card in BE mode if it's not */
	if (NV_READ(NV03_PMC_BOOT_1))
		NV_WRITE(NV03_PMC_BOOT_1,0x00000001);

	DRM_MEMORYBARRIER();
#endif

#if defined(__linux__) && defined(__powerpc__)
	/* if we have an OF card, copy vbios to RAMIN */
	dn = pci_device_to_OF_node(dev->pdev);
	if (dn)
	{
		int size;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
		const uint32_t *bios = of_get_property(dn, "NVDA,BMP", &size);
#else
		const uint32_t *bios = get_property(dn, "NVDA,BMP", &size);
#endif
		if (bios)
		{
			int i;
			for(i=0;i<size;i+=4)
				NV_WI32(i, bios[i/4]);
			DRM_INFO("OF bios successfully copied (%d bytes)\n",size);
		}
		else
			DRM_INFO("Unable to get the OF bios\n");
	}
	else
		DRM_INFO("Unable to get the OF node\n");
#endif
	return 0;
}

/* first module load, setup the mmio/fb mapping */
/* KMS: we need mmio at load time, not when the first drm client opens. */
int nouveau_firstopen(struct drm_device *dev)
{
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

	return nouveau_setup_mappings(dev);
}

#define NV40_CHIPSET_MASK 0x00000baf
#define NV44_CHIPSET_MASK 0x00005450

int nouveau_load(struct drm_device *dev, unsigned long flags)
{
	struct drm_nouveau_private *dev_priv;
	void __iomem *regs;
	uint32_t reg0,reg1;
	uint8_t architecture = 0;

	dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER);
	if (!dev_priv)
		return -ENOMEM;

	dev_priv->flags = flags & NOUVEAU_FLAGS;
	dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;

	DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class);

	/* Time to determine the card architecture */
	regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8);
	if (!regs) {
		DRM_ERROR("Could not ioremap to determine register\n");
		return -ENOMEM;
	}

	reg0 = readl(regs+NV03_PMC_BOOT_0);
	reg1 = readl(regs+NV03_PMC_BOOT_1);
#if defined(__powerpc__)
	if (reg1)
		reg0=___swab32(reg0);
#endif

	/* We're dealing with >=NV10 */
	if ((reg0 & 0x0f000000) > 0 ) {
		/* Bit 27-20 contain the architecture in hex */
		architecture = (reg0 & 0xff00000) >> 20;
	/* NV04 or NV05 */
	} else if ((reg0 & 0xff00fff0) == 0x20004000) {
		architecture = 0x04;
	}

	iounmap(regs);

	if (architecture >= 0x80) {
		dev_priv->card_type = NV_50;
	} else if (architecture >= 0x60) {
		/* FIXME we need to figure out who's who for NV6x */
		dev_priv->card_type = NV_44;
	} else if (architecture >= 0x50) {
		dev_priv->card_type = NV_50;
	} else if (architecture >= 0x40) {
		uint8_t subarch = architecture & 0xf;
		/* Selection criteria borrowed from NV40EXA */
		if (NV40_CHIPSET_MASK & (1 << subarch)) {
			dev_priv->card_type = NV_40;
		} else if (NV44_CHIPSET_MASK & (1 << subarch)) {
			dev_priv->card_type = NV_44;
		} else {
			dev_priv->card_type = NV_UNKNOWN;
		}
	} else if (architecture >= 0x30) {
		dev_priv->card_type = NV_30;
	} else if (architecture >= 0x20) {
		dev_priv->card_type = NV_20;
	} else if (architecture >= 0x17) {
		dev_priv->card_type = NV_17;
	} else if (architecture >= 0x11) {
		dev_priv->card_type = NV_11;
	} else if (architecture >= 0x10) {
		dev_priv->card_type = NV_10;
	} else if (architecture >= 0x04) {
		dev_priv->card_type = NV_04;
	} else {
		dev_priv->card_type = NV_UNKNOWN;
	}

	DRM_INFO("Detected an NV%d generation card (0x%08x)\n", dev_priv->card_type,reg0);

	if (dev_priv->card_type == NV_UNKNOWN) {
		return -EINVAL;
	}

	/* For those who think they want to be funny. */
	if (dev_priv->card_type < NV_50)