/** * \file drm.h * Header for the Direct Rendering Manager * * \author Rickard E. (Rik) Faith * * \par Acknowledgments: * Dec 1999, Richard Henderson , move to generic \c cmpxchg. */ /* * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ /** * \mainpage * * The Direct Rendering Manager (DRM) is a device-independent kernel-level * device driver that provides support for the XFree86 Direct Rendering * Infrastructure (DRI). * * The DRM supports the Direct Rendering Infrastructure (DRI) in four major * ways: * -# The DRM provides synchronized access to the graphics hardware via * the use of an optimized two-tiered lock. * -# The DRM enforces the DRI security policy for access to the graphics * hardware by only allowing authenticated X11 clients access to * restricted regions of memory. * -# The DRM provides a generic DMA engine, complete with multiple * queues and the ability to detect the need for an OpenGL context * switch. * -# The DRM is extensible via the use of small device-specific modules * that rely extensively on the API exported by the DRM module. * */ #ifndef _DRM_H_ #define _DRM_H_ #ifndef __user #define __user #endif #ifndef __iomem #define __iomem #endif #ifdef __GNUC__ # define DEPRECATED __attribute__ ((deprecated)) #else # define DEPRECATED #endif #if defined(__linux__) #include /* For _IO* macros */ #define DRM_IOCTL_NR(n) _IOC_NR(n) #define DRM_IOC_VOID _IOC_NONE #define DRM_IOC_READ _IOC_READ #define DRM_IOC_WRITE _IOC_WRITE #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) #include #define DRM_IOCTL_NR(n) ((n) & 0xff) #define DRM_IOC_VOID IOC_VOID #define DRM_IOC_READ IOC_OUT #define DRM_IOC_WRITE IOC_IN #define DRM_IOC_READWRITE IOC_INOUT #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) #endif #ifdef __OpenBSD__ #define DRM_MAJOR 81 #endif #if defined(__linux__) || defined(__NetBSD__) #define DRM_MAJOR 226 #endif #define DRM_MAX_MINOR 15 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) #if defined(__linux__) typedef unsigned int drm_handle_t; #else #include typedef unsigned long drm_handle_t; /**< To mapped regions */ #endif typedef unsigned int drm_context_t; /**< GLXContext handle */ typedef unsigned int drm_drawable_t; typedef unsigned int drm_magic_t; /**< Magic for authentication */ /** * Cliprect. * * \warning If you change this structure, make sure you change * XF86DRIClipRectRec in the server as well * * \note KW: Actually it's illegal to change either for * backwards-compatibility reasons. */ struct drm_clip_rect { unsigned short x1; unsigned short y1; unsigned short x2; unsigned short y2; }; /** * Texture region, */ struct drm_tex_region { unsigned char next; unsigned char prev; unsigned char in_use; unsigned char padding; unsigned int age; }; /** * Hardware lock. * * The lock structure is a simple cache-line aligned integer. To avoid * processor bus contention on a multiprocessor system, there should not be any * other data stored in the same cache line. */ struct drm_hw_lock { __volatile__ unsigned int lock; /**< lock variable */ char padding[60]; /**< Pad to cache line */ }; /* This is beyond ugly, and only works on GCC. However, it allows me to use * drm.h in places (i.e., in the X-server) where I can't use size_t. The real * fix is to use uint32_t instead of size_t, but that fix will break existing * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will* * eventually happen, though. I chose 'unsigned long' to be the fallback type * because that works on all the platforms I know about. Hopefully, the * real fix will happen before that bites us. */ #ifdef __SIZE_TYPE__ # define DRM_SIZE_T __SIZE_TYPE__ #else # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!" # define DRM_SIZE_T unsigned long #endif /** * DRM_IOCTL_VERSION ioctl argument type. * * \sa drmGetVersion(). */ struct drm_version { int version_major; /**< Major version */ int version_minor; /**< Minor version */ int version_patchlevel; /**< Patch level */ DRM_SIZE_T name_len; /**< Length of name buffer */ char __user *name; /**< Name of driver */ DRM_SIZE_T date_len; /**< Length of date buffer */ char __user *date; /**< User-space buffer to hold date */ DRM_SIZE_T desc_len; /**< Length of desc buffer */ char __user *desc; /**< User-space buffer to hold desc */ }; /** * DRM_IOCTL_GET_UNIQUE ioctl argument type. * * \sa drmGetBusid() and drmSetBusId(). */ struct drm_unique { DRM_SIZE_T unique_len; /**< Length of unique */ char __user *unique; /**< Unique name for driver instantiation */ }; #undef DRM_SIZE_T struct drm_list { int count; /**< Length of user-space structures */ struct drm_version __user *version; }; struct drm_block { int unused; }; /** * DRM_IOCTL_CONTROL ioctl argument type. * * \sa drmCtlInstHandler() and drmCtlUninstHandler(). */ struct drm_control { enum { DRM_ADD_COMMAND, DRM_RM_COMMAND, DRM_INST_HANDLER, DRM_UNINST_HANDLER } func; int irq; }; /** * Type of memory to map. */ enum drm_map_type { _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ _DRM_REGISTERS = 1, /**< no caching, no core dump */ _DRM_SHM = 2, /**< shared, cached */ _DRM_AGP = 3, /**< AGP/GART */ _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ _DRM_TTM = 6 }; /** * Memory mapping flags. */ enum drm_map_flags { _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ _DRM_READ_ONLY = 0x02, _DRM_LOCKED = 0x04, /**< shared, cached, locked */ _DRM_KERNEL = 0x08, /**< kernel requires access */ _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ _DRM_REMOVABLE = 0x40, /**< Removable mapping */ _DRM_DRIVER = 0x80 /**< Managed by driver */ }; struct drm_ctx_priv_map { unsigned int ctx_id; /**< Context requesting private mapping */ void *handle; /**< Handle of map */ }; /** * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls * argument type. * * \sa drmAddMap(). */ struct drm_map { unsigned long offset; /**< Requested physical address (0 for SAREA)*/ unsigned long size; /**< Requested physical size (bytes) */ enum drm_map_type type; /**< Type of memory to map */ enum drm_map_flags flags; /**< Flags */ void *handle; /**< User-space: "Handle" to pass to mmap() */ /**< Kernel-space: kernel-virtual address */ int mtrr; /**< MTRR slot used */ /* Private data */ }; /** * DRM_IOCTL_GET_CLIENT ioctl argument type. */ struct drm_client { int idx; /**< Which client desired? */ int auth; /**< Is client authenticated? */ unsigned long pid; /**< Process ID */ unsigned long uid; /**< User ID */ unsigned long magic; /**< Magic */ unsigned long iocs; /**< Ioctl count */ }; enum drm_stat_type { _DRM_STAT_LOCK, _DRM_STAT_OPENS, _DRM_STAT_CLOSES, _DRM_STAT_IOCTLS, _DRM_STAT_LOCKS, _DRM_STAT_UNLOCKS, _DRM_STAT_VALUE, /**< Generic value */ _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ _DRM_STAT_IRQ, /**< IRQ */ _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ _DRM_STAT_DMA, /**< DMA */ _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ _DRM_STAT_MISSED /**< Missed DMA opportunity */ /* Add to the *END* of the list */ }; /** * DRM_IOCTL_GET_STATS ioctl argument type. */ struct drm_stats { unsigned long count; struct { unsigned long value; enum drm_stat_type type; } data[15]; }; /** * Hardware locking flags. */ enum drm_lock_flags { _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ /* These *HALT* flags aren't supported yet -- they will be used to support the full-screen DGA-like mode. */ _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ }; /** * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. * * \sa drmGetLock() and drmUnlock(). */ struct drm_lock { int context; enum drm_lock_flags flags; }; /** * DMA flags * * \warning * These values \e must match xf86drm.h. * * \sa drm_dma. */ enum drm_dma_flags { /* Flags for DMA buffer dispatch */ _DRM_DMA_BLOCK = 0x01, /**< * Block until buffer dispatched. * * \note The buffer may not yet have * been processed by the hardware -- * getting a hardware lock with the * hardware quiescent will ensure * that the buffer has been * processed. */ _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ /* Flags for DMA buffer request */ _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ }; /** * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. * * \sa drmAddBufs(). */ struct drm_buf_desc { int count; /**< Number of buffers of this size */ int size; /**< Size in bytes */ int low_mark; /**< Low water mark */ int high_mark; /**< High water mark */ enum { _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ } flags; unsigned long agp_start; /**< * Start address of where the AGP buffers are * in the AGP aperture */ }; /** * DRM_IOCTL_INFO_BUFS ioctl argument type. */ struct drm_buf_info { int count; /**< Number of buffers described in list */ struct drm_buf_desc __user *list; /**< List of buffer descriptions */ }; /** * DRM_IOCTL_FREE_BUFS ioctl argument type. */ struct drm_buf_free { int count; int __user *list; }; /** * Buffer information * * \sa drm_buf_map. */ struct drm_buf_pub { int idx; /**< Index into the master buffer list */ int total; /**< Buffer size */ int used; /**< Amount of buffer in use (for DMA) */ void __user *address; /**< Address of buffer */ }; /** * DRM_IOCTL_MAP_BUFS ioctl argument type. */ struct drm_buf_map { int count; /**< Length of the buffer list */ #if defined(__cplusplus) void __user *c_virtual; #else void __user *virtual; /**< Mmap'd area in user-virtual */ #endif struct drm_buf_pub __user *list; /**< Buffer information */ }; /** * DRM_IOCTL_DMA ioctl argument type. * * Indices here refer to the offset into the buffer list in drm_buf_get. * * \sa drmDMA(). */ struct drm_dma { int context; /**< Context handle */ int send_count; /**< Number of buffers to send */ int __user *send_indices; /**< List of handles to buffers */ int __user *send_sizes; /**< Lengths of data to send */ enum drm_dma_flags flags; /**< Flags */ int request_count; /**< Number of buffers requested */ int request_size; /**< Desired size for buffers */ int __user *request_indices; /**< Buffer information */ int __user *request_sizes; int granted_count; /**< Number of buffers granted */ }; enum drm_ctx_flags { _DRM_CONTEXT_PRESERVED = 0x01, _DRM_CONTEXT_2DONLY = 0x02 }; /** * DRM_IOCTL_ADD_CTX ioctl argument type. * * \sa drmCreateContext() and drmDestroyContext(). */ struct drm_ctx { drm_context_t handle; enum drm_ctx_flags flags; }; /** * DRM_IOCTL_RES_CTX ioctl argument type. */ struct drm_ctx_res { int count; struct drm_ctx __user *contexts; }; /** * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. */ struct drm_draw { drm_drawable_t handle; }; /** * DRM_IOCTL_UPDATE_DRAW ioctl argument type. */ typedef enum { DRM_DRAWABLE_CLIPRECTS, } drm_drawable_info_type_t; struct drm_update_draw { drm_drawable_t handle; unsigned int type; unsigned int num; unsigned long long data; }; /** * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. */ struct drm_auth { drm_magic_t magic; }; /** * DRM_IOCTL_IRQ_BUSID ioctl argument type. * * \sa drmGetInterruptFromBusID(). */ struct drm_irq_busid { int irq; /**< IRQ number */ int busnum; /**< bus number */ int devnum; /**< device number */ int funcnum; /**< function number */ }; enum drm_vblank_seq_type { _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ }; #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ _DRM_VBLANK_NEXTONMISS) struct drm_wait_vblank_request { enum drm_vblank_seq_type type; unsigned int sequence; unsigned long signal; }; struct drm_wait_vblank_reply { enum drm_vblank_seq_type type; unsigned int sequence; long tval_sec; long tval_usec; }; /** * DRM_IOCTL_WAIT_VBLANK ioctl argument type. * * \sa drmWaitVBlank(). */ union drm_wait_vblank { struct drm_wait_vblank_request request; struct drm_wait_vblank_reply reply; }; /* Handle monitor hotplug. * * May want to extend this later to pass reply information which * details the connectors which generated the hotplug event. * Some chipsets can't determine that though, and we'd need to leave * it to the higher levels to determine exactly what changed. */ enum drm_hotplug_seq_type { _DRM_HOTPLUG_SIGNAL = 0x00000001, /**< Send signal instead of blocking */ }; struct drm_wait_hotplug_request { enum drm_hotplug_seq_type type; unsigned long signal; }; struct drm_wait_hotplug_reply { enum drm_hotplug_seq_type type; unsigned int counter; long tval_sec; long tval_usec; }; /** * DRM_IOCTL_WAIT_HOTPLUG ioctl argument type. * * \sa drmWaitHotplug(). */ union drm_wait_hotplug { struct drm_wait_hotplug_request request; struct drm_wait_hotplug_reply reply; }; enum drm_modeset_ctl_cmd { _DRM_PRE_MODESET = 1, _DRM_POST_MODESET = 2, }; /** * DRM_IOCTL_MODESET_CTL ioctl argument type * * \sa drmModesetCtl(). */ struct drm_modeset_ctl { uint32_t crtc; uint32_t cmd; }; /** * DRM_IOCTL_AGP_ENABLE ioctl argument type. * * \sa drmAgpEnable(). */ struct drm_agp_mode { unsigned long mode; /**< AGP mode */ }; /** * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. * * \sa drmAgpAlloc() and drmAgpFree(). */ struct drm_agp_buffer { unsigned long size; /**< In bytes -- will round to page boundary */ unsigned long handle; /**< Used for binding / unbinding */ unsigned long type; /**< Type of memory to allocate */ unsigned long physical; /**< Physical used by i810 */ }; /** * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. * * \sa drmAgpBind() and drmAgpUnbind(). */ struct drm_agp_binding { unsigned long handle; /**< From drm_agp_buffer */ unsigned long offset; /**< In bytes -- will round to page boundary */ }; /** * DRM_IOCTL_AGP_INFO ioctl argument type. * * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), * drmAgpVendorId() and drmAgpDeviceId(). */ struct drm_agp_info { int agp_version_major; int agp_version_minor; unsigned long mode; unsigned long aperture_base; /**< physical address */ unsigned long aperture_size; /**< bytes */ unsigned long memory_allowed; /**< bytes */ unsigned long memory_used; /** \name PCI information */ /*@{ */ unsigned short id_vendor; unsigned short id_device; /*@} */ }; /** * DRM_IOCTL_SG_ALLOC ioctl argument type. */ struct drm_scatter_gather { unsigned long size; /**< In bytes -- will round to page boundary */ unsigned long handle; /**< Used for mapping / unmapping */ }; /** * DRM_IOCTL_SET_VERSION ioctl argument type. */ struct drm_set_version { int drm_di_major; int drm_di_minor; int drm_dd_major; int drm_dd_minor; }; #define DRM_FENCE_FLAG_EMIT 0x00000001 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002 /** * On hardware with no interrupt events for operation completion, * indicates that the kernel should sleep while waiting for any blocking * operation to complete rather than spinning. * * Has no effect otherwise. */ #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004 #define DRM_FENCE_FLAG_NO_USER 0x00000010 /* Reserved for driver use */ #define DRM_FENCE_MASK_DRIVER 0xFF000000 #define DRM_FENCE_TYPE_EXE 0x00000001 struct drm_fence_arg { unsigned int handle; unsigned int fence_class; unsigned int type; unsigned int flags; unsigned int signaled; unsigned int error; unsigned int sequence; unsigned int pad64; uint64_t expand_pad[2]; /*Future expansion */ }; /* Buffer permissions, referring to how the GPU uses the buffers. * these translate to fence types used for the buffers. * Typically a texture buffer is read, A destination buffer is write and * a command (batch-) buffer is exe. Can be or-ed together. */ #define DRM_BO_FLAG_READ (1ULL << 0) #define DRM_BO_FLAG_WRITE (1ULL << 1) #define DRM_BO_FLAG_EXE (1ULL << 2) /* * All of the bits related to access mode */ #define DRM_BO_MASK_ACCESS (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE) /* * Status flags. Can be read to determine the actual state of a buffer. * Can also be set in the buffer mask before validation. */ /* * Mask: Never evict this buffer. Not even with force. This type of buffer is only * available to root and must be manually removed before buffer manager shutdown * or lock. * Flags: Acknowledge */ #define DRM_BO_FLAG_NO_EVICT (1ULL << 4) /* * Mask: Require that the buffer is placed in mappable memory when validated. * If not set the buffer may or may not be in mappable memory when validated. * Flags: If set, the buffer is in mappable memory. */ #define DRM_BO_FLAG_MAPPABLE (1ULL << 5) /* Mask: The buffer should be shareable with other processes. * Flags: The buffer is shareable with other processes. */ #define DRM_BO_FLAG_SHAREABLE (1ULL << 6) /* Mask: If set, place the buffer in cache-coherent memory if available. * If clear, never place the buffer in cache coherent memory if validated. * Flags: The buffer is currently in cache-coherent memory. */ #define DRM_BO_FLAG_CACHED (1ULL << 7) /* Mask: Make sure that every time this buffer is validated, * it ends up on the same location provided that the memory mask is the same. * The buffer will also not be evicted when claiming space for * other buffers. Basically a pinned buffer but it may be thrown out as * part of buffer manager shutdown or locking. * Flags: Acknowledge. */ #define DRM_BO_FLAG_NO_MOVE (1ULL << 8) /* Mask: Make sure the buffer is in cached memory when mapped. In conjunction * with DRM_BO_FLAG_CACHED it also allows the buffer to be bound into the GART * with unsnooped PTEs instead of snooped, by using chipset-specific cache * flushing at bind time. A better name might be DRM_BO_FLAG_TT_UNSNOOPED, * as the eviction to local memory (TTM unbind) on map is just a side effect * to prevent aggressive cache prefetch from the GPU disturbing the cache * management that the DRM is doing. * * Flags: Acknowledge. * Buffers allocated with this flag should not be used for suballocators * This type may have issues on CPUs with over-aggressive caching * http://marc.info/?l=linux-kernel&m=102376926732464&w=2 */ #define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19) /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set. * Flags: Acknowledge. */ #define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13) /* * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear. * Flags: Acknowledge. */ #define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14) #define DRM_BO_FLAG_TILE (1ULL << 15) /* * Memory type flags that can be or'ed together in the mask, but only * one appears in flags. */ /* System memory */ #define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24) /* Translation table memory */ #define DRM_BO_FLAG_MEM_TT (1ULL << 25) /* Vram memory */ #define DRM_BO_FLAG_MEM_VRAM (1ULL << 26) /* Up to the driver to define. */ #define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27) #define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28) #define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29) #define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30) #define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31) /* We can add more of these now with a 64-bit flag type */ /* * This is a mask covering all of the memory type flags; easier to just * use a single constant than a bunch of | values. It covers * DRM_BO_FLAG_MEM_LOCAL through DRM_BO_FLAG_MEM_PRIV4 */ #define DRM_BO_MASK_MEM 0x00000000FF000000ULL /* * This adds all of the CPU-mapping options in with the memory * type to label all bits which change how the page gets mapped */ #define DRM_BO_MASK_MEMTYPE (DRM_BO_MASK_MEM | \ DRM_BO_FLAG_CACHED_MAPPED | \ DRM_BO_FLAG_CACHED | \ DRM_BO_FLAG_MAPPABLE) /* Driver-private flags */ #define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL /* * Don't block on validate and map. Instead, return EBUSY. */ #define DRM_BO_HINT_DONT_BLOCK 0x00000002 /* * Don't place this buffer on the unfenced list. This means * that the buffer will not end up having a fence associated * with it as a result of this operation */ #define DRM_BO_HINT_DONT_FENCE 0x00000004 /** * On hardware with no interrupt events for operation completion, * indicates that the kernel should sleep while waiting for any blocking * operation to complete rather than spinning. * * Has no effect otherwise. */ #define DRM_BO_HINT_WAIT_LAZY 0x00000008 /* * The client has compute relocations refering to this buffer using the * offset in the presumed_offset field. If that offset ends up matching * where this buffer lands, the kernel is free to skip executing those * relocations */ #define DRM_BO_HINT_PRESUMED_OFFSET 0x00000010 #define DRM_BO_INIT_MAGIC 0xfe769812 #define DRM_BO_INIT_MAJOR 1 #define DRM_BO_INIT_MINOR 0 #define DRM_BO_INIT_PATCH 0 struct drm_bo_info_req { uint64_t mask; uint64_t flags; unsigned int handle; unsigned int hint; unsigned int fence_class; unsigned int desired_tile_stride; unsigned int tile_info; unsigned int pad64; uint64_t presumed_offset; }; struct drm_bo_create_req { uint64_t flags; uint64_t size; uint64_t buffer_start; unsigned int hint; unsigned int page_alignment; }; /* * Reply flags */ #define DRM_BO_REP_BUSY 0x00000001 struct drm_bo_info_rep { uint64_t flags; uint64_t proposed_flags; uint64_t size; uint64_t offset; uint64_t arg_handle; uint64_t buffer_start; unsigned int handle; unsigned int fence_flags; unsigned int rep_flags; unsigned int page_alignment; unsigned int desired_tile_stride; unsigned int hw_tile_stride; unsigned int tile_info; unsigned int pad64; uint64_t expand_pad[4]; /*Future expansion */ }; struct drm_bo_arg_rep { struct drm_bo_info_rep bo_info; int ret; unsigned int pad64; }; struct drm_bo_create_arg { union { struct drm_bo_create_req req; struct drm_bo_info_rep rep; } d; }; struct drm_bo_handle_arg { unsigned int handle; }; struct drm_bo_reference_info_arg { union { struct drm_bo_handle_arg req; struct drm_bo_info_rep rep; } d; }; struct drm_bo_map_wait_idle_arg { union { struct drm_bo_info_req req; struct drm_bo_info_rep rep; } d; }; struct drm_bo_op_req { enum { drm_bo_validate, drm_bo_fence, drm_bo_ref_fence, } op; unsigned int arg_handle; struct drm_bo_info_req bo_req; }; struct drm_bo_op_arg { uint64_t next; union { struct drm_bo_op_req req; struct drm_bo_arg_rep rep; } d; int handled; unsigned int pad64; }; #define DRM_BO_MEM_LOCAL 0 #define DRM_BO_MEM_TT 1 #define DRM_BO_MEM_VRAM 2 #define DRM_BO_MEM_PRIV0 3 #define DRM_BO_MEM_PRIV1 4 #define DRM_BO_MEM_PRIV2 5 #define DRM_BO_MEM_PRIV3 6 #define DRM_BO_MEM_PRIV4 7 #define DRM_BO_MEM_TYPES 8 /* For now. */ #define DRM_BO_LOCK_UNLOCK_BM (1 << 0) #define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1) struct drm_bo_version_arg { uint32_t major; uint32_t minor; uint32_t patchlevel; }; struct drm_mm_type_arg { unsigned int mem_type; unsigned int lock_flags; }; struct drm_mm_init_arg { unsigned int magic; unsigned int major; unsigned int minor; unsigned int mem_type; uint64_t p_offset; uint64_t p_size; }; struct drm_mm_info_arg { unsigned int mem_type; uint64_t p_size; }; /* * Drm mode setting */ #define DRM_DISPLAY_INFO_LEN 32 #define DRM_CONNECTOR_NAME_LEN 32 #define DRM_DISPLAY_MODE_LEN 32 #define DRM_PROP_NAME_LEN 32 #define DRM_MODE_TYPE_BUILTIN (1<<0) #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) #define DRM_MODE_TYPE_PREFERRED (1<<3) #define DRM_MODE_TYPE_DEFAULT (1<<4) #define DRM_MODE_TYPE_USERDEF (1<<5) #define DRM_MODE_TYPE_DRIVER (1<<6) struct drm_mode_modeinfo { unsigned int clock; unsigned short hdisplay, hsync_start, hsync_end, htotal, hskew; unsigned short vdisplay, vsync_start, vsync_end, vtotal, vscan; unsigned int vrefresh; /* vertical refresh * 1000 */ unsigned int flags; unsigned int type; char name[DRM_DISPLAY_MODE_LEN]; }; struct drm_mode_card_res { uint64_t fb_id_ptr; uint64_t crtc_id_ptr; uint64_t connector_id_ptr; uint64_t encoder_id_ptr; int count_fbs; int count_crtcs; int count_connectors; int count_encoders; int min_width, max_width; int min_height, max_height; uint32_t generation; }; struct drm_mode_crtc { uint64_t set_connectors_ptr; unsigned int crtc_id; /**< Id */ unsigned int fb_id; /**< Id of framebuffer */ int x, y; /**< Position on the frameuffer */ uint32_t generation; int count_connectors; unsigned int connectors; /**< Connectors that are connected */ int count_possibles; unsigned int possibles; /**< Connectors that can be connected */ uint32_t gamma_size; int mode_valid; struct drm_mode_modeinfo mode; }; struct drm_mode_get_encoder { uint32_t generation; uint32_t encoder_type; uint32_t encoder_id; unsigned int crtc; /**< Id of crtc */ uint32_t crtcs; uint32_t clones; }; #define DRM_MODE_ENCODER_NONE 0 #define DRM_MODE_ENCODER_DAC 1 #define DRM_MODE_ENCODER_TMDS 2 #define DRM_MODE_ENCODER_LVDS 3 #define DRM_MODE_ENCODER_TVDAC 4 struct drm_mode_get_connector { uint64_t encoders_ptr; uint64_t modes_ptr; uint64_t props_ptr; uint64_t prop_values_ptr; int count_modes; int count_props; int count_encoders; unsigned int encoder; /**< Current Encoder */ unsigned int connector; /**< Id */ unsigned int connector_type; unsigned int connector_type_id; uint32_t generation; unsigned int connection; unsigned int mm_width, mm_height; /**< HxW in millimeters */ unsigned int subpixel; }; #define DRM_MODE_PROP_PENDING (1<<0) #define DRM_MODE_PROP_RANGE (1<<1) #define DRM_MODE_PROP_IMMUTABLE (1<<2) #define DRM_MODE_PROP_ENUM (1<<3) // enumerated type with text strings #define DRM_MODE_PROP_BLOB (1<<4) struct drm_mode_property_enum { uint64_t value; unsigned char name[DRM_PROP_NAME_LEN]; }; struct drm_mode_get_property { uint64_t values_ptr; /* values and blob lengths */ uint64_t enum_blob_ptr; /* enum and blob id ptrs */ unsigned int prop_id; unsigned int flags; unsigned char name[DRM_PROP_NAME_LEN]; int count_values; int count_enum_blobs; }; struct drm_mode_connector_set_property { uint64_t value; unsigned int prop_id; unsigned int connector_id; }; struct drm_mode_get_blob { uint32_t blob_id; uint32_t length; uint64_t data; }; struct drm_mode_fb_cmd { unsigned int buffer_id; unsigned int width, height; unsigned int pitch; unsigned int bpp; unsigned int handle; unsigned int depth; }; struct drm_mode_mode_cmd { unsigned int connector_id; struct drm_mode_modeinfo mode; }; #define DRM_MODE_CURSOR_BO 0x01 #define DRM_MODE_CURSOR_MOVE 0x02 /* * depending on the value in flags diffrent members are used. * * CURSOR_BO uses * crtc * width * height * handle - if 0 turns the cursor of * * CURSOR_MOVE uses * crtc * x * y */ struct drm_mode_cursor { unsigned int flags; unsigned int crtc; int x; int y; uint32_t width; uint32_t height; unsigned int handle; }; /* * oh so ugly hotplug */ struct drm_mode_hotplug { uint32_t counter; }; struct drm_mode_crtc_lut { uint32_t crtc_id; uint32_t gamma_size; uint64_t red; uint64_t green; uint64_t blue; }; /** * \name Ioctls Definitions */ /*@{*/ #define DRM_IOCTL_BASE 'd' #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) #define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg) #define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg) #define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg) #define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg) #define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg) #define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg) #define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg) #define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg) #define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg) #define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg) #define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg) #define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg) #define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg) #define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg) #define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg) #define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg) #define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg) #define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg) #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) #define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg) #define DRM_IOCTL_MM_INFO DRM_IOWR(0xd7, struct drm_mm_info_arg) #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA2, struct drm_mode_get_connector) #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA3, struct drm_mode_crtc) #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xA4, struct drm_mode_fb_cmd) #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xA5, unsigned int) #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xA6, struct drm_mode_fb_cmd) #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xA7, struct drm_mode_connector_set_property) #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xA8, struct drm_mode_get_blob) #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xAA, struct drm_mode_mode_cmd) #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAB, struct drm_mode_get_property) #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xAC, struct drm_mode_cursor) #define DRM_IOCTL_MODE_HOTPLUG DRM_IOWR(0xAD, struct drm_mode_hotplug) #define DRM_IOCTL_WAIT_HOTPLUG DRM_IOWR(0xAE, union drm_wait_hotplug) #define DRM_IOCTL_MODE_REPLACEFB DRM_IOWR(0xAF, struct drm_mode_fb_cmd) #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xB0, struct drm_mode_get_encoder) #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xB1, struct drm_mode_crtc_lut) #define DRM_/* mach64_drv.h -- Private header for mach64 driver -*- linux-c -*- * Created: Fri Nov 24 22:07:58 2000 by gareth@valinux.com * * Copyright 2000 Gareth Hughes * Copyright 2002 Frank C. Earl * Copyright 2002-2003 Leif Delgass * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Gareth Hughes <gareth@valinux.com> * Frank C. Earl <fearl@airmail.net> * Leif Delgass <ldelgass@retinalburn.net> * José Fonseca <j_r_fonseca@yahoo.co.uk> */ #ifndef __MACH64_DRV_H__ #define __MACH64_DRV_H__ /* FIXME: remove these when not needed */ /* Development driver options */ #define MACH64_EXTRA_CHECKING 0 /* Extra sanity checks for DMA/freelist management */ #define MACH64_VERBOSE 0 /* Verbose debugging output */ typedef struct drm_mach64_freelist { struct list_head list; /* List pointers for free_list, placeholders, or pending list */ drm_buf_t *buf; /* Pointer to the buffer */ int discard; /* This flag is set when we're done (re)using a buffer */ u32 ring_ofs; /* dword offset in ring of last descriptor for this buffer */ } drm_mach64_freelist_t; typedef struct drm_mach64_descriptor_ring { dma_addr_t handle; /* handle (bus address) of ring returned by pci_alloc_consistent() */ void *start; /* write pointer (cpu address) to start of descriptor ring */ u32 start_addr; /* bus address of beginning of descriptor ring */ int size; /* size of ring in bytes */ u32 head_addr; /* bus address of descriptor ring head */ u32 head; /* dword offset of descriptor ring head */ u32 tail; /* dword offset of descriptor ring tail */ u32 tail_mask; /* mask used to wrap ring */ int space; /* number of free bytes in ring */ } drm_mach64_descriptor_ring_t; typedef struct drm_mach64_private { drm_mach64_sarea_t *sarea_priv; int is_pci; drm_mach64_dma_mode_t driver_mode; /* Async DMA, sync DMA, or MMIO */ int usec_timeout; /* Timeout for the wait functions */ drm_mach64_descriptor_ring_t ring; /* DMA descriptor table (ring buffer) */ int ring_running; /* Is bus mastering is enabled */ struct list_head free_list; /* Free-list head */ struct list_head placeholders; /* Placeholder list for buffers held by clients */ struct list_head pending; /* Buffers pending completion */ u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */ unsigned int fb_bpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_bpp; unsigned int depth_offset, depth_pitch; u32 front_offset_pitch; u32 back_offset_pitch; u32 depth_offset_pitch; drm_local_map_t *sarea; drm_local_map_t *fb; drm_local_map_t *mmio; drm_local_map_t *ring_map; drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */ drm_local_map_t *agp_textures; } drm_mach64_private_t; /* mach64_dma.c */ extern int mach64_dma_init( DRM_IOCTL_ARGS ); extern int mach64_dma_idle( DRM_IOCTL_ARGS ); extern int mach64_dma_flush( DRM_IOCTL_ARGS ); extern int mach64_engine_reset( DRM_IOCTL_ARGS ); extern int mach64_dma_buffers( DRM_IOCTL_ARGS ); extern int mach64_init_freelist( drm_device_t *dev ); extern void mach64_destroy_freelist( drm_device_t *dev ); extern drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv ); extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, int entries ); extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv ); extern int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n ); extern int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ); extern int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv ); extern void mach64_dump_engine_info( drm_mach64_private_t *dev_priv ); extern void mach64_dump_ring_info( drm_mach64_private_t *dev_priv ); extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv ); extern int mach64_do_dma_idle( drm_mach64_private_t *dev_priv ); extern int mach64_do_dma_flush( drm_mach64_private_t *dev_priv ); extern int mach64_do_cleanup_dma( drm_device_t *dev ); /* mach64_state.c */ extern int mach64_dma_clear( DRM_IOCTL_ARGS ); extern int mach64_dma_swap( DRM_IOCTL_ARGS ); extern int mach64_dma_vertex( DRM_IOCTL_ARGS ); extern int mach64_dma_blit( DRM_IOCTL_ARGS ); extern int mach64_get_param( DRM_IOCTL_ARGS ); extern int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); extern irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS ); extern void mach64_driver_irq_preinstall( drm_device_t *dev ); extern void mach64_driver_irq_postinstall( drm_device_t *dev ); extern void mach64_driver_irq_uninstall( drm_device_t *dev ); /* ================================================================ * Registers */ #define MACH64_AGP_BASE 0x0148 #define MACH64_AGP_CNTL 0x014c #define MACH64_ALPHA_TST_CNTL 0x0550 #define MACH64_DSP_CONFIG 0x0420 #define MACH64_DSP_ON_OFF 0x0424 #define MACH64_EXT_MEM_CNTL 0x04ac #define MACH64_GEN_TEST_CNTL 0x04d0 #define MACH64_HW_DEBUG 0x047c #define MACH64_MEM_ADDR_CONFIG 0x0434 #define MACH64_MEM_BUF_CNTL 0x042c #define MACH64_MEM_CNTL 0x04b0 #define MACH64_BM_ADDR 0x0648 #define MACH64_BM_COMMAND 0x0188 #define MACH64_BM_DATA 0x0648 #define MACH64_BM_FRAME_BUF_OFFSET 0x0180 #define MACH64_BM_GUI_TABLE 0x01b8 #define MACH64_BM_GUI_TABLE_CMD 0x064c # define MACH64_CIRCULAR_BUF_SIZE_16KB (0 << 0) # define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0) # define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0) # define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0) # define MACH64_LAST_DESCRIPTOR (1 << 31) #define MACH64_BM_HOSTDATA 0x0644 #define MACH64_BM_STATUS 0x018c #define MACH64_BM_SYSTEM_MEM_ADDR 0x0184 #define MACH64_BM_SYSTEM_TABLE 0x01bc #define MACH64_BUS_CNTL 0x04a0 # define MACH64_BUS_MSTR_RESET (1 << 1) # define MACH64_BUS_APER_REG_DIS (1 << 4) # define MACH64_BUS_FLUSH_BUF (1 << 2) # define MACH64_BUS_MASTER_DIS (1 << 6) # define MACH64_BUS_EXT_REG_EN (1 << 27) #define MACH64_CLR_CMP_CLR 0x0700 #define MACH64_CLR_CMP_CNTL 0x0708 #define MACH64_CLR_CMP_MASK 0x0704 #define MACH64_CONFIG_CHIP_ID 0x04e0 #define MACH64_CONFIG_CNTL 0x04dc #define MACH64_CONFIG_STAT0 0x04e4 #define MACH64_CONFIG_STAT1 0x0494 #define MACH64_CONFIG_STAT2 0x0498 #define MACH64_CONTEXT_LOAD_CNTL 0x072c #define MACH64_CONTEXT_MASK 0x0720 #define MACH64_COMPOSITE_SHADOW_ID 0x0798 #define MACH64_CRC_SIG 0x04e8 #define MACH64_CUSTOM_MACRO_CNTL 0x04d4 #define MACH64_DP_BKGD_CLR 0x06c0 #define MACH64_DP_FOG_CLR 0x06c4 #define MACH64_DP_FGRD_BKGD_CLR 0x06e0 #define MACH64_DP_FRGD_CLR 0x06c4 #define MACH64_DP_FGRD_CLR_MIX 0x06dc #define MACH64_DP_MIX 0x06d4 # define BKGD_MIX_NOT_D (0 << 0) # define BKGD_MIX_ZERO (1 << 0) # define BKGD_MIX_ONE (2 << 0) # define MACH64_BKGD_MIX_D (3 << 0) # define BKGD_MIX_NOT_S (4 << 0) # define BKGD_MIX_D_XOR_S (5 << 0) # define BKGD_MIX_NOT_D_XOR_S (6 << 0) # define MACH64_BKGD_MIX_S (7 << 0) # define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) # define BKGD_MIX_D_OR_NOT_S (9 << 0) # define BKGD_MIX_NOT_D_OR_S (10 << 0) # define BKGD_MIX_D_OR_S (11 << 0) # define BKGD_MIX_D_AND_S (12 << 0) # define BKGD_MIX_NOT_D_AND_S (13 << 0) # define BKGD_MIX_D_AND_NOT_S (14 << 0) # define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0) # define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0) # define FRGD_MIX_NOT_D (0 << 16) # define FRGD_MIX_ZERO (1 << 16) # define FRGD_MIX_ONE (2 << 16) # define FRGD_MIX_D (3 << 16) # define FRGD_MIX_NOT_S (4 << 16) # define FRGD_MIX_D_XOR_S (5 << 16) # define FRGD_MIX_NOT_D_XOR_S (6 << 16) # define MACH64_FRGD_MIX_S (7 << 16) # define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16) # define FRGD_MIX_D_OR_NOT_S (9 << 16) # define FRGD_MIX_NOT_D_OR_S (10 << 16) # define FRGD_MIX_D_OR_S (11 << 16) # define FRGD_MIX_D_AND_S (12 << 16) # define FRGD_MIX_NOT_D_AND_S (13 << 16) # define FRGD_MIX_D_AND_NOT_S (14 << 16) # define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16) # define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16) #define MACH64_DP_PIX_WIDTH 0x06d0 # define MACH64_HOST_TRIPLE_ENABLE (1 << 13) # define MACH64_BYTE_ORDER_MSB_TO_LSB (0 << 24) # define MACH64_BYTE_ORDER_LSB_TO_MSB (1 << 24) #define MACH64_DP_SRC 0x06d8 # define MACH64_BKGD_SRC_BKGD_CLR (0 << 0) # define MACH64_BKGD_SRC_FRGD_CLR (1 << 0) # define MACH64_BKGD_SRC_HOST (2 << 0) # define MACH64_BKGD_SRC_BLIT (3 << 0) # define MACH64_BKGD_SRC_PATTERN (4 << 0) # define MACH64_BKGD_SRC_3D (5 << 0) # define MACH64_FRGD_SRC_BKGD_CLR (0 << 8) # define MACH64_FRGD_SRC_FRGD_CLR (1 << 8) # define MACH64_FRGD_SRC_HOST (2 << 8) # define MACH64_FRGD_SRC_BLIT (3 << 8) # define MACH64_FRGD_SRC_PATTERN (4 << 8) # define MACH64_FRGD_SRC_3D (5 << 8) # define MACH64_MONO_SRC_ONE (0 << 16) # define MACH64_MONO_SRC_PATTERN (1 << 16) # define MACH64_MONO_SRC_HOST (2 << 16) # define MACH64_MONO_SRC_BLIT (3 << 16) #define MACH64_DP_WRITE_MASK 0x06c8 #define MACH64_DST_CNTL 0x0530 # define MACH64_DST_X_RIGHT_TO_LEFT (0 << 0) # define MACH64_DST_X_LEFT_TO_RIGHT (1 << 0) # define MACH64_DST_Y_BOTTOM_TO_TOP (0 << 1) # define MACH64_DST_Y_TOP_TO_BOTTOM (1 << 1) # define MACH64_DST_X_MAJOR (0 << 2) # define MACH64_DST_Y_MAJOR (1 << 2) # define MACH64_DST_X_TILE (1 << 3) # define MACH64_DST_Y_TILE (1 << 4) # define MACH64_DST_LAST_PEL (1 << 5) # define MACH64_DST_POLYGON_ENABLE (1 << 6) # define MACH64_DST_24_ROTATION_ENABLE (1 << 7) #define MACH64_DST_HEIGHT_WIDTH 0x0518 #define MACH64_DST_OFF_PITCH 0x0500 #define MACH64_DST_WIDTH_HEIGHT 0x06ec #define MACH64_DST_X_Y 0x06e8 #define MACH64_DST_Y_X 0x050c #define MACH64_FIFO_STAT 0x0710 # define MACH64_FIFO_SLOT_MASK 0x0000ffff # define MACH64_FIFO_ERR (1 << 31) #define MACH64_GEN_TEST_CNTL 0x04d0 # define MACH64_GUI_ENGINE_ENABLE (1 << 8) #define MACH64_GUI_CMDFIFO_DEBUG 0x0170 #define MACH64_GUI_CMDFIFO_DATA 0x0174 #define MACH64_GUI_CNTL 0x0178 # define MACH64_CMDFIFO_SIZE_MASK 0x00000003ul # define MACH64_CMDFIFO_SIZE_192 0x00000000ul # define MACH64_CMDFIFO_SIZE_128 0x00000001ul # define MACH64_CMDFIFO_SIZE_64 0x00000002ul #define MACH64_GUI_STAT 0x0738 # define MACH64_GUI_ACTIVE (1 << 0) #define MACH64_GUI_TRAJ_CNTL 0x0730 #define MACH64_HOST_CNTL 0x0640 #define MACH64_HOST_DATA0 0x0600 #define MACH64_ONE_OVER_AREA 0x029c #define MACH64_ONE_OVER_AREA_UC 0x0300 #define MACH64_PAT_REG0 0x0680 #define MACH64_PAT_REG1 0x0684 #define MACH64_SC_LEFT 0x06a0 #define MACH64_SC_RIGHT 0x06a4 #define MACH64_SC_LEFT_RIGHT 0x06a8 #define MACH64_SC_TOP 0x06ac #define MACH64_SC_BOTTOM 0x06b0 #define MACH64_SC_TOP_BOTTOM 0x06b4 #define MACH64_SCALE_3D_CNTL 0x05fc #define MACH64_SCRATCH_REG0 0x0480 #define MACH64_SCRATCH_REG1 0x0484 #define MACH64_SECONDARY_TEX_OFF 0x0778 #define MACH64_SETUP_CNTL 0x0304 #define MACH64_SRC_CNTL 0x05b4 # define MACH64_SRC_BM_ENABLE (1 << 8) # define MACH64_SRC_BM_SYNC (1 << 9) # define MACH64_SRC_BM_OP_FRAME_TO_SYSTEM (0 << 10) # define MACH64_SRC_BM_OP_SYSTEM_TO_FRAME (1 << 10) # define MACH64_SRC_BM_OP_REG_TO_SYSTEM (2 << 10) # define MACH64_SRC_BM_OP_SYSTEM_TO_REG (3 << 10) #define MACH64_SRC_HEIGHT1 0x0594 #define MACH64_SRC_HEIGHT2 0x05ac #define MACH64_SRC_HEIGHT1_WIDTH1 0x0598 #define MACH64_SRC_HEIGHT2_WIDTH2 0x05b0 #define MACH64_SRC_OFF_PITCH 0x0580 #define MACH64_SRC_WIDTH1 0x0590 #define MACH64_SRC_Y_X 0x058c #define MACH64_TEX_0_OFF 0x05c0 #define MACH64_TEX_CNTL 0x0774 #define MACH64_TEX_SIZE_PITCH 0x0770 #define MACH64_TIMER_CONFIG 0x0428 #define MACH64_VERTEX_1_ARGB 0x0254 #define MACH64_VERTEX_1_S 0x0240 #define MACH64_VERTEX_1_SECONDARY_S 0x0328 #define MACH64_VERTEX_1_SECONDARY_T 0x032c #define MACH64_VERTEX_1_SECONDARY_W 0x0330 #define MACH64_VERTEX_1_SPEC_ARGB 0x024c #define MACH64_VERTEX_1_T 0x0244 #define MACH64_VERTEX_1_W 0x0248 #define MACH64_VERTEX_1_X_Y 0x0258 #define MACH64_VERTEX_1_Z 0x0250 #define MACH64_VERTEX_2_ARGB 0x0274 #define MACH64_VERTEX_2_S 0x0260 #define MACH64_VERTEX_2_SECONDARY_S 0x0334 #define MACH64_VERTEX_2_SECONDARY_T 0x0338 #define MACH64_VERTEX_2_SECONDARY_W 0x033c #define MACH64_VERTEX_2_SPEC_ARGB 0x026c #define MACH64_VERTEX_2_T 0x0264 #define MACH64_VERTEX_2_W 0x0268 #define MACH64_VERTEX_2_X_Y 0x0278 #define MACH64_VERTEX_2_Z 0x0270 #define MACH64_VERTEX_3_ARGB 0x0294 #define MACH64_VERTEX_3_S 0x0280 #define MACH64_VERTEX_3_SECONDARY_S 0x02a0 #define MACH64_VERTEX_3_SECONDARY_T 0x02a4 #define MACH64_VERTEX_3_SECONDARY_W 0x02a8 #define MACH64_VERTEX_3_SPEC_ARGB 0x028c #define MACH64_VERTEX_3_T 0x0284 #define MACH64_VERTEX_3_W 0x0288 #define MACH64_VERTEX_3_X_Y 0x0298 #define MACH64_VERTEX_3_Z 0x0290 #define MACH64_Z_CNTL 0x054c #define MACH64_Z_OFF_PITCH 0x0548 #define MACH64_CRTC_VLINE_CRNT_VLINE 0x0410 # define MACH64_CRTC_VLINE_MASK 0x000007ff # define MACH64_CRTC_CRNT_VLINE_MASK 0x07ff0000 #define MACH64_CRTC_OFF_PITCH 0x0414 #define MACH64_CRTC_INT_CNTL 0x0418 # define MACH64_CRTC_VBLANK (1 << 0) # define MACH64_CRTC_VBLANK_INT_EN (1 << 1) # define MACH64_CRTC_VBLANK_INT (1 << 2) # define MACH64_CRTC_VLINE_INT_EN (1 << 3) # define MACH64_CRTC_VLINE_INT (1 << 4) # define MACH64_CRTC_VLINE_SYNC (1 << 5) /* 0=even, 1=odd */ # define MACH64_CRTC_FRAME (1 << 6) /* 0=even, 1=odd */ # define MACH64_CRTC_SNAPSHOT_INT_EN (1 << 7) # define MACH64_CRTC_SNAPSHOT_INT (1 << 8) # define MACH64_CRTC_I2C_INT_EN (1 << 9) # define MACH64_CRTC_I2C_INT (1 << 10) # define MACH64_CRTC2_VBLANK (1 << 11) /* LT Pro */ # define MACH64_CRTC2_VBLANK_INT_EN (1 << 12) /* LT Pro */ # define MACH64_CRTC2_VBLANK_INT (1 << 13) /* LT Pro */ # define MACH64_CRTC2_VLINE_INT_EN (1 << 14) /* LT Pro */ # define MACH64_CRTC2_VLINE_INT (1 << 15) /* LT Pro */ # define MACH64_CRTC_CAPBUF0_INT_EN (1 << 16) # define MACH64_CRTC_CAPBUF0_INT (1 << 17) # define MACH64_CRTC_CAPBUF1_INT_EN (1 << 18) # define MACH64_CRTC_CAPBUF1_INT (1 << 19) # define MACH64_CRTC_OVERLAY_EOF_INT_EN (1 << 20) # define MACH64_CRTC_OVERLAY_EOF_INT (1 << 21) # define MACH64_CRTC_ONESHOT_CAP_INT_EN (1 << 22) # define MACH64_CRTC_ONESHOT_CAP_INT (1 << 23) # define MACH64_CRTC_BUSMASTER_EOL_INT_EN (1 << 24) # define MACH64_CRTC_BUSMASTER_EOL_INT (1 << 25) # define MACH64_CRTC_GP_INT_EN (1 << 26) # define MACH64_CRTC_GP_INT (1 << 27) # define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */ # define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */ # define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */ # define MACH64_CRTC_VBLANK2_INT (1 << 31) # define MACH64_CRTC_INT_ENS \ ( \ MACH64_CRTC_VBLANK_INT_EN | \ MACH64_CRTC_VLINE_INT_EN | \ MACH64_CRTC_SNAPSHOT_INT_EN | \ MACH64_CRTC_I2C_INT_EN | \ MACH64_CRTC2_VBLANK_INT_EN | \ MACH64_CRTC2_VLINE_INT_EN | \ MACH64_CRTC_CAPBUF0_INT_EN | \ MACH64_CRTC_CAPBUF1_INT_EN | \ MACH64_CRTC_OVERLAY_EOF_INT_EN | \ MACH64_CRTC_ONESHOT_CAP_INT_EN | \ MACH64_CRTC_BUSMASTER_EOL_INT_EN | \ MACH64_CRTC_GP_INT_EN | \ MACH64_CRTC_SNAPSHOT2_INT_EN | \ 0 \ ) # define MACH64_CRTC_INT_ACKS \ ( \ MACH64_CRTC_VBLANK_INT | \ MACH64_CRTC_VLINE_INT | \ MACH64_CRTC_SNAPSHOT_INT | \ MACH64_CRTC_I2C_INT | \ MACH64_CRTC2_VBLANK_INT | \ MACH64_CRTC2_VLINE_INT | \ MACH64_CRTC_CAPBUF0_INT | \ MACH64_CRTC_CAPBUF1_INT | \ MACH64_CRTC_OVERLAY_EOF_INT | \ MACH64_CRTC_ONESHOT_CAP_INT | \ MACH64_CRTC_BUSMASTER_EOL_INT | \ MACH64_CRTC_GP_INT | \ MACH64_CRTC_SNAPSHOT2_INT | \ MACH64_CRTC_VBLANK2_INT | \ 0 \ ) #define MACH64_DATATYPE_CI8 2 #define MACH64_DATATYPE_ARGB1555 3 #define MACH64_DATATYPE_RGB565 4 #define MACH64_DATATYPE_ARGB8888 6 #define MACH64_DATATYPE_RGB332 7 #define MACH64_DATATYPE_Y8 8 #define MACH64_DATATYPE_RGB8 9 #define MACH64_DATATYPE_VYUY422 11 #define MACH64_DATATYPE_YVYU422 12 #define MACH64_DATATYPE_AYUV444 14 #define MACH64_DATATYPE_ARGB4444 15 #define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) ) #define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) ) #define DWMREG0 0x0400 #define DWMREG0_END 0x07ff #define DWMREG1 0x0000 #define DWMREG1_END 0x03ff #define ISREG0(r) (((r) >= DWMREG0) && ((r) <= DWMREG0_END)) #define DMAREG0(r) (((r) - DWMREG0) >> 2) #define DMAREG1(r) ((((r) - DWMREG1) >> 2 ) | 0x0100) #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) #define MMREG0 0x0000 #define MMREG0_END 0x00ff #define ISMMREG0(r) (((r) >= MMREG0) && ((r) <= MMREG0_END)) #define MMSELECT0(r) (((r) << 2) + DWMREG0) #define MMSELECT1(r) (((((r) & 0xff) << 2) + DWMREG1)) #define MMSELECT(r) (ISMMREG0(r) ? MMSELECT0(r) : MMSELECT1(r)) /* ================================================================ * DMA constants */ /* DMA descriptor field indices: * The descriptor fields are loaded into the read-only * BM_* system bus master registers during a bus-master operation */ #define MACH64_DMA_FRAME_BUF_OFFSET 0 /* BM_FRAME_BUF_OFFSET */ #define MACH64_DMA_SYS_MEM_ADDR 1 /* BM_SYSTEM_MEM_ADDR */ #define MACH64_DMA_COMMAND 2 /* BM_COMMAND */ #define MACH64_DMA_RESERVED 3 /* BM_STATUS */ /* BM_COMMAND descriptor field flags */ #define MACH64_DMA_HOLD_OFFSET (1<<30) /* Don't increment DMA_FRAME_BUF_OFFSET */ #define MACH64_DMA_EOL (1<<31) /* End of descriptor list flag */ #define MACH64_DMA_CHUNKSIZE 0x1000 /* 4kB per DMA descriptor */ #define MACH64_APERTURE_OFFSET 0x7ff800 /* frame-buffer offset for gui-masters */ /* ================================================================ * Misc helper macros */ static __inline__ void mach64_set_dma_eol( volatile u32 * addr ) { #if defined(__i386__) int nr = 31; /* Taken from include/asm-i386/bitops.h linux header */ __asm__ __volatile__( "lock;" "btsl %1,%0" :"=m" (*addr) :"Ir" (nr)); #elif defined(__powerpc__) u32 old; u32 mask = cpu_to_le32( MACH64_DMA_EOL ); /* Taken from the include/asm-ppc/bitops.h linux header */ __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ or %0,%0,%2 \n\ stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (old), "=m" (*addr) : "r" (mask), "r" (addr), "m" (*addr) : "cc"); #elif defined(__alpha__) u32 temp; u32 mask = MACH64_DMA_EOL; /* Taken from the include/asm-alpha/bitops.h linux header */ __asm__ __volatile__( "1: ldl_l %0,%3\n" " bis %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (*addr) :"Ir" (mask), "m" (*addr)); #else u32 mask = cpu_to_le32( MACH64_DMA_EOL ); *addr |= mask; #endif } static __inline__ void mach64_clear_dma_eol( volatile u32 * addr ) { #if defined(__i386__) int nr = 31; /* Taken from include/asm-i386/bitops.h linux header */ __asm__ __volatile__( "lock;" "btrl %1,%0" :"=m" (*addr) :"Ir" (nr)); #elif defined(__powerpc__) u32 old; u32 mask = cpu_to_le32( MACH64_DMA_EOL ); /* Taken from the include/asm-ppc/bitops.h linux header */ __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ andc %0,%0,%2 \n\ stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (old), "=m" (*addr) : "r" (mask), "r" (addr), "m" (*addr) : "cc"); #elif defined(__alpha__) u32 temp; u32 mask = ~MACH64_DMA_EOL; /* Taken from the include/asm-alpha/bitops.h linux header */ __asm__ __volatile__( "1: ldl_l %0,%3\n" " and %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (*addr) :"Ir" (mask), "m" (*addr)); #else u32 mask = cpu_to_le32( ~MACH64_DMA_EOL ); *addr &= mask; #endif } static __inline__ void mach64_ring_start( drm_mach64_private_t *dev_priv ) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", __FUNCTION__, ring->head_addr, ring->head, ring->tail, ring->space ); if ( mach64_do_wait_for_idle( dev_priv ) < 0 ) { mach64_do_engine_reset( dev_priv ); } if (dev_priv->driver_mode != MACH64_MODE_MMIO ) { /* enable bus mastering and block 1 registers */ MACH64_WRITE( MACH64_BUS_CNTL, ( MACH64_READ(MACH64_BUS_CNTL) & ~MACH64_BUS_MASTER_DIS ) | MACH64_BUS_EXT_REG_EN ); mach64_do_wait_for_idle( dev_priv ); } /* reset descriptor table ring head */ MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); dev_priv->ring_running = 1; } static __inline__ void mach64_ring_resume( drm_mach64_private_t *dev_priv, drm_mach64_descriptor_ring_t *ring ) { DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", __FUNCTION__, ring->head_addr, ring->head, ring->tail, ring->space ); /* reset descriptor table ring head */ MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); if ( dev_priv->driver_mode == MACH64_MODE_MMIO ) { mach64_do_dispatch_pseudo_dma( dev_priv ); } else { /* enable GUI bus mastering, and sync the bus master to the GUI */ MACH64_WRITE( MACH64_SRC_CNTL, MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | MACH64_SRC_BM_OP_SYSTEM_TO_REG ); /* kick off the transfer */ MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 ); if ( dev_priv->driver_mode == MACH64_MODE_DMA_SYNC ) { if ( (mach64_do_wait_for_idle( dev_priv )) < 0 ) { DRM_ERROR( "%s: idle failed, resetting engine\n", __FUNCTION__); mach64_dump_engine_info( dev_priv ); mach64_do_engine_reset( dev_priv ); return; } mach64_do_release_used_buffers( dev_priv ); } } } static __inline__ void mach64_ring_tick( drm_mach64_private_t *dev_priv, drm_mach64_descriptor_ring_t *ring ) { DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", __FUNCTION__, ring->head_addr, ring->head, ring->tail, ring->space ); if ( !dev_priv->ring_running ) { mach64_ring_start( dev_priv ); if ( ring->head != ring->tail ) { mach64_ring_resume( dev_priv, ring ); } } else { /* GUI_ACTIVE must be read before BM_GUI_TABLE to * correctly determine the ring head */ int gui_active = MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE; ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0; if ( gui_active ) { /* If not idle, BM_GUI_TABLE points one descriptor * past the current head */ if ( ring->head_addr == ring->start_addr ) { ring->head_addr += ring->size; } ring->head_addr -= 4 * sizeof(u32); } if( ring->head_addr < ring->start_addr || ring->head_addr >= ring->start_addr + ring->size ) { DRM_ERROR( "bad ring head address: 0x%08x\n", ring->head_addr ); mach64_dump_ring_info( dev_priv ); mach64_do_engine_reset( dev_priv ); return; } ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32); if ( !gui_active && ring->head != ring->tail ) { mach64_ring_resume( dev_priv, ring ); } } } static __inline__ void mach64_ring_stop( drm_mach64_private_t *dev_priv ) { DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", __FUNCTION__, dev_priv->ring.head_addr, dev_priv->ring.head, dev_priv->ring.tail, dev_priv->ring.space ); /* restore previous SRC_CNTL to disable busmastering */ mach64_do_wait_for_fifo( dev_priv, 1 ); MACH64_WRITE( MACH64_SRC_CNTL, 0 ); /* disable busmastering but keep the block 1 registers enabled */ mach64_do_wait_for_idle( dev_priv ); MACH64_WRITE( MACH64_BUS_CNTL, MACH64_READ( MACH64_BUS_CNTL ) | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN ); dev_priv->ring_running = 0; } static __inline__ void mach64_update_ring_snapshot( drm_mach64_private_t *dev_priv ) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; DRM_DEBUG( "%s\n", __FUNCTION__ ); mach64_ring_tick( dev_priv, ring ); ring->space = (ring->head - ring->tail) * sizeof(u32); if ( ring->space <= 0 ) { ring->space += ring->size; } } /* ================================================================ * DMA descriptor ring macros */ #define RING_LOCALS \ int _ring_tail, _ring_write; unsigned int _ring_mask; volatile u32 *_ring #define RING_WRITE_OFS _ring_write #define BEGIN_RING( n ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ (n), __FUNCTION__ ); \ } \ if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ int ret; \ if ((ret=mach64_wait_ring( dev_priv, (n) * sizeof(u32))) < 0 ) { \ DRM_ERROR( "wait_ring failed, resetting engine\n"); \ mach64_dump_engine_info( dev_priv ); \ mach64_do_engine_reset( dev_priv ); \ return ret; \ } \ } \ dev_priv->ring.space -= (n) * sizeof(u32); \ _ring = (u32 *) dev_priv->ring.start; \ _ring_tail = _ring_write = dev_priv->ring.tail; \ _ring_mask = dev_priv->ring.tail_mask; \ } while (0) #define OUT_RING( x ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ (unsigned int)(x), _ring_write ); \ } \ _ring[_ring_write++] = cpu_to_le32( x ); \ _ring_write &= _ring_mask; \ } while (0) #define ADVANCE_RING() \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ _ring_write, _ring_tail ); \ } \ DRM_MEMORYBARRIER(); \ mach64_clear_dma_eol( &_ring[(_ring_tail - 2) & _ring_mask] ); \ DRM_MEMORYBARRIER(); \ dev_priv->ring.tail = _ring_write; \ mach64_ring_tick( dev_priv, &(dev_priv)->ring ); \ } while (0) /* ================================================================ * DMA macros */ #define DMALOCALS \ drm_mach64_freelist_t *_entry = NULL; \ drm_buf_t *_buf = NULL; \ u32 *_buf_wptr; int _outcount #define GETBUFPTR( __buf ) \ ((dev_priv->is_pci) ? \ ((u32 *)(__buf)->address) : \ ((u32 *)((char *)dev_priv->dev_buffers->handle + (__buf)->offset))) #define GETBUFADDR( __buf ) ((u32)(__buf)->bus_address) #define GETRINGOFFSET() (_entry->ring_ofs) static __inline__ int mach64_find_pending_buf_entry ( drm_mach64_private_t *dev_priv, drm_mach64_freelist_t **entry, drm_buf_t *buf ) { struct list_head *ptr; #if MACH64_EXTRA_CHECKING if (list_empty(&dev_priv->pending)) { DRM_ERROR("Empty pending list in %s\n", __FUNCTION__); return DRM_ERR(EINVAL); } #endif ptr = dev_priv->pending.prev; *entry = list_entry(ptr, drm_mach64_freelist_t, list); while ((*entry)->buf != buf) { if (ptr == &dev_priv->pending) { return DRM_ERR(EFAULT); } ptr = ptr->prev; *entry = list_entry(ptr, drm_mach64_freelist_t, list); } return 0; } #define DMASETPTR( _p ) \ do { \ _buf = (_p); \ _outcount = 0; \ _buf_wptr = GETBUFPTR( _buf ); \ } while(0) /* FIXME: use a private set of smaller buffers for state emits, clears, and swaps? */ #define DMAGETPTR( filp, dev_priv, n ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "DMAGETPTR( %d ) in %s\n", \ n, __FUNCTION__ ); \ } \ _buf = mach64_freelist_get( dev_priv ); \ if (_buf == NULL) { \ DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n", \ __FUNCTION__ ); \ return DRM_ERR(EAGAIN); \ } \ if (_buf->pending) { \ DRM_ERROR("%s: pending buf in DMAGETPTR\n", \ __FUNCTION__ ); \ return DRM_ERR(EFAULT); \ } \ _buf->filp = filp; \ _outcount = 0; \ \ _buf_wptr = GETBUFPTR( _buf ); \ } while (0) #define DMAOUTREG( reg, val ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( " DMAOUTREG( 0x%x = 0x%08x )\n", \ reg, val ); \ } \ _buf_wptr[_outcount++] = cpu_to_le32(DMAREG(reg)); \ _buf_wptr[_outcount++] = cpu_to_le32((val)); \ _buf->used += 8; \ } while (0) #define DMAADVANCE( dev_priv, _discard ) \ do { \ struct list_head *ptr; \ RING_LOCALS; \ \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "DMAADVANCE() in %s\n", __FUNCTION__ ); \ } \ \ if (_buf->used <= 0) { \ DRM_ERROR( "DMAADVANCE() in %s: sending empty buf %d\n", \ __FUNCTION__, _buf->idx ); \ return DRM_ERR(EFAULT); \ } \ if (_buf->pending) { \ /* This is a resued buffer, so we need to find it in the pending list */ \ int ret; \ if ( (ret=mach64_find_pending_buf_entry(dev_priv, &_entry, _buf)) ) { \ DRM_ERROR( "DMAADVANCE() in %s: couldn't find pending buf %d\n", \ __FUNCTION__, _buf->idx ); \ return ret; \ } \ if (_entry->discard) { \ DRM_ERROR( "DMAADVANCE() in %s: sending discarded pending buf %d\n", \ __FUNCTION__, _buf->idx ); \ return DRM_ERR(EFAULT); \ } \ } else { \ if (list_empty(&dev_priv->placeholders)) { \ DRM_ERROR( "DMAADVANCE() in %s: empty placeholder list\n", \ __FUNCTION__ ); \ return DRM_ERR(EFAULT); \ } \ ptr = dev_priv->placeholders.next; \ list_del(ptr); \ _entry = list_entry(ptr, drm_mach64_freelist_t, list); \ _buf->pending = 1; \ _entry->buf = _buf; \ list_add_tail(ptr, &dev_priv->pending); \ } \ _entry->discard = (_discard); \ ADD_BUF_TO_RING( dev_priv ); \ } while (0) #define DMADISCARDBUF() \ do { \ if (_entry == NULL) { \ int ret; \ if ( (ret=mach64_find_pending_buf_entry(dev_priv, &_entry, _buf)) ) { \ DRM_ERROR( "%s: couldn't find pending buf %d\n", \ __FUNCTION__, _buf->idx ); \ return ret; \ } \ } \ _entry->discard = 1; \ } while(0) #define ADD_BUF_TO_RING( dev_priv ) \ do { \ int bytes, pages, remainder; \ u32 address, page; \ int i; \ \ bytes = _buf->used; \ address = GETBUFADDR( _buf ); \ \ pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; \ \ BEGIN_RING( pages * 4 ); \ \ for ( i = 0 ; i < pages-1 ; i++ ) { \ page = address + i * MACH64_DMA_CHUNKSIZE; \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ OUT_RING( page ); \ OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); \ OUT_RING( 0 ); \ } \ \ /* generate the final descriptor for any remaining commands in this buffer */ \ page = address + i * MACH64_DMA_CHUNKSIZE; \ remainder = bytes - i * MACH64_DMA_CHUNKSIZE; \ \ /* Save dword offset of last descriptor for this buffer. \ * This is needed to check for completion of the buffer in freelist_get \ */ \ _entry->ring_ofs = RING_WRITE_OFS; \ \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ OUT_RING( page ); \ OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); \ OUT_RING( 0 ); \ \ ADVANCE_RING(); \ } while(0) #define DMAADVANCEHOSTDATA( dev_priv ) \ do { \ struct list_head *ptr; \ RING_LOCALS; \ \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "DMAADVANCEHOSTDATA() in %s\n", __FUNCTION__ ); \ } \ \ if (_buf->used <= 0) { \ DRM_ERROR( "DMAADVANCEHOSTDATA() in %s: sending empty buf %d\n", \ __FUNCTION__, _buf->idx ); \ return DRM_ERR(EFAULT); \ } \ if (list_empty(&dev_priv->placeholders)) { \ DRM_ERROR( "%s: empty placeholder list in DMAADVANCEHOSTDATA()\n", \ __FUNCTION__ ); \ return DRM_ERR(EFAULT); \ } \ \ ptr = dev_priv->placeholders.next; \ list_del(ptr); \ _entry = list_entry(ptr, drm_mach64_freelist_t, list); \ _entry->buf = _buf; \ _entry->buf->pending = 1; \ list_add_tail(ptr, &dev_priv->pending); \ _entry->discard = 1; \ ADD_HOSTDATA_BUF_TO_RING( dev_priv ); \ } while (0) #define ADD_HOSTDATA_BUF_TO_RING( dev_priv ) \ do { \ int bytes, pages, remainder; \ u32 address, page; \ int i; \ \ bytes = _buf->used - MACH64_HOSTDATA_BLIT_OFFSET; \ pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; \ address = GETBUFADDR( _buf ); \ \ BEGIN_RING( 4 + pages * 4 ); \ \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ OUT_RING( address ); \ OUT_RING( MACH64_HOSTDATA_BLIT_OFFSET | MACH64_DMA_HOLD_OFFSET ); \ OUT_RING( 0 ); \ \ address += MACH64_HOSTDATA_BLIT_OFFSET; \ \ for ( i = 0 ; i < pages-1 ; i++ ) { \ page = address + i * MACH64_DMA_CHUNKSIZE; \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \ OUT_RING( page ); \ OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); \ OUT_RING( 0 ); \ } \ \ /* generate the final descriptor for any remaining commands in this buffer */ \ page = address + i * MACH64_DMA_CHUNKSIZE; \ remainder = bytes - i * MACH64_DMA_CHUNKSIZE; \ \ /* Save dword offset of last descriptor for this buffer. \ * This is needed to check for completion of the buffer in freelist_get \ */ \ _entry->ring_ofs = RING_WRITE_OFS; \ \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \ OUT_RING( page ); \ OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); \ OUT_RING( 0 ); \ \ ADVANCE_RING(); \ } while(0) #endif /* __MACH64_DRV_H__ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-04 21:10:57 +0000