shared/drm_pciids.txt


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[radeon]
0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP "ATI Radeon RS100 IGP 320M"
0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP "ATI Radeon RS200 IGP"
0x1002 0x4144 CHIP_R300 "ATI Radeon AD 9500 Pro"
0x1002 0x4145 CHIP_R300 "ATI Radeon AE 9700 Pro"
0x1002 0x4146 CHIP_R300 "ATI Radeon AF 9700 Pro"
0x1002 0x4147 CHIP_R300 "ATI FireGL AG Z1/X1"
0x1002 0x4150 CHIP_RV350 "ATI Radeon AP 9600"
0x1002 0x4151 CHIP_RV350 "ATI Radeon AQ 9600"
0x1002 0x4152 CHIP_RV350 "ATI Radeon AR 9600"
0x1002 0x4153 CHIP_RV350 "ATI Radeon AS 9600 AS"
0x1002 0x4154 CHIP_RV350 "ATI FireGL AT T2"
0x1002 0x4156 CHIP_RV350 "ATI FireGL AV T2"
0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP"
0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
0x1002 0x4243 CHIP_R200 "ATI Radeon BC R200"
0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100 Mobility U1"
0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200 Mobility IGP 340M"
0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250 Mobility IGP"
0x1002 0x4964 CHIP_R250 "ATI Radeon Id R250 9000"
0x1002 0x4965 CHIP_R250 "ATI Radeon Ie R250 9000"
0x1002 0x4966 CHIP_R250 "ATI Radeon If R250 9000"
0x1002 0x4967 CHIP_R250 "ATI Radeon Ig R250 9000"
0x1002 0x4C57 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500 M7"
0x1002 0x4C58 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL 7800 M7"
0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6"
0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6"
0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Ld R250 Mobility 9000 M9"
0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Le R250 Mobility 9000 M9"
0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lf R250 Mobility 9000 M9"
0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lg R250 Mobility 9000 M9"
0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY "ATI Radeon RV300 Mobility 9600 M10"
0x1002 0x5144 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QD R100"
0x1002 0x5145 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QE R100"
0x1002 0x5146 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QF R100"
0x1002 0x5147 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QG R100"
0x1002 0x5148 CHIP_R200 "ATI Radeon QH R200 8500"
0x1002 0x5149 CHIP_R200 "ATI Radeon QI R200"
0x1002 0x514A CHIP_R200 "ATI Radeon QJ R200"
0x1002 0x514B CHIP_R200 "ATI Radeon QK R200"
0x1002 0x514C CHIP_R200 "ATI Radeon QL R200 8500 LE"
0x1002 0x514D CHIP_R200 "ATI Radeon QM R200 9100"
0x1002 0x514E CHIP_R200 "ATI Radeon QN R200 8500 LE"
0x1002 0x514F CHIP_R200 "ATI Radeon QO R200 8500 LE"
0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500"
0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500"
0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE"
0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE"
0x1002 0x515E CHIP_RV100 "ATI ES1000 RN50"
0x1002 0x5168 CHIP_R200 "ATI Radeon Qh R200"
0x1002 0x5169 CHIP_R200 "ATI Radeon Qi R200"
0x1002 0x516A CHIP_R200 "ATI Radeon Qj R200"
0x1002 0x516B CHIP_R200 "ATI Radeon Qk R200"
0x1002 0x516C CHIP_R200 "ATI Radeon Ql R200"
0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS300 Mobility IGP"
0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9200"
0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200 SE"
0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
0x1002 0x5963 CHIP_RV280 "ATI Radeon RV280 9200"
0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE"
0x1002 0x5968 CHIP_RV280 "ATI Radeon RV280 9200"
0x1002 0x5969 CHIP_RV100 "ATI ES1000 RN50"
0x1002 0x596A CHIP_RV280 "ATI Radeon RV280 9200"
0x1002 0x596B CHIP_RV280 "ATI Radeon RV280 9200"
0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
0x1002 0x5c62 CHIP_RV280 "ATI Radeon RV280"
0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
0x1002 0x5c64 CHIP_RV280 "ATI Radeon RV280"

[r128]
0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"
0x1002 0x4c46 0 "ATI Rage 128 Mobility LF (AGP)"
0x1002 0x4d46 0 "ATI Rage 128 Mobility MF (AGP)"
0x1002 0x4d4c 0 "ATI Rage 128 Mobility ML (AGP)"
0x1002 0x5041 0 "ATI Rage 128 Pro PA (PCI)"
0x1002 0x5042 0 "ATI Rage 128 Pro PB (AGP)"
0x1002 0x5043 0 "ATI Rage 128 Pro PC (AGP)"
0x1002 0x5044 0 "ATI Rage 128 Pro PD (PCI)"
0x1002 0x5045 0 "ATI Rage 128 Pro PE (AGP)"
0x1002 0x5046 0 "ATI Rage 128 Pro PF (AGP)"
0x1002 0x5047 0 "ATI Rage 128 Pro PG (PCI)"
0x1002 0x5048 0 "ATI Rage 128 Pro PH (AGP)"
0x1002 0x5049 0 "ATI Rage 128 Pro PI (AGP)"
0x1002 0x504A 0 "ATI Rage 128 Pro PJ (PCI)"
0x1002 0x504B 0 "ATI Rage 128 Pro PK (AGP)"
0x1002 0x504C 0 "ATI Rage 128 Pro PL (AGP)"
0x1002 0x504D 0 "ATI Rage 128 Pro PM (PCI)"
0x1002 0x504E 0 "ATI Rage 128 Pro PN (AGP)"
0x1002 0x504F 0 "ATI Rage 128 Pro PO (AGP)"
0x1002 0x5050 0 "ATI Rage 128 Pro PP (PCI)"
0x1002 0x5051 0 "ATI Rage 128 Pro PQ (AGP)"
0x1002 0x5052 0 "ATI Rage 128 Pro PR (PCI)"
0x1002 0x5053 0 "ATI Rage 128 Pro PS (PCI)"
0x1002 0x5054 0 "ATI Rage 128 Pro PT (AGP)"
0x1002 0x5055 0 "ATI Rage 128 Pro PU (AGP)"
0x1002 0x5056 0 "ATI Rage 128 Pro PV (PCI)"
0x1002 0x5057 0 "ATI Rage 128 Pro PW (AGP)"
0x1002 0x5058 0 "ATI Rage 128 Pro PX (AGP)"
0x1002 0x5245 0 "ATI Rage 128 RE (PCI)"
0x1002 0x5246 0 "ATI Rage 128 RF (AGP)"
0x1002 0x5247 0 "ATI Rage 128 RG (AGP)"
0x1002 0x524b 0 "ATI Rage 128 RK (PCI)"
0x1002 0x524c 0 "ATI Rage 128 RL (AGP)"
0x1002 0x534d 0 "ATI Rage 128 SM (AGP)"
0x1002 0x5446 0 "ATI Rage 128 Pro Ultra TF (AGP)"
0x1002 0x544C 0 "ATI Rage 128 Pro Ultra TL (AGP)"
0x1002 0x5452 0 "ATI Rage 128 Pro Ultra TR (AGP)"

[mga]
0x102b 0x0521 0 "Matrox G200 (AGP)"
0x102b 0x0525 0 "Matrox G400/G450 (AGP)"
0x102b 0x2527 0 "Matrox G550 (AGP)"

[mach64]
0x1002 0x4749 0 "3D Rage Pro"
0x1002 0x4750 0 "3D Rage Pro 215GP"
0x1002 0x4751 0 "3D Rage Pro 215GQ"
0x1002 0x4742 0 "3D Rage Pro AGP 1X/2X"
0x1002 0x4744 0 "3D Rage Pro AGP 1X"
0x1002 0x4c49 0 "3D Rage LT Pro"
0x1002 0x4c50 0 "3D Rage LT Pro"
0x1002 0x4c51 0 "3D Rage LT Pro"
0x1002 0x4c42 0 "3D Rage LT Pro AGP-133"
0x1002 0x4c44 0 "3D Rage LT Pro AGP-66"
0x1002 0x474c 0 "Rage XC"
0x1002 0x474f 0 "Rage XL"
0x1002 0x4752 0 "Rage XL"
0x1002 0x4753 0 "Rage XC"
0x1002 0x474d 0 "Rage XL AGP 2X"
0x1002 0x474e 0 "Rage XC AGP"
0x1002 0x4c52 0 "Rage Mobility P/M"
0x1002 0x4c53 0 "Rage Mobility L"
0x1002 0x4c4d 0 "Rage Mobility P/M AGP 2X"
0x1002 0x4c4e 0 "Rage Mobility L AGP 2X"

[sisdrv]
0x1039 0x0300 0 "SiS 300/305"
0x1039 0x5300 0 "SiS 540"
0x1039 0x6300 0 "SiS 630"
0x1039 0x7300 0 "SiS 730"

[tdfx]
0x121a 0x0003 0 "3dfx Voodoo Banshee"
0x121a 0x0004 0 "3dfx Voodoo3 2000"
0x121a 0x0005 0 "3dfx Voodoo3 3000"
0x121a 0x0007 0 "3dfx Voodoo4 4500"
0x121a 0x0009 0 "3dfx Voodoo5 5500"
0x121a 0x000b 0 "3dfx Voodoo4 4200"

[viadrv]
0x1106 0x3022 0 "VIA CLE266 3022"
0x1106 0x3118 0 "VIA CN400 / PM8X0"
0x1106 0x3122 0 "VIA CLE266"
0x1106 0x7205 0 "VIA KM400"
0x1106 0x3108 0 "VIA K8M800"

[i810]
0x8086 0x7121 0 "Intel i810 GMCH"
0x8086 0x7123 0 "Intel i810-DC100 GMCH"
0x8086 0x7125 0 "Intel i810E GMCH"
0x8086 0x1132 0 "Intel i815 GMCH"

[i830]
0x8086 0x3577 0 "Intel i830M GMCH"
0x8086 0x2562 0 "Intel i845G GMCH"
0x8086 0x3582 0 "Intel i852GM/i855GM GMCH"
0x8086 0x2572 0 "Intel i865G GMCH"

[gamma]
0x3d3d 0x0008 0 "3DLabs GLINT Gamma G1"

[savage]
0x5333 0x8a20 S3_SAVAGE3D "Savage 3D"
0x5333 0x8a21 S3_SAVAGE3D "Savage 3D/MV"
0x5333 0x8a22 S3_SAVAGE4 "Savage4"
0x5333 0x8a23 S3_SAVAGE4 "Savage4"
0x5333 0x8c10 S3_SAVAGE_MX "Savage/MX-MV"
0x5333 0x8c11 S3_SAVAGE_MX "Savage/MX"
0x5333 0x8c12 S3_SAVAGE_MX "Savage/IX-MV"
0x5333 0x8c13 S3_SAVAGE_MX "Savage/IX"
0x5333 0x8c22 S3_SUPERSAVAGE "SuperSavage MX/128"
0x5333 0x8c24 S3_SUPERSAVAGE "SuperSavage MX/64"
0x5333 0x8c26 S3_SUPERSAVAGE "SuperSavage MX/64C"
0x5333 0x8c2a S3_SUPERSAVAGE "SuperSavage IX/128 SDR"
0x5333 0x8c2b S3_SUPERSAVAGE "SuperSavage IX/128 DDR"
0x5333 0x8c2c S3_SUPERSAVAGE "SuperSavage IX/64 SDR"
0x5333 0x8c2d S3_SUPERSAVAGE "SuperSavage IX/64 DDR"
0x5333 0x8c2e S3_SUPERSAVAGE "SuperSavage IX/C SDR"
0x5333 0x8c2f S3_SUPERSAVAGE "SuperSavage IX/C DDR"
0x5333 0x8a25 S3_PROSAVAGE "ProSavage PM133"
0x5333 0x8a26 S3_PROSAVAGE "ProSavage KM133"
0x5333 0x8d01 S3_TWISTER "ProSavage Twister PN133"
0x5333 0x8d02 S3_TWISTER "ProSavage Twister KN133"
0x5333 0x8d03 S3_PROSAVAGEDDR "ProSavage DDR"
0x5333 0x8d04 S3_PROSAVAGEDDR "ProSavage DDR-K"

[ffb]

[i915]
0x8086 0x3577 0 "Intel i830M GMCH"
0x8086 0x2562 0 "Intel i845G GMCH"
0x8086 0x3582 0 "Intel i852GM/i855GM GMCH"
0x8086 0x2572 0 "Intel i865G GMCH"
0x8086 0x2582 0 "Intel i915G"
0x8086 0x2592 0 "Intel i915GM"
0x8086 0x2772 0 "Intel i945G"
/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
 */
/* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

/**
 * \file mga_dma.c
 * DMA support for MGA G200 / G400.
 *
 * \author Rickard E. (Rik) Faith <faith@valinux.com>
 * \author Jeff Hartmann <jhartmann@valinux.com>
 * \author Keith Whitwell <keith@tungstengraphics.com>
 * \author Gareth Hughes <gareth@valinux.com>
 */

#include "drmP.h"
#include "drm.h"
#include "drm_sarea.h"
#include "mga_drm.h"
#include "mga_drv.h"

#define MGA_DEFAULT_USEC_TIMEOUT	10000
#define MGA_FREELIST_DEBUG		0

#define MINIMAL_CLEANUP    0
#define FULL_CLEANUP       1
static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);

/* ================================================================
 * Engine control
 */

int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
{
	u32 status = 0;
	int i;
	DRM_DEBUG("\n");

	for (i = 0; i < dev_priv->usec_timeout; i++) {
		status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
		if (status == MGA_ENDPRDMASTS) {
			MGA_WRITE8(MGA_CRTC_INDEX, 0);
			return 0;
		}
		DRM_UDELAY(1);
	}

#if MGA_DMA_DEBUG
	DRM_ERROR("failed!\n");
	DRM_INFO("   status=0x%08x\n", status);
#endif
	return -EBUSY;
}

static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	drm_mga_primary_buffer_t *primary = &dev_priv->prim;

	DRM_DEBUG("\n");

	/* The primary DMA stream should look like new right about now.
	 */
	primary->tail = 0;
	primary->space = primary->size;
	primary->last_flush = 0;

	sarea_priv->last_wrap = 0;

	/* FIXME: Reset counters, buffer ages etc...
	 */

	/* FIXME: What else do we need to reinitialize?  WARP stuff?
	 */

	return 0;
}

/* ================================================================
 * Primary DMA stream
 */

void mga_do_dma_flush(drm_mga_private_t * dev_priv)
{
	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
	u32 head, tail;
	u32 status = 0;
	int i;
	DMA_LOCALS;
	DRM_DEBUG("\n");

	/* We need to wait so that we can do an safe flush */
	for (i = 0; i < dev_priv->usec_timeout; i++) {
		status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
		if (status == MGA_ENDPRDMASTS)
			break;
		DRM_UDELAY(1);
	}

	if (primary->tail == primary->last_flush) {
		DRM_DEBUG("   bailing out...\n");
		return;
	}

	tail = primary->tail + dev_priv->primary->offset;

	/* We need to pad the stream between flushes, as the card
	 * actually (partially?) reads the first of these commands.
	 * See page 4-16 in the G400 manual, middle of the page or so.
	 */
	BEGIN_DMA(1);

	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
		  MGA_DMAPAD, 0x00000000,
		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);

	ADVANCE_DMA();

	primary->last_flush = primary->tail;

	head = MGA_READ(MGA_PRIMADDRESS);

	if (head <= tail) {
		primary->space = primary->size - primary->tail;
	} else {
		primary->space = head - tail;
	}

	DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
	DRM_DEBUG("   tail = 0x%06lx\n", tail - dev_priv->primary->offset);
	DRM_DEBUG("  space = 0x%06x\n", primary->space);

	mga_flush_write_combine();
	MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);

	DRM_DEBUG("done.\n");
}

void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
{
	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
	u32 head, tail;
	DMA_LOCALS;
	DRM_DEBUG("\n");

	BEGIN_DMA_WRAP();

	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
		  MGA_DMAPAD, 0x00000000,
		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);

	ADVANCE_DMA();

	tail = primary->tail + dev_priv->primary->offset;

	primary->tail = 0;
	primary->last_flush = 0;
	primary->last_wrap++;

	head = MGA_READ(MGA_PRIMADDRESS);

	if (head == dev_priv->primary->offset) {
		primary->space = primary->size;
	} else {
		primary->space = head - dev_priv->primary->offset;
	}

	DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
	DRM_DEBUG("   tail = 0x%06x\n", primary->tail);
	DRM_DEBUG("   wrap = %d\n", primary->last_wrap);
	DRM_DEBUG("  space = 0x%06x\n", primary->space);

	mga_flush_write_combine();
	MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);

	set_bit(0, &primary->wrapped);
	DRM_DEBUG("done.\n");
}

void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
{
	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	u32 head = dev_priv->primary->offset;
	DRM_DEBUG("\n");

	sarea_priv->last_wrap++;
	DRM_DEBUG("   wrap = %d\n", sarea_priv->last_wrap);

	mga_flush_write_combine();
	MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);

	clear_bit(0, &primary->wrapped);
	DRM_DEBUG("done.\n");
}

/* ================================================================
 * Freelist management
 */

#define MGA_BUFFER_USED		~0
#define MGA_BUFFER_FREE		0

#if MGA_FREELIST_DEBUG
static void mga_freelist_print(struct drm_device * dev)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	drm_mga_freelist_t *entry;

	DRM_INFO("\n");
	DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
		 dev_priv->sarea_priv->last_dispatch,
		 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
				dev_priv->primary->offset));
	DRM_INFO("current freelist:\n");

	for (entry = dev_priv->head->next; entry; entry = entry->next) {
		DRM_INFO("   %p   idx=%2d  age=0x%x 0x%06lx\n",
			 entry, entry->buf->idx, entry->age.head,
			 entry->age.head - dev_priv->primary->offset);
	}
	DRM_INFO("\n");
}
#endif

static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv)
{
	struct drm_device_dma *dma = dev->dma;
	struct drm_buf *buf;
	drm_mga_buf_priv_t *buf_priv;
	drm_mga_freelist_t *entry;
	int i;
	DRM_DEBUG("count=%d\n", dma->buf_count);

	dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
	if (dev_priv->head == NULL)
		return -ENOMEM;

	memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
	SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);

	for (i = 0; i < dma->buf_count; i++) {
		buf = dma->buflist[i];
		buf_priv = buf->dev_private;

		entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
		if (entry == NULL)
			return -ENOMEM;

		memset(entry, 0, sizeof(drm_mga_freelist_t));

		entry->next = dev_priv->head->next;
		entry->prev = dev_priv->head;
		SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
		entry->buf = buf;

		if (dev_priv->head->next != NULL)
			dev_priv->head->next->prev = entry;
		if (entry->next == NULL)
			dev_priv->tail = entry;

		buf_priv->list_entry = entry;
		buf_priv->discard = 0;
		buf_priv->dispatched = 0;

		dev_priv->head->next = entry;
	}

	return 0;
}

static void mga_freelist_cleanup(struct drm_device * dev)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	drm_mga_freelist_t *entry;
	drm_mga_freelist_t *next;
	DRM_DEBUG("\n");

	entry = dev_priv->head;
	while (entry) {
		next = entry->next;
		drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
		entry = next;
	}

	dev_priv->head = dev_priv->tail = NULL;
}

#if 0
/* FIXME: Still needed?
 */
static void mga_freelist_reset(struct drm_device * dev)
{
	drm_device_dma_t *dma = dev->dma;
	struct drm_buf *buf;
	drm_mga_buf_priv_t *buf_priv;
	int i;

	for (i = 0; i < dma->buf_count; i++) {
		buf = dma->buflist[i];
		buf_priv = buf->dev_private;
		SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
	}
}
#endif

static struct drm_buf *mga_freelist_get(struct drm_device * dev)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	drm_mga_freelist_t *next;
	drm_mga_freelist_t *prev;
	drm_mga_freelist_t *tail = dev_priv->tail;
	u32 head, wrap;
	DRM_DEBUG("\n");

	head = MGA_READ(MGA_PRIMADDRESS);
	wrap = dev_priv->sarea_priv->last_wrap;

	DRM_DEBUG("   tail=0x%06lx %d\n",
		  tail->age.head ?
		  tail->age.head - dev_priv->primary->offset : 0,
		  tail->age.wrap);
	DRM_DEBUG("   head=0x%06lx %d\n",
		  head - dev_priv->primary->offset, wrap);

	if (TEST_AGE(&tail->age, head, wrap)) {
		prev = dev_priv->tail->prev;
		next = dev_priv->tail;
		prev->next = NULL;
		next->prev = next->next = NULL;
		dev_priv->tail = prev;
		SET_AGE(&next->age, MGA_BUFFER_USED, 0);
		return next->buf;
	}

	DRM_DEBUG("returning NULL!\n");
	return NULL;
}

int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
	drm_mga_freelist_t *head, *entry, *prev;

	DRM_DEBUG("age=0x%06lx wrap=%d\n",
		  buf_priv->list_entry->age.head -
		  dev_priv->primary->offset, buf_priv->list_entry->age.wrap);

	entry = buf_priv->list_entry;
	head = dev_priv->head;

	if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
		SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
		prev = dev_priv->tail;
		prev->next = entry;
		entry->prev = prev;