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-rw-r--r--Makefile.am1884logplain
-rw-r--r--drm.h34759logplain
-rw-r--r--drm_internal.h1528logplain
-rw-r--r--drm_pciids.txt30342logplain
-rw-r--r--drm_sarea.h2654logplain
-rw-r--r--i915_dma.c33196logplain
-rw-r--r--i915_drm.h21785logplain
-rw-r--r--i915_drv.h69583logplain
-rw-r--r--i915_irq.c23912logplain
-rw-r--r--i915_mem.c9637logplain
-rw-r--r--i915_suspend.c16302logplain
-rw-r--r--imagine_drv.h1616logplain
-rw-r--r--mach64_dma.c49792logplain
-rw-r--r--mach64_drm.h7895logplain
-rw-r--r--mach64_drv.h30349logplain
-rw-r--r--mach64_irq.c4728logplain
-rw-r--r--mach64_state.c25466logplain
-rw-r--r--mga_dma.c29690logplain
-rw-r--r--mga_drm.h12950logplain
-rw-r--r--mga_drv.h20038logplain
-rw-r--r--mga_irq.c5052logplain
-rw-r--r--mga_state.c29375logplain
-rw-r--r--mga_ucode.h181349logplain
-rw-r--r--mga_warp.c6652logplain
-rw-r--r--nouveau_dma.c5297logplain
-rw-r--r--nouveau_dma.h4992logplain
-rw-r--r--nouveau_drm.h5065logplain
-rw-r--r--nouveau_drv.h20942logplain
-rw-r--r--nouveau_fifo.c17873logplain
-rw-r--r--nouveau_irq.c15465logplain
-rw-r--r--nouveau_mem.c23126logplain
-rw-r--r--nouveau_notifier.c4608logplain
-rw-r--r--nouveau_object.c30639logplain
-rw-r--r--nouveau_reg.h39475logplain
-rw-r--r--nouveau_state.c21738logplain
-rw-r--r--nouveau_swmthd.c6205logplain
-rw-r--r--nouveau_swmthd.h1422logplain
-rw-r--r--nv04_fb.c466logplain
-rw-r--r--nv04_fifo.c4462logplain
-rw-r--r--nv04_graph.c12080logplain
-rw-r--r--nv04_instmem.c4208logplain
-rw-r--r--nv04_mc.c388logplain
-rw-r--r--nv04_timer.c1546logplain
-rw-r--r--nv10_fb.c455logplain
-rw-r--r--nv10_fifo.c5694logplain
-rw-r--r--nv10_graph.c23211logplain
-rw-r--r--nv20_graph.c33558logplain
-rw-r--r--nv40_fb.c1465logplain
-rw-r--r--nv40_fifo.c7424logplain
-rw-r--r--nv40_graph.c90759logplain
-rw-r--r--nv40_mc.c693logplain
-rw-r--r--nv50_fifo.c8924logplain
-rw-r--r--nv50_graph.c85822logplain
-rw-r--r--nv50_instmem.c10582logplain
-rw-r--r--nv50_mc.c1460logplain
-rw-r--r--nv_drv.h1720logplain
-rw-r--r--r128_cce.c25775logplain
-rw-r--r--r128_drm.h9943logplain
-rw-r--r--r128_drv.h16974logplain
-rw-r--r--r128_irq.c3550logplain
-rw-r--r--r128_state.c42360logplain
-rw-r--r--r300_cmdbuf.c31588logplain
-rw-r--r--r300_reg.h79309logplain
-rw-r--r--r600_microcode.h455847logplain
-rw-r--r--radeon_cp.c51116logplain
-rw-r--r--radeon_drm.h27502logplain
-rw-r--r--radeon_drv.h52973logplain
-rw-r--r--radeon_irq.c10240logplain
-rw-r--r--radeon_mem.c7571logplain
-rw-r--r--radeon_microcode.h58992logplain
-rw-r--r--radeon_state.c93170logplain
-rw-r--r--savage_bci.c31278logplain
-rw-r--r--savage_drm.h7071logplain
-rw-r--r--savage_drv.h19697logplain
-rw-r--r--savage_state.c30988logplain
-rw-r--r--sis_drm.h2534logplain
-rw-r--r--sis_drv.h2760logplain
-rw-r--r--sis_ds.c7032logplain
-rw-r--r--sis_ds.h4596logplain
-rw-r--r--sis_mm.c9772logplain
-rw-r--r--tdfx_drv.h1700logplain
-rw-r--r--via_3d_reg.h68052logplain
-rw-r--r--via_dma.c20657logplain
-rw-r--r--via_drm.h8392logplain
-rw-r--r--via_drv.c4701logplain
-rw-r--r--via_drv.h7434logplain
-rw-r--r--via_ds.c5663logplain
-rw-r--r--via_ds.h2825logplain
-rw-r--r--via_irq.c11335logplain
-rw-r--r--via_map.c3763logplain
-rw-r--r--via_mm.c7759logplain
-rw-r--r--via_mm.h1522logplain
-rw-r--r--via_verifier.c28316logplain
-rw-r--r--via_verifier.h2094logplain
-rw-r--r--via_video.c2747logplain
-rw-r--r--xgi_drm.h3732logplain
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-28 04:09:13 +0000
pan class="hl opt">((p->file_priv == 0) && (p->next->file_priv == 0) && (p->next!=heap)) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; p->next->prev = p; drm_free(q, sizeof(*q), DRM_MEM_DRIVER); } } } /* * Cleanup everything */ void nouveau_mem_takedown(struct mem_block **heap) { struct mem_block *p; if (!*heap) return; for (p = (*heap)->next; p != *heap;) { struct mem_block *q = p; p = p->next; drm_free(q, sizeof(*q), DRM_MEM_DRIVER); } drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER); *heap = NULL; } void nouveau_mem_close(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; nouveau_mem_takedown(&dev_priv->agp_heap); nouveau_mem_takedown(&dev_priv->fb_heap); if (dev_priv->pci_heap) nouveau_mem_takedown(&dev_priv->pci_heap); } /*XXX won't work on BSD because of pci_read_config_dword */ static uint32_t nouveau_mem_fb_amount_igp(struct drm_device *dev) { #if defined(__linux__) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) struct drm_nouveau_private *dev_priv = dev->dev_private; struct pci_dev *bridge; uint32_t mem; bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0,1)); if (!bridge) { DRM_ERROR("no bridge device\n"); return 0; } if (dev_priv->flags&NV_NFORCE) { pci_read_config_dword(bridge, 0x7C, &mem); return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; } else if(dev_priv->flags&NV_NFORCE2) { pci_read_config_dword(bridge, 0x84, &mem); return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; } DRM_ERROR("impossible!\n"); #else DRM_ERROR("Linux kernel >= 2.6.19 required to check for igp memory amount\n"); #endif return 0; } /* returns the amount of FB ram in bytes */ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) { struct drm_nouveau_private *dev_priv=dev->dev_private; switch(dev_priv->card_type) { case NV_04: case NV_05: if (NV_READ(NV03_BOOT_0) & 0x00000100) { return (((NV_READ(NV03_BOOT_0) >> 12) & 0xf)*2+2)*1024*1024; } else switch(NV_READ(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT) { case NV04_BOOT_0_RAM_AMOUNT_32MB: return 32*1024*1024; case NV04_BOOT_0_RAM_AMOUNT_16MB: return 16*1024*1024; case NV04_BOOT_0_RAM_AMOUNT_8MB: return 8*1024*1024; case NV04_BOOT_0_RAM_AMOUNT_4MB: return 4*1024*1024; } break; case NV_10: case NV_11: case NV_17: case NV_20: case NV_30: case NV_40: case NV_44: case NV_50: default: if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { return nouveau_mem_fb_amount_igp(dev); } else { uint64_t mem; mem = (NV_READ(NV04_FIFO_DATA) & NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >> NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT; return mem*1024*1024; } break; } DRM_ERROR("Unable to detect video ram size. Please report your setup to " DRIVER_EMAIL "\n"); return 0; } static void nouveau_mem_reset_agp(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable; saved_pci_nv_1 = NV_READ(NV04_PBUS_PCI_NV_1); saved_pci_nv_19 = NV_READ(NV04_PBUS_PCI_NV_19); /* clear busmaster bit */ NV_WRITE(NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4); /* clear SBA and AGP bits */ NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff); /* power cycle pgraph, if enabled */ pmc_enable = NV_READ(NV03_PMC_ENABLE); if (pmc_enable & NV_PMC_ENABLE_PGRAPH) { NV_WRITE(NV03_PMC_ENABLE, pmc_enable & ~NV_PMC_ENABLE_PGRAPH); NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); } /* and restore (gives effect of resetting AGP) */ NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19); NV_WRITE(NV04_PBUS_PCI_NV_1, saved_pci_nv_1); } static int nouveau_mem_init_agp(struct drm_device *dev, int ttm) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_agp_info info; struct drm_agp_mode mode; int ret; nouveau_mem_reset_agp(dev); ret = drm_agp_acquire(dev); if (ret) { DRM_ERROR("Unable to acquire AGP: %d\n", ret); return ret; } ret = drm_agp_info(dev, &info); if (ret) { DRM_ERROR("Unable to get AGP info: %d\n", ret); return ret; } /* see agp.h for the AGPSTAT_* modes available */ mode.mode = info.mode; ret = drm_agp_enable(dev, mode); if (ret) { DRM_ERROR("Unable to enable AGP: %d\n", ret); return ret; } if (!ttm) { struct drm_agp_buffer agp_req; struct drm_agp_binding bind_req; agp_req.size = info.aperture_size; agp_req.type = 0; ret = drm_agp_alloc(dev, &agp_req); if (ret) { DRM_ERROR("Unable to alloc AGP: %d\n", ret); return ret; } bind_req.handle = agp_req.handle; bind_req.offset = 0; ret = drm_agp_bind(dev, &bind_req); if (ret) { DRM_ERROR("Unable to bind AGP: %d\n", ret); return ret; } } dev_priv->gart_info.type = NOUVEAU_GART_AGP; dev_priv->gart_info.aper_base = info.aperture_base; dev_priv->gart_info.aper_size = info.aperture_size; return 0; } #define HACK_OLD_MM int nouveau_mem_init_ttm(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t vram_size, bar1_size; int ret; dev_priv->agp_heap = dev_priv->pci_heap = dev_priv->fb_heap = NULL; dev_priv->fb_phys = drm_get_resource_start(dev,1); dev_priv->gart_info.type = NOUVEAU_GART_NONE; drm_bo_driver_init(dev); /* non-mappable vram */ dev_priv->fb_available_size = nouveau_mem_fb_amount(dev); dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; vram_size = dev_priv->fb_available_size >> PAGE_SHIFT; bar1_size = drm_get_resource_len(dev, 1) >> PAGE_SHIFT; if (bar1_size < vram_size) { if ((ret = drm_bo_init_mm(dev, DRM_BO_MEM_PRIV0, bar1_size, vram_size - bar1_size, 1))) { DRM_ERROR("Failed PRIV0 mm init: %d\n", ret); return ret; } vram_size = bar1_size; } /* mappable vram */ #ifdef HACK_OLD_MM vram_size /= 4; #endif if ((ret = drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, vram_size, 1))) { DRM_ERROR("Failed VRAM mm init: %d\n", ret); return ret; } /* GART */ #if !defined(__powerpc__) && !defined(__ia64__) if (drm_device_is_agp(dev) && dev->agp) { if ((ret = nouveau_mem_init_agp(dev, 1))) DRM_ERROR("Error initialising AGP: %d\n", ret); } #endif if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { if ((ret = nouveau_sgdma_init(dev))) DRM_ERROR("Error initialising PCI SGDMA: %d\n", ret); } if ((ret = drm_bo_init_mm(dev, DRM_BO_MEM_TT, 0, dev_priv->gart_info.aper_size >> PAGE_SHIFT, 1))) { DRM_ERROR("Failed TT mm init: %d\n", ret); return ret; } #ifdef HACK_OLD_MM vram_size <<= PAGE_SHIFT;