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-rw-r--r--Makefile.am1884logplain
-rw-r--r--drm.h34176logplain
-rw-r--r--drm_internal.h1528logplain
-rw-r--r--drm_pciids.txt30221logplain
-rw-r--r--drm_sarea.h2654logplain
-rw-r--r--i915_dma.c29054logplain
-rw-r--r--i915_drm.h12278logplain
-rw-r--r--i915_drv.h40155logplain
-rw-r--r--i915_irq.c24524logplain
-rw-r--r--i915_mem.c9637logplain
-rw-r--r--imagine_drv.h1616logplain
-rw-r--r--mach64_dma.c49792logplain
-rw-r--r--mach64_drm.h7895logplain
-rw-r--r--mach64_drv.h30349logplain
-rw-r--r--mach64_irq.c4728logplain
-rw-r--r--mach64_state.c25466logplain
-rw-r--r--mga_dma.c29690logplain
-rw-r--r--mga_drm.h12950logplain
-rw-r--r--mga_drv.h20038logplain
-rw-r--r--mga_irq.c5052logplain
-rw-r--r--mga_state.c29375logplain
-rw-r--r--mga_ucode.h181349logplain
-rw-r--r--mga_warp.c6652logplain
-rw-r--r--nouveau_dma.c5297logplain
-rw-r--r--nouveau_dma.h4992logplain
-rw-r--r--nouveau_drm.h4763logplain
-rw-r--r--nouveau_drv.h20837logplain
-rw-r--r--nouveau_fifo.c17801logplain
-rw-r--r--nouveau_irq.c14421logplain
-rw-r--r--nouveau_mem.c21042logplain
-rw-r--r--nouveau_notifier.c4605logplain
-rw-r--r--nouveau_object.c30613logplain
-rw-r--r--nouveau_reg.h39475logplain
-rw-r--r--nouveau_state.c21722logplain
-rw-r--r--nouveau_swmthd.c6205logplain
-rw-r--r--nouveau_swmthd.h1422logplain
-rw-r--r--nv04_fb.c466logplain
-rw-r--r--nv04_fifo.c4462logplain
-rw-r--r--nv04_graph.c12080logplain
-rw-r--r--nv04_instmem.c4208logplain
-rw-r--r--nv04_mc.c388logplain
-rw-r--r--nv04_timer.c1546logplain
-rw-r--r--nv10_fb.c455logplain
-rw-r--r--nv10_fifo.c5694logplain
-rw-r--r--nv10_graph.c23211logplain
-rw-r--r--nv20_graph.c33558logplain
-rw-r--r--nv40_fb.c1465logplain
-rw-r--r--nv40_fifo.c7424logplain
-rw-r--r--nv40_graph.c90759logplain
-rw-r--r--nv40_mc.c693logplain
-rw-r--r--nv50_fifo.c8761logplain
-rw-r--r--nv50_graph.c38782logplain
-rw-r--r--nv50_instmem.c10582logplain
-rw-r--r--nv50_mc.c1460logplain
-rw-r--r--nv_drv.h1720logplain
-rw-r--r--r128_cce.c25775logplain
-rw-r--r--r128_drm.h9943logplain
-rw-r--r--r128_drv.h16974logplain
-rw-r--r--r128_irq.c3550logplain
-rw-r--r--r128_state.c42360logplain
-rw-r--r--r300_cmdbuf.c27916logplain
-rw-r--r--r300_reg.h73399logplain
-rw-r--r--radeon_cp.c561048logplain
-rw-r--r--radeon_drm.h27435logplain
-rw-r--r--radeon_drv.h48339logplain
-rw-r--r--radeon_irq.c8128logplain
-rw-r--r--radeon_mem.c7556logplain
-rw-r--r--radeon_state.c92878logplain
-rw-r--r--savage_bci.c31278logplain
-rw-r--r--savage_drm.h7071logplain
-rw-r--r--savage_drv.h19697logplain
-rw-r--r--savage_state.c30988logplain
-rw-r--r--sis_drm.h2534logplain
-rw-r--r--sis_drv.h2760logplain
-rw-r--r--sis_ds.c7032logplain
-rw-r--r--sis_ds.h4596logplain
-rw-r--r--sis_mm.c9772logplain
-rw-r--r--tdfx_drv.h1700logplain
-rw-r--r--via_3d_reg.h68052logplain
-rw-r--r--via_dma.c20657logplain
-rw-r--r--via_drm.h8392logplain
-rw-r--r--via_drv.c4701logplain
-rw-r--r--via_drv.h7434logplain
-rw-r--r--via_ds.c5663logplain
-rw-r--r--via_ds.h2825logplain
-rw-r--r--via_irq.c11335logplain
-rw-r--r--via_map.c3763logplain
-rw-r--r--via_mm.c7759logplain
-rw-r--r--via_mm.h1522logplain
-rw-r--r--via_verifier.c28316logplain
-rw-r--r--via_verifier.h2094logplain
-rw-r--r--via_video.c2747logplain
-rw-r--r--xgi_drm.h3479logplain
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-27 18:38:22 +0000
tureRegionPtr; typedef enum { DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ DRM_VBLANK_SIGNAL = 0x40000000 /* Send signal instead of blocking */ } drmVBlankSeqType; typedef struct _drmVBlankReq { drmVBlankSeqType type; unsigned int sequence; unsigned long signal; } drmVBlankReq, *drmVBlankReqPtr; typedef struct _drmVBlankReply { drmVBlankSeqType type; unsigned int sequence; long tval_sec; long tval_usec; } drmVBlankReply, *drmVBlankReplyPtr; typedef union _drmVBlank { drmVBlankReq request; drmVBlankReply reply; } drmVBlank, *drmVBlankPtr; typedef struct _drmSetVersion { int drm_di_major; int drm_di_minor; int drm_dd_major; int drm_dd_minor; } drmSetVersion, *drmSetVersionPtr; #define __drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock) #define DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ #define DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ #if defined(__GNUC__) && (__GNUC__ >= 2) # if defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__) /* Reflect changes here to drmP.h */ #define DRM_CAS(lock,old,new,__ret) \ do { \ int __dummy; /* Can't mark eax as clobbered */ \ __asm__ __volatile__( \ "lock ; cmpxchg %4,%1\n\t" \ "setnz %0" \ : "=d" (__ret), \ "=m" (__drm_dummy_lock(lock)), \ "=a" (__dummy) \ : "2" (old), \ "r" (new)); \ } while (0) #elif defined(__alpha__) #define DRM_CAS(lock, old, new, ret) \ do { \ int old32; \ int cur32; \ __asm__ __volatile__( \ " mb\n" \ " zap %4, 0xF0, %0\n" \ " ldl_l %1, %2\n" \ " zap %1, 0xF0, %1\n" \ " cmpeq %0, %1, %1\n" \ " beq %1, 1f\n" \ " bis %5, %5, %1\n" \ " stl_c %1, %2\n" \ "1: xor %1, 1, %1\n" \ " stl %1, %3" \ : "=r" (old32), \ "=&r" (cur32), \ "=m" (__drm_dummy_lock(lock)),\ "=m" (ret) \ : "r" (old), \ "r" (new)); \ } while(0) #elif defined(__sparc__) #define DRM_CAS(lock,old,new,__ret) \ do { register unsigned int __old __asm("o0"); \ register unsigned int __new __asm("o1"); \ register volatile unsigned int *__lock __asm("o2"); \ __old = old; \ __new = new; \ __lock = (volatile unsigned int *)lock; \ __asm__ __volatile__( \ /*"cas [%2], %3, %0"*/ \ ".word 0xd3e29008\n\t" \ /*"membar #StoreStore | #StoreLoad"*/ \ ".word 0x8143e00a" \ : "=&r" (__new) \ : "0" (__new), \ "r" (__lock), \ "r" (__old) \ : "memory"); \ __ret = (__new != __old); \ } while(0) #elif defined(__ia64__) #ifdef __INTEL_COMPILER /* this currently generates bad code (missing stop bits)... */ #include <ia64intrin.h> #define DRM_CAS(lock,old,new,__ret) \ do { \ unsigned long __result, __old = (old) & 0xffffffff; \ __mf(); \ __result = _InterlockedCompareExchange_acq(&__drm_dummy_lock(lock), (new), __old);\ __ret = (__result) != (__old); \ /* __ret = (__sync_val_compare_and_swap(&__drm_dummy_lock(lock), \ (old), (new)) \ != (old)); */\ } while (0) #else #define DRM_CAS(lock,old,new,__ret) \ do { \ unsigned int __result, __old = (old); \ __asm__ __volatile__( \ "mf\n" \ "mov ar.ccv=%2\n" \ ";;\n" \ "cmpxchg4.acq %0=%1,%3,ar.ccv" \ : "=r" (__result), "=m" (__drm_dummy_lock(lock)) \ : "r" ((unsigned long)__old), "r" (new) \ : "memory"); \ __ret = (__result) != (__old); \ } while (0) #endif #elif defined(__powerpc__) #define DRM_CAS(lock,old,new,__ret) \ do { \ __asm__ __volatile__( \ "sync;" \ "0: lwarx %0,0,%1;" \ " xor. %0,%3,%0;" \ " bne 1f;" \ " stwcx. %2,0,%1;" \ " bne- 0b;" \ "1: " \ "sync;" \ : "=&r"(__ret) \ : "r"(lock), "r"(new), "r"(old) \ : "cr0", "memory"); \ } while (0) #endif /* architecture */ #endif /* __GNUC__ >= 2 */ #ifndef DRM_CAS #define DRM_CAS(lock,old,new,ret) do { ret=1; } while (0) /* FAST LOCK FAILS */ #endif #if defined(__alpha__) || defined(__powerpc__) #define DRM_CAS_RESULT(_result) int _result #else #define DRM_CAS_RESULT(_result) char _result #endif #define DRM_LIGHT_LOCK(fd,lock,context) \ do { \ DRM_CAS_RESULT(__ret); \ DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ if (__ret) drmGetLock(fd,context,0); \ } while(0) /* This one counts fast locks -- for benchmarking only. */ #define DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) \ do { \ DRM_CAS_RESULT(__ret); \ DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ if (__ret) drmGetLock(fd,context,0); \ else ++count; \ } while(0) #define DRM_LOCK(fd,lock,context,flags) \ do { \ if (flags) drmGetLock(fd,context,flags); \ else DRM_LIGHT_LOCK(fd,lock,context); \ } while(0) #define DRM_UNLOCK(fd,lock,context) \ do { \ DRM_CAS_RESULT(__ret); \ DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); \ if (__ret) drmUnlock(fd,context); \ } while(0) /* Simple spin locks */ #define DRM_SPINLOCK(spin,val) \ do { \ DRM_CAS_RESULT(__ret); \ do { \ DRM_CAS(spin,0,val,__ret); \ if (__ret) while ((spin)->lock); \ } while (__ret); \ } while(0) #define DRM_SPINLOCK_TAKE(spin,val) \ do { \ DRM_CAS_RESULT(__ret); \ int cur; \ do { \ cur = (*spin).lock; \ DRM_CAS(spin,cur,val,__ret); \ } while (__ret); \ } while(0) #define DRM_SPINLOCK_COUNT(spin,val,count,__ret) \ do { \ int __i; \ __ret = 1; \ for (__i = 0; __ret && __i < count; __i++) { \ DRM_CAS(spin,0,val,__ret); \ if (__ret) for (;__i < count && (spin)->lock; __i++); \ } \ } while(0) #define DRM_SPINUNLOCK(spin,val) \ do { \ DRM_CAS_RESULT(__ret); \ if ((*spin).lock == val) { /* else server stole lock */ \ do { \ DRM_CAS(spin,val,0,__ret); \ } while (__ret); \ } \ } while(0) /* General user-level programmer's API: unprivileged */ extern int drmAvailable(void); extern int drmOpen(const char *name, const char *busid); extern int drmClose(int fd); extern drmVersionPtr drmGetVersion(int fd); extern drmVersionPtr drmGetLibVersion(int fd); extern void drmFreeVersion(drmVersionPtr); extern int drmGetMagic(int fd, drm_magic_t * magic); extern char *drmGetBusid(int fd); extern int drmGetInterruptFromBusID(int fd, int busnum, int devnum, int funcnum); extern int drmGetMap(int fd, int idx, drm_handle_t *offset, drmSize *size, drmMapType *type, drmMapFlags *flags, drm_handle_t *handle, int *mtrr); extern int drmGetClient(int fd, int idx, int *auth, int *pid, int *uid, unsigned long *magic, unsigned long *iocs); extern int drmGetStats(int fd, drmStatsT *stats); extern int drmSetInterfaceVersion(int fd, drmSetVersion *version); extern int drmCommandNone(int fd, unsigned long drmCommandIndex); extern int drmCommandRead(int fd, unsigned long drmCommandIndex, void *data, unsigned long size); extern int drmCommandWrite(int fd, unsigned long drmCommandIndex, void *data, unsigned long size); extern int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, void *data, unsigned long size); /* General user-level programmer's API: X server (root) only */ extern void drmFreeBusid(const char *busid); extern int drmSetBusid(int fd, const char *busid); extern int drmAuthMagic(int fd, drm_magic_t magic); extern int drmAddMap(int fd, drm_handle_t offset, drmSize size, drmMapType type, drmMapFlags flags, drm_handle_t * handle); extern int drmRmMap(int fd, drm_handle_t handle); extern int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id, drm_handle_t handle); extern int drmAddBufs(int fd, int count, int size, drmBufDescFlags flags, int agp_offset); extern int drmMarkBufs(int fd, double low, double high); extern int drmCreateContext(int fd, drm_context_t * handle); extern int drmSetContextFlags(int fd, drm_context_t context, drm_context_tFlags flags); extern int drmGetContextFlags(int fd, drm_context_t context, drm_context_tFlagsPtr flags);