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/*
 * Copyright 2005 Thomas Hellstrom. All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHOR(S), AND/OR THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Author: Thomas Hellstrom 2005.
 *
 * Video and XvMC related functions.
 */

#include "drmP.h"
#include "via_drm.h"
#include "via_drv.h"

void via_init_futex(drm_via_private_t * dev_priv)
{
	unsigned int i;

	DRM_DEBUG("%s\n", __FUNCTION__);

	for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) {
		DRM_INIT_WAITQUEUE(&(dev_priv->decoder_queue[i]));
		XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0;
	}
}

void via_cleanup_futex(drm_via_private_t * dev_priv)
{
}

void via_release_futex(drm_via_private_t * dev_priv, int context)
{
	unsigned int i;
	volatile int *lock;

	if (!dev_priv->sarea_priv)
		return;

	for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) {
		lock = (volatile int *)XVMCLOCKPTR(dev_priv->sarea_priv, i);
		if ((_DRM_LOCKING_CONTEXT(*lock) == context)) {
			if (_DRM_LOCK_IS_HELD(*lock)
			    && (*lock & _DRM_LOCK_CONT)) {
				DRM_WAKEUP(&(dev_priv->decoder_queue[i]));
			}
			*lock = 0;
		}
	}
}

int via_decoder_futex(DRM_IOCTL_ARGS)
{
	DRM_DEVICE;
	drm_via_futex_t fx;
	volatile int *lock;
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	drm_via_sarea_t *sAPriv = dev_priv->sarea_priv;
	int ret = 0;

	DRM_DEBUG("%s\n", __FUNCTION__);

	DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t __user *) data,
				 sizeof(fx));

	if (fx.lock > VIA_NR_XVMC_LOCKS)
		return -EFAULT;

	lock = (volatile int *)XVMCLOCKPTR(sAPriv, fx.lock);

	switch (fx.func) {
	case VIA_FUTEX_WAIT:
		DRM_WAIT_ON(ret, dev_priv->decoder_queue[fx.lock],
			    (fx.ms / 10) * (DRM_HZ / 100), *lock != fx.val);
		return ret;
	case VIA_FUTEX_WAKE:
		DRM_WAKEUP(&(dev_priv->decoder_queue[fx.lock]));
		return 0;
	}
	return 0;
}
OUT OF OR IN CONNECTION * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include "drmP.h" #include "drm.h" #include "nouveau_drv.h" typedef struct { struct nouveau_gpuobj_ref *thingo; } nv50_fifo_priv; #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) static void nv50_fifo_init_thingo(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; struct nouveau_gpuobj_ref *thingo = priv->thingo; int i, fi=2; DRM_DEBUG("\n"); INSTANCE_WR(thingo->gpuobj, 0, 0x7e); INSTANCE_WR(thingo->gpuobj, 1, 0x7e); for (i = 1; i < 127; i++, fi) { if (dev_priv->fifos[i]) { INSTANCE_WR(thingo->gpuobj, fi, i); fi++; } } NV_WRITE(0x32f4, thingo->instance >> 12); NV_WRITE(0x32ec, fi); NV_WRITE(0x2500, 0x101); } static int nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_channel *chan = dev_priv->fifos[channel]; uint32_t inst; DRM_DEBUG("ch%d\n", channel); if (!chan->ramfc) return -EINVAL; if (IS_G80) inst = chan->ramfc->instance >> 12; else inst = chan->ramfc->instance >> 8; NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); if (!nt) nv50_fifo_init_thingo(dev); return 0; } static void nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t inst; DRM_DEBUG("ch%d, nt=%d\n", channel, nt); if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80; else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84; NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst); if (!nt) nv50_fifo_init_thingo(dev); } static void nv50_fifo_init_reset(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t pmc_e; DRM_DEBUG("\n"); pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO); pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO); } static void nv50_fifo_init_intr(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); } static void nv50_fifo_init_context_table(struct drm_device *dev) { int i; DRM_DEBUG("\n"); for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) nv50_fifo_channel_disable(dev, i, 1); nv50_fifo_init_thingo(dev); } static void nv50_fifo_init_regs__nv(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); NV_WRITE(0x250c, 0x6f3cfc34); } static int nv50_fifo_init_regs(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); NV_WRITE(0x2500, 0); NV_WRITE(0x3250, 0); NV_WRITE(0x3220, 0); NV_WRITE(0x3204, 0); NV_WRITE(0x3210, 0); NV_WRITE(0x3270, 0); /* Enable dummy channels setup by nv50_instmem.c */ nv50_fifo_channel_enable(dev, 0, 1); nv50_fifo_channel_enable(dev, 127, 1); return 0; } int nv50_fifo_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv; int ret; DRM_DEBUG("\n"); priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); if (!priv) return -ENOMEM; dev_priv->Engine.fifo.priv = priv; nv50_fifo_init_reset(dev); nv50_fifo_init_intr(dev); if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo))) { DRM_ERROR("error creating thingo: %d\n", ret); return ret; } nv50_fifo_init_context_table(dev); nv50_fifo_init_regs__nv(dev); if ((ret = nv50_fifo_init_regs(dev))) return ret; return 0; } void nv50_fifo_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; DRM_DEBUG("\n"); if (!priv) return; nouveau_gpuobj_ref_del(dev, &priv->thingo); dev_priv->Engine.fifo.priv = NULL; drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); } int nv50_fifo_channel_id(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) & NV50_PFIFO_CACHE1_PUSH1_CHID_MASK); } int nv50_fifo_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *ramfc = NULL; int ret; DRM_DEBUG("ch%d\n", chan->id);