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/*
 * Copyright 2004 The Unichrome Project. All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE UNICHROME PROJECT, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Author: Thomas Hellström 2004.
 */

#ifndef _VIA_VERIFIER_H_
#define _VIA_VERIFIER_H_

typedef enum {
	no_sequence = 0, 
	z_address,
	dest_address,
	tex_address
} drm_via_sequence_t;



typedef struct {
	unsigned texture;
	uint32_t z_addr; 
	uint32_t d_addr; 
	uint32_t t_addr[2][10];
	uint32_t pitch[2][10];
	uint32_t height[2][10];
	uint32_t tex_level_lo[2]; 
	uint32_t tex_level_hi[2];
	uint32_t tex_palette_size[2];
        uint32_t tex_npot[2];
	drm_via_sequence_t unfinished;
	int agp_texture;
	int multitex;
	drm_device_t *dev;
	drm_local_map_t *map_cache;
	uint32_t vertex_count;
	int agp;
	const uint32_t *buf_start;
} drm_via_state_t;

extern int via_verify_command_stream(const uint32_t * buf, unsigned int size, 
				    drm_device_t *dev, int agp);
extern int via_parse_command_stream(drm_device_t *dev, const uint32_t * buf,
                                   unsigned int size);

#endif
an> * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "drmP.h" # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) #define ATI_PCIE_WRITE 0x4 #define ATI_PCIE_READ 0x8 static int drm_ati_alloc_pcigart_table(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) { gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size, PAGE_SIZE, gart_info->table_mask); if (gart_info->table_handle == NULL) return -ENOMEM; return 0; } static void drm_ati_free_pcigart_table(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) { drm_pci_free(dev, gart_info->table_handle); gart_info->table_handle = NULL; } int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) { struct drm_sg_mem *entry = dev->sg; unsigned long pages; int i; int max_pages; /* we need to support large memory configurations */ if (!entry) { DRM_ERROR("no scatter/gather memory!\n"); return 0; } if (gart_info->bus_addr) { max_pages = (gart_info->table_size / sizeof(u32)); pages = (entry->pages <= max_pages) ? entry->pages : max_pages; for (i = 0; i < pages; i++) { if (!entry->busaddr[i]) break; pci_unmap_single(dev->pdev, entry->busaddr[i], PAGE_SIZE, PCI_DMA_TODEVICE); } if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) gart_info->bus_addr = 0; } if (gart_info->gart_table_location == DRM_ATI_GART_MAIN && gart_info->table_handle) { drm_ati_free_pcigart_table(dev, gart_info); } return 1; } EXPORT_SYMBOL(drm_ati_pcigart_cleanup); int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) { struct drm_sg_mem *entry = dev->sg; void *address = NULL; unsigned long pages; u32 *pci_gart, page_base; dma_addr_t bus_address = 0; int i, j, ret = 0; int max_pages; dma_addr_t entry_addr; if (!entry) { DRM_ERROR("no scatter/gather memory!\n"); goto done; } if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); ret = drm_ati_alloc_pcigart_table(dev, gart_info); if (ret) { DRM_ERROR("cannot allocate PCI GART page!\n"); goto done; } address = gart_info->table_handle->vaddr; bus_address = gart_info->table_handle->busaddr; } else { address = gart_info->addr; bus_address = gart_info->bus_addr; DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n", bus_address, (unsigned long)address); } pci_gart = (u32 *) address; max_pages = (gart_info->table_size / sizeof(u32)); pages = (entry->pages <= max_pages) ? entry->pages : max_pages; memset(pci_gart, 0, max_pages * sizeof(u32)); for (i = 0; i < pages; i++) { /* we need to support large memory configurations */ entry->busaddr[i] = pci_map_single(dev->pdev, page_address(entry-> pagelist[i]), PAGE_SIZE, PCI_DMA_TODEVICE); if (entry->busaddr[i] == 0) { DRM_ERROR("unable to map PCIGART pages!\n"); drm_ati_pcigart_cleanup(dev, gart_info); address = NULL; bus_address = 0; goto done; } entry_addr = entry->busaddr[i]; for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { page_base = (u32) entry_addr & ATI_PCIGART_PAGE_MASK; switch(gart_info->gart_reg_if) { case DRM_ATI_GART_IGP: page_base |= (upper_32_bits(entry_addr) & 0xff) << 4; page_base |= 0xc; break; case DRM_ATI_GART_PCIE: page_base >>= 8; page_base |= (upper_32_bits(entry_addr) & 0xff) << 24; page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE; break; default: case DRM_ATI_GART_PCI: break; } *pci_gart = cpu_to_le32(page_base); pci_gart++; entry_addr += ATI_PCIGART_PAGE_SIZE; } } ret = 1; #if defined(__i386__) || defined(__x86_64__) wbinvd(); #else mb(); #endif done: gart_info->addr = address; gart_info->bus_addr = bus_address; return ret; } EXPORT_SYMBOL(drm_ati_pcigart_init);