/* * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sub license, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef VIA_3D_REG_H #define VIA_3D_REG_H #define HC_REG_BASE 0x0400 #define HC_REG_TRANS_SPACE 0x0040 #define HC_ParaN_MASK 0xffffffff #define HC_Para_MASK 0x00ffffff #define HC_SubA_MASK 0xff000000 #define HC_SubA_SHIFT 24 /* Transmission Setting */ #define HC_REG_TRANS_SET 0x003c #define HC_ParaSubType_MASK 0xff000000 #define HC_ParaType_MASK 0x00ff0000 #define HC_ParaOS_MASK 0x0000ff00 #define HC_ParaAdr_MASK 0x000000ff #define HC_ParaSubType_SHIFT 24 #define HC_ParaType_SHIFT 16 #define HC_ParaOS_SHIFT 8 #define HC_ParaAdr_SHIFT 0 #define HC_ParaType_CmdVdata 0x0000 #define HC_ParaType_NotTex 0x0001 #define HC_ParaType_Tex 0x0002 #define HC_ParaType_Palette 0x0003 #define HC_ParaType_PreCR 0x0010 #define HC_ParaType_Auto 0x00fe /* Transmission Space */ #define HC_REG_Hpara0 0x0040 #define HC_REG_HpataAF 0x02fc /* Read */ #define HC_REG_HREngSt 0x0000 #define HC_REG_HRFIFOempty 0x0004 #define HC_REG_HRFIFOfull 0x0008 #define HC_REG_HRErr 0x000c #define HC_REG_FIFOstatus 0x0010 /* HC_REG_HREngSt 0x0000 */ #define HC_HDASZC_MASK 0x00010000 #define HC_HSGEMI_MASK 0x0000f000 #define HC_HLGEMISt_MASK 0x00000f00 #define HC_HCRSt_MASK 0x00000080 #define HC_HSE0St_MASK 0x00000040 #define HC_HSE1St_MASK 0x00000020 #define HC_HPESt_MASK 0x00000010 #define HC_HXESt_MASK 0x00000008 #define HC_HBESt_MASK 0x00000004 #define HC_HE2St_MASK 0x00000002 #define HC_HE3St_MASK 0x00000001 /* HC_REG_HRFIFOempty 0x0004 */ #define HC_HRZDempty_MASK 0x00000010 #define HC_HRTXAempty_MASK 0x00000008 #define HC_HRTXDempty_MASK 0x00000004 #define HC_HWZDempty_MASK 0x00000002 #define HC_HWCDempty_MASK 0x00000001 /* HC_REG_HRFIFOfull 0x0008 */ #define HC_HRZDfull_MASK 0x00000010 #define HC_HRTXAfull_MASK 0x00000008 #define HC_HRTXDfull_MASK 0x00000004 #define HC_HWZDfull_MASK 0x00000002 #define HC_HWCDfull_MASK 0x00000001 /* HC_REG_HRErr 0x000c */ #define HC_HAGPCMErr_MASK 0x80000000 #define HC_HAGPCMErrC_MASK 0x70000000 /* HC_REG_FIFOstatus 0x0010 */ #define HC_HRFIFOATall_MASK 0x80000000 #define HC_HRFIFOATbusy_MASK 0x40000000 #define HC_HRATFGMDo_MASK 0x00000100 #define HC_HRATFGMDi_MASK 0x00000080 #define HC_HRATFRZD_MASK 0x00000040 #define HC_HRATFRTXA_MASK 0x00000020 #define HC_HRATFRTXD_MASK 0x00000010 #define HC_HRATFWZD_MASK 0x00000008 #define HC_HRATFWCD_MASK 0x00000004 #define HC_HRATTXTAG_MASK 0x00000002 #define HC_HRATTXCH_MASK 0x00000001 /* AGP Command Setting */ #define HC_SubA_HAGPBstL 0x0060 #define HC_SubA_HAGPBendL 0x0061 #defin#include "drmP.h" #include "drm.h" #include "nouveau_drv.h" #include "nouveau_drm.h" int nv40_mc_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t tmp; /* Power up everything, resetting each individual unit will * be done later if needed. */ NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); switch (dev_priv->chipset) { case 0x44: case 0x46: /* G72 */ case 0x4e: case 0x4c: /* C51_G7X */ tmp = NV_READ(NV40_PFB_020C); NV_WRITE(NV40_PMC_1700, tmp); NV_WRITE(NV40_PMC_1704, 0); NV_WRITE(NV40_PMC_1708, 0); NV_WRITE(NV40_PMC_170C, tmp); break; default: break; } return 0; } void nv40_mc_takedown(struct drm_device *dev) { }