/* i810_dma.c -- DMA support for the i810 -*- linux-c -*- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: Rickard E. (Rik) Faith * Jeff Hartmann * Keith Whitwell * */ #define __NO_VERSION__ #include "drmP.h" #include "i810_drv.h" #include /* For task queue support */ /* in case we don't have a 2.3.99-pre6 kernel or later: */ #ifndef VM_DONTCOPY #define VM_DONTCOPY 0 #endif #define I810_BUF_FREE 2 #define I810_BUF_CLIENT 1 #define I810_BUF_HARDWARE 0 #define I810_BUF_UNMAPPED 0 #define I810_BUF_MAPPED 1 #define I810_REG(reg) 2 #define I810_BASE(reg) ((unsigned long) \ dev->maplist[I810_REG(reg)]->handle) #define I810_ADDR(reg) (I810_BASE(reg) + reg) #define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg) #define I810_READ(reg) I810_DEREF(reg) #define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0) #define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg) #define I810_READ16(reg) I810_DEREF16(reg) #define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0) #define RING_LOCALS unsigned int outring, ringmask; volatile char *virt; #define BEGIN_LP_RING(n) do { \ if (I810_VERBOSE) \ DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \ n, __FUNCTION__); \ if (dev_priv->ring.space < n*4) \ i810_wait_ring(dev, n*4); \ dev_priv->ring.space -= n*4; \ outring = dev_priv->ring.tail; \ ringmask = dev_priv->ring.tail_mask; \ virt = dev_priv->ring.virtual_start; \ } while (0) #define ADVANCE_LP_RING() do { \ if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \ dev_priv->ring.tail = outring; \ I810_WRITE(LP_RING + RING_TAIL, outring); \ } while(0) #define OUT_RING(n) do { \ if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ *(volatile unsigned int *)(virt + outring) = n; \ outring += 4; \ outring &= ringmask; \ } while (0); static inline void i810_print_status_page(drm_device_t *dev) { drm_device_dma_t *dma = dev->dma; drm_i810_private_t *dev_priv = dev->dev_private; u32 *temp = (u32 *)dev_priv->hw_status_page; int i; DRM_DEBUG( "hw_status: Interrupt Status : %x\n", temp[0]); DRM_DEBUG( "hw_status: LpRing Head ptr : %x\n", temp[1]); DRM_DEBUG( "hw_status: IRing Head ptr : %x\n", temp[2]); DRM_DEBUG( "hw_status: Reserved : %x\n", temp[3]); DRM_DEBUG( "hw_status: Driver Counter : %d\n", temp[5]); for(i = 6; i < dma->buf_count + 6; i++) { DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 6, temp[i]); } } static drm_buf_t *i810_freelist_get(drm_device_t *dev) { drm_device_dma_t *dma = dev->dma; int i; int used; /* Linear search might not be the best solution */ for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i810_buf_priv_t *buf_priv = buf->dev_private; /* In use is already a pointer */ used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, I810_BUF_CLIENT); if(used == I810_BUF_FREE) { return buf; } } return NULL; } /* This should only be called if the buffer is not sent to the hardware * yet, the hardware updates in use for us once its on the ring buffer. */ static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf) { drm_i810_buf_priv_t *buf_priv = buf->dev_private; int used; /* In use is already a pointer */ used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); if(used != I810_BUF_CLIENT) { DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); return -EINVAL; } return 0; } static struct file_operations i810_buffer_fops = { open: i810_open, flush: drm_flush, release: i810_release, ioctl: i810_ioctl, mmap: i810_mmap_buffers, read: drm_read, fasync: drm_fasync, poll: drm_poll, }; int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) { drm_file_t *priv = filp->private_data; drm_device_t *dev; drm_i810_private_t *dev_priv; drm_buf_t *buf; drm_i810_buf_priv_t *buf_priv; lock_kernel(); dev = priv->dev; dev_priv = dev->dev_private; buf = dev_priv->mmap_buffer; buf_priv = buf->dev_private; vma->vm_flags |= (VM_IO | VM_DONTCOPY); vma->vm_file = filp; buf_priv->currently_mapped = I810_BUF_MAPPED; unlock_kernel(); if (remap_page_range(vma->vm_start, VM_OFFSET(vma), vma->vm_end - vma->vm_start, vma->vm_page_prot)) return -EAGAIN; return 0; } static int i810_map_buffer(drm_buf_t *buf, struct file *filp) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i810_buf_priv_t *buf_priv = buf->dev_private; drm_i810_private_t *dev_priv = dev->dev_private; struct file_operations *old_fops; int retcode = 0; if(buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL; if(VM_DONTCOPY != 0) { down(¤t->mm->mmap_sem); old_fops = filp->f_op; filp->f_op = &i810_buffer_fops; dev_priv->mmap_buffer = buf; buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, PROT_READ|PROT_WRITE, MAP_SHARED, buf->bus_address); dev_priv->mmap_buffer = NULL; filp->f_op = old_fops; if ((unsigned long)buf_priv->virtual > -1024UL) { /* Real error */ DRM_DEBUG("mmap error\n"); retcode = (signed int)buf_priv->virtual; buf_priv->virtual = 0; } up(¤t->mm->mmap_sem); } else { buf_priv->virtual = buf_priv->kernel_virtual; buf_priv->currently_mapped = I810_BUF_MAPPED; } return retcode; } static int i810_unmap_buffer(drm_buf_t *buf) { drm_i810_buf_priv_t *buf_priv = buf->dev_private; int retcode = 0; if(VM_DONTCOPY != 0) { if(buf_priv->currently_mapped != I810_BUF_MAPPED) return -EINVAL; down(¤t->mm->mmap_sem); #if LINUX_VERSION_CODE < 0x020399 retcode = do_munmap((unsigned long)buf_priv->virtual, (size_t) buf->total); #else retcode = do_munmap(current->mm, (unsigned long)buf_priv->virtual, (size_t) buf->total); #endif up(¤t->mm->mmap_sem); } buf_priv->currently_mapped = I810_BUF_UNMAPPED; buf_priv->virtual = 0; return retcode; } static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d, struct file *filp) { drm_file_t *priv = filp->private_data; drm_buf_t *buf; drm_i810_buf_priv_t *buf_priv; int retcode = 0; buf = i810_freelist_get(dev); if (!buf) { retcode = -ENOMEM; DRM_DEBUG("retcode=%d\n", retcode); return retcode; } retcode = i810_map_buffer(buf, filp); if(retcode) { i810_freelist_put(dev, buf); DRM_DEBUG("mapbuf failed, retcode %d\n", retcode); return retcode; } buf->pid = priv->pid; buf_priv = buf->dev_private; d->granted = 1; d->request_idx = buf->idx; d->request_size = buf->total; d->virtual = buf_priv->virtual; return retcode; } static unsigned long i810_alloc_page(drm_device_t *dev) { unsigned long address; address = __get_free_page(GFP_KERNEL); if(address == 0UL) return 0; atomic_inc(&virt_to_page(address)->count); set_bit(PG_locked, &virt_to_page(address)->flags); return address; } static void i810_free_page(drm_device_t *dev, unsigned long page) { if(page == 0UL) return; atomic_dec(&virt_to_page(page)->count); clear_bit(PG_locked, &virt_to_page(page)->flags); wake_up(&virt_to_page(page)->wait); free_page(page); return; } static int i810_dma_cleanup(drm_device_t *dev) { drm_device_dma_t *dma = dev->dma; if(dev->dev_private) { int i; drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; if(dev_priv->ring.virtual_start) { drm_ioremapfree((void *) dev_priv->ring.virtual_start, dev_priv->ring.Size); } if(dev_priv->hw_status_page != 0UL) { i810_free_page(dev, dev_priv->hw_status_page); /* Need to rewrite hardware status page */ I810_WRITE(0x02080, 0x1ffff000); } drm_free(dev->dev_private, sizeof(drm_i810_private_t), DRM_MEM_DRIVER); dev->dev_private = NULL; for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i810_buf_priv_t *buf_priv = buf->dev_private; drm_ioremapfree(buf_priv->kernel_virtual, buf->total); } } return 0; } static int i810_wait_ring(drm_device_t *dev, int n) { drm_i810_private_t *dev_priv = dev->dev_private; drm_i810_ring_buffer_t *ring = &(dev_priv->ring); int iters = 0; unsign/* * Copyright (C) 2007 Ben Skeggs. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include "drmP.h" #include "nouveau_drv.h" #include "nouveau_drm.h" #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \ NV40_RAMFC_##offset/4, (val)) #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ NV40_RAMFC_##offset/4) #define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c)*NV40_RAMFC__SIZE)) #define NV40_RAMFC__SIZE 128 int nv40_fifo_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0, NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, NULL, &chan->ramfc))) return ret; /* Fill entries that are seen filled in dumps of nvidia driver just * after channel's is put into DMA mode */ RAMFC_WR(DMA_PUT , chan->pushbuf_base); RAMFC_WR(DMA_GET , chan->pushbuf_base); RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4); RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | #ifdef __BIG_ENDIAN NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0x30000000 /* no idea.. */); RAMFC_WR(DMA_SUBROUTINE, 0); RAMFC_WR(GRCTX_INSTANCE, chan->ramin_grctx->instance >> 4); RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); /* enable the fifo dma operation */ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id)); return 0; } void nv40_fifo_destroy_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id)); if (chan->ramfc) nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int nv40_fifo_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t tmp, tmp2; NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , RAMFC_RD(DMA_INSTANCE)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , RAMFC_RD(DMA_DCOUNT)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE)); /* No idea what 0x2058 is.. */ tmp = RAMFC_RD(DMA_FETCH); tmp2 = NV_READ(0x2058) & 0xFFF; tmp2 |= (tmp & 0x30000000); NV_WRITE(0x2058, tmp2); tmp &= ~0x30000000; NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , tmp); NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE)); NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE)); NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE , RAMFC_RD(ACQUIRE_VALUE)); NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP)); NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT , RAMFC_RD(ACQUIRE_TIMEOUT)); NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE , RAMFC_RD(SEMAPHORE)); NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE , RAMFC_RD(DMA_SUBROUTINE)); NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE , RAMFC_RD(GRCTX_INSTANCE)); NV_WRITE(0x32e4, RAMFC_RD(UNK_40)); /* NVIDIA does this next line twice... */ NV_WRITE(0x32e8, RAMFC_RD(UNK_44)); NV_WRITE(0x2088, RAMFC_RD(UNK_4C)); NV_WRITE(0x3300, RAMFC_RD(UNK_50)); /* not sure what part is PUT, and which is GET.. never seen a non-zero * value appear in a mmio-trace yet.. */ #if 0 tmp = NV_READ(UNK_84); NV_WRITE(NV_PFIFO_CACHE1_GET, tmp ???); NV_WRITE(NV_PFIFO_CACHE1_PUT, tmp ???); #endif /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */ tmp = NV_READ(NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF; tmp |= RAMFC_RD(DMA_TIMESLICE) & 0x1FFFF; NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp); /* Set channel active, and in DMA mode */ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00010000 | chan->id); /* Reset DMA_CTL_AT_INFO to INVALID */ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); return 0; } int nv40_fifo_save_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE)); RAMFC_WR(DMA_DCOUNT , NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT)); RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH); tmp |= NV_READ(0x2058) & 0x30000000; RAMFC_WR(DMA_FETCH , tmp); RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); tmp = NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP); RAMFC_WR(ACQUIRE_TIMESTAMP, tmp); RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something * more involved depending on the value of 0x3228? */ RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE)); /* No idea what the below is for exactly, ripped from a mmio-trace */ RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4)); /* NVIDIA do this next line twice.. bug? */ RAMFC_WR(UNK_44 , NV_READ(0x32e8)); RAMFC_WR(UNK_4C , NV_READ(0x2088)); RAMFC_WR(UNK_50 , NV_READ(0x3300)); #if 0 /* no real idea which is PUT/GET in UNK_48.. */ tmp = NV_READ(NV04_PFIFO_CACHE1_GET); tmp |= (NV_READ(NV04_PFIFO_CACHE1_PUT) << 16); RAMFC_WR(UNK_48 , tmp); #endif return 0; } int nv40_fifo_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; if ((ret = nouveau_fifo_init(dev))) return ret; NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff); return 0; }
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-26 08:03:30 +0000
dev, clear.flags, clear.clear_color, clear.clear_depth ); return 0; } int i810_swap_bufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; DRM_DEBUG("i810_swap_bufs\n"); if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i810_swap_buf called without lock held\n"); return -EINVAL; } i810_dma_dispatch_swap( dev ); return 0; } int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; u32 *hw_status = (u32 *)dev_priv->hw_status_page; drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) dev_priv->sarea_priv; sarea_priv->last_dispatch = (int) hw_status[5]; return 0; } int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; int retcode = 0; drm_i810_dma_t d; drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; u32 *hw_status = (u32 *)dev_priv->hw_status_page; drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) dev_priv->sarea_priv; DRM_DEBUG("getbuf\n"); if (copy_from_user(&d, (drm_i810_dma_t *)arg, sizeof(d))) return -EFAULT; if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i810_dma called without lock held\n"); return -EINVAL; } d.granted = 0; retcode = i810_dma_get_buffer(dev, &d, filp); DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n", current->pid, retcode, d.granted); if (copy_to_user((drm_dma_t *)arg, &d, sizeof(d))) return -EFAULT; sarea_priv->last_dispatch = (int) hw_status[5]; return retcode; } int i810_copybuf(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i810_copy_t d; drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; u32 *hw_status = (u32 *)dev_priv->hw_status_page; drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) dev_priv->sarea_priv; drm_buf_t *buf; drm_i810_buf_priv_t *buf_priv; drm_device_dma_t *dma = dev->dma; if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i810_dma called without lock held\n"); return -EINVAL; } if (copy_from_user(&d, (drm_i810_copy_t *)arg, sizeof(d))) return -EFAULT; if(d.idx > dma->buf_count) return -EINVAL; buf = dma->buflist[ d.idx ]; buf_priv = buf->dev_private; if (buf_priv->currently_mapped != I810_BUF_MAPPED) return -EPERM; if (copy_from_user(buf_priv->virtual, d.address, d.used)) return -EFAULT; sarea_priv->last_dispatch = (int) hw_status[5]; return 0; } int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { if(VM_DONTCOPY == 0) return 1; return 0; }