1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
|
#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"
/*
* NV20
* -----
* There are 3 families :
* NV20 is 0x10de:0x020*
* NV25/28 is 0x10de:0x025* / 0x10de:0x028*
* NV2A is 0x10de:0x02A0
*
* NV30
* -----
* There are 3 families :
* NV30/31 is 0x10de:0x030* / 0x10de:0x031*
* NV34 is 0x10de:0x032*
* NV35/36 is 0x10de:0x033* / 0x10de:0x034*
*
* Not seen in the wild, no dumps (probably NV35) :
* NV37 is 0x10de:0x00fc, 0x10de:0x00fd
* NV38 is 0x10de:0x0333, 0x10de:0x00fe
*
*/
#define NV20_GRCTX_SIZE (3580*4)
#define NV25_GRCTX_SIZE (3529*4)
#define NV2A_GRCTX_SIZE (3500*4)
#define NV30_31_GRCTX_SIZE (24392)
#define NV34_GRCTX_SIZE (18140)
#define NV35_36_GRCTX_SIZE (22396)
static void nv20_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
/*
write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements:
+0x00740adc: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bfc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740c1c: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740c3c: 00000000 00000000 00000000 44400000 00000000 00000000 00000000 00000000
+0x00740c5c: 00000000 00000000 00000000 00000000 00000000 00000000 00030303 00030303
+0x00740c7c: 00030303 00030303 00000000 00000000 00000000 00000000 00080000 00080000
+0x00740c9c: 00080000 00080000 00000000 00000000 01012000 01012000 01012000 01012000
+0x00740cbc: 000105b8 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008
+0x00740cdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740cfc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740d1c: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740d3c: 00000000 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000
+0x00740d5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d9c: 00000001 00000000 00004000 00000000 00000000 00000001 00000000 00040000
+0x00740dbc: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740ddc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
*/
INSTANCE_WR(ctx, (0x33c/4)+0, 0xffff0000);
INSTANCE_WR(ctx, (0x33c/4)+25, 0x0fff0000);
INSTANCE_WR(ctx, (0x33c/4)+26, 0x0fff0000);
INSTANCE_WR(ctx, (0x33c/4)+80, 0x00000101);
INSTANCE_WR(ctx, (0x33c/4)+85, 0x00000111);
INSTANCE_WR(ctx, (0x33c/4)+91, 0x44400000);
for (i = 0; i < 4; ++i)
INSTANCE_WR(ctx, (0x33c/4)+102+i, 0x00030303);
for (i = 0; i < 4; ++i)
INSTANCE_WR(ctx, (0x33c/4)+110+i, 0x00080000);
for (i = 0; i < 4; ++i)
INSTANCE_WR(ctx, (0x33c/4)+116+i, 0x01012000);
for (i = 0; i < 4; ++i)
INSTANCE_WR(ctx, (0x33c/4)+120+i, 0x000105b8);
for (i = 0; i < 4; ++i)
INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008);
for (i = 0; i < 16; ++i)
INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000);
INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7fffff);
INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001);
INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000);
INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001);
INSTANCE_WR(ctx, (0x33c/4)+183, 0x00040000);
INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000);
/*
...
+0x0074239c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x007423bc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x007423dc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x007423fc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
...
+0x00742bdc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742bfc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742c1c: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742c3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
*/
for (i = 0; i < 0x880; i += 0x10) {
INSTANCE_WR(ctx, ((0x1c1c + i)/4)+0, 0x10700ff9);
INSTANCE_WR(ctx, ((0x1c1c + i)/4)+1, 0x0436086c);
INSTANCE_WR(ctx, ((0x1c1c + i)/4)+2, 0x000c001b);
}
/*
write32 #1 block at +0x00742fbc NV_PRAMIN+0x42fbc of 4 (0x4) elements:
+0x00742fbc: 3f800000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x281c/4), 0x3f800000);
/*
write32 #1 block at +0x00742ffc NV_PRAMIN+0x42ffc of 12 (0xc) elements:
+0x00742ffc: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
+0x0074301c: 00000000 bf800000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x285c/4)+0, 0x40000000);
INSTANCE_WR(ctx, (0x285c/4)+1, 0x3f800000);
INSTANCE_WR(ctx, (0x285c/4)+2, 0x3f000000);
INSTANCE_WR(ctx, (0x285c/4)+4, 0x40000000);
INSTANCE_WR(ctx, (0x285c/4)+5, 0x3f800000);
INSTANCE_WR(ctx, (0x285c/4)+7, 0xbf800000);
INSTANCE_WR(ctx, (0x285c/4)+9, 0xbf800000);
/*
write32 #1 block at +0x00742fcc NV_PRAMIN+0x42fcc of 4 (0x4) elements:
+0x00742fcc: 00000000 3f800000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x282c/4)+1, 0x3f800000);
/*
write32 #1 block at +0x0074302c NV_PRAMIN+0x4302c of 4 (0x4) elements:
+0x0074302c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743c9c NV_PRAMIN+0x43c9c of 4 (0x4) elements:
+0x00743c9c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743c3c NV_PRAMIN+0x43c3c of 8 (0x8) elements:
+0x00743c3c: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x349c/4)+2, 0x000fe000);
/*
write32 #1 block at +0x00743c6c NV_PRAMIN+0x43c6c of 4 (0x4) elements:
+0x00743c6c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743ccc NV_PRAMIN+0x43ccc of 4 (0x4) elements:
+0x00743ccc: 00000000 000003f8 00000000 00000000
*/
INSTANCE_WR(ctx, (0x352c/4)+1, 0x000003f8);
/* write32 #1 NV_PRAMIN+0x43ce0 <- 0x002fe000 */
INSTANCE_WR(ctx, 0x3540/4, 0x002fe000);
/*
write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements:
+0x00743cfc: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
*/
for (i = 0; i < 8; ++i)
INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c);
}
static void nv2a_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
INSTANCE_WR(ctx, 0x33c/4, 0xffff0000);
for(i = 0x3a0; i< 0x3a8; i += 4)
INSTANCE_WR(ctx, i/4, 0x0fff0000);
INSTANCE_WR(ctx, 0x47c/4, 0x00000101);
INSTANCE_WR(ctx, 0x490/4, 0x00000111);
INSTANCE_WR(ctx, 0x4a8/4, 0x44400000);
for(i = 0x4d4; i< 0x4e4; i += 4)
INSTANCE_WR(ctx, i/4, 0x00030303);
for(i = 0x4f4; i< 0x504; i += 4)
INSTANCE_WR(ctx, i/4, 0x00080000);
for(i = 0x50c; i< 0x51c; i += 4)
INSTANCE_WR(ctx, i/4, 0x01012000);
for(i = 0x51c; i< 0x52c; i += 4)
INSTANCE_WR(ctx, i/4, 0x000105b8);
for(i = 0x52c; i< 0x53c; i += 4)
INSTANCE_WR(ctx, i/4, 0x00080008);
for(i = 0x55c; i< 0x59c; i += 4)
INSTANCE_WR(ctx, i/4, 0x07ff0000);
INSTANCE_WR(ctx, 0x5a4/4, 0x4b7fffff);
INSTANCE_WR(ctx, 0x5fc/4, 0x00000001);
INSTANCE_WR(ctx, 0x604/4, 0x00004000);
INSTANCE_WR(ctx, 0x610/4, 0x00000001);
INSTANCE_WR(ctx, 0x618/4, 0x00040000);
INSTANCE_WR(ctx, 0x61c/4, 0x00010000);
for (i=0x1a9c; i <= 0x22fc/4; i += 32) {
INSTANCE_WR(ctx, i/4 , 0x10700ff9);
INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
}
INSTANCE_WR(ctx, 0x269c/4, 0x3f800000);
INSTANCE_WR(ctx, 0x26b0/4, 0x3f800000);
INSTANCE_WR(ctx, 0x26dc/4, 0x40000000);
INSTANCE_WR(ctx, 0x26e0/4, 0x3f800000);
INSTANCE_WR(ctx, 0x26e4/4, 0x3f000000);
INSTANCE_WR(ctx, 0x26ec/4, 0x40000000);
INSTANCE_WR(ctx, 0x26f0/4, 0x3f800000);
INSTANCE_WR(ctx, 0x26f8/4, 0xbf800000);
INSTANCE_WR(ctx, 0x2700/4, 0xbf800000);
INSTANCE_WR(ctx, 0x3024/4, 0x000fe000);
INSTANCE_WR(ctx, 0x30a0/4, 0x000003f8);
INSTANCE_WR(ctx, 0x33fc/4, 0x002fe000);
for(i = 0x341c; i< 0x343c; i += 4)
INSTANCE_WR(ctx, i/4, 0x001c527c);
}
static void nv25_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
/*
write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements:
+0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000
+0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000
+0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303
+0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000
+0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8
+0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000
+0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000
+0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000
+0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d1c: 00000000 00000000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000);
INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000);
INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000);
INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101);
INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111);
INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080);
INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000);
INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001);
INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000);
INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000);
INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303);
INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303);
INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303);
INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303);
INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000);
INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000);
INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000);
INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000);
INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000);
INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000);
INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000);
INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000);
INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8);
INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8);
INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8);
INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8);
INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008);
INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008);
INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008);
INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008);
for (i=0; i<16; ++i)
INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000);
INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7fffff);
/*
write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements:
+0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0
+0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000
+0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000
+0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
+0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
...
+0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000
+0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080);
INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000);
INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040);
INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080);
INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0);
INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001);
INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000);
INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001);
INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000);
INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000);
for (i=0; i < 0x880/4; i+=4) {
INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9);
INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c);
INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b);
}
/*
write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements:
+0x00742e24: 3f800000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x2704/4), 0x3f800000);
/*
write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements:
+0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
+0x00742e84: 00000000 bf800000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000);
INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000);
INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000);
INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000);
INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000);
INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000);
INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000);
/*
write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements:
+0x00742e34: 00000000 3f800000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000);
/*
write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements:
+0x00742e94: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements:
+0x00743804: 00000000 00000000 00000000 00000000
write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements:
+0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000);
/*
write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements:
+0x007437d4: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements:
+0x00743824: 00000000 000003f8 00000000 00000000
*/
INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8);
/* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */
INSTANCE_WR(ctx, 0x3468/4, 0x002fe000);
/*
write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements:
+0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
*/
for (i=0; i<8; ++i)
INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c);
}
static void nv30_31_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
INSTANCE_WR(ctx, 0x410/4, 0x00000101);
INSTANCE_WR(ctx, 0x424/4, 0x00000111);
INSTANCE_WR(ctx, 0x428/4, 0x00000060);
INSTANCE_WR(ctx, 0x444/4, 0x00000080);
INSTANCE_WR(ctx, 0x448/4, 0xffff0000);
INSTANCE_WR(ctx, 0x44c/4, 0x00000001);
INSTANCE_WR(ctx, 0x460/4, 0x44400000);
INSTANCE_WR(ctx, 0x48c/4, 0xffff0000);
for(i = 0x4e0; i< 0x4e8; i += 4)
INSTANCE_WR(ctx, i/4, 0x0fff0000);
INSTANCE_WR(ctx, 0x4ec/4, 0x00011100);
for(i = 0x508; i< 0x548; i += 4)
INSTANCE_WR(ctx, i/4, 0x07ff0000);
INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff);
INSTANCE_WR(ctx, 0x58c/4, 0x00000080);
INSTANCE_WR(ctx, 0x590/4, 0x30201000);
INSTANCE_WR(ctx, 0x594/4, 0x70605040);
INSTANCE_WR(ctx, 0x598/4, 0xb8a89888);
INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8);
INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000);
for(i = 0x600; i< 0x640; i += 4)
INSTANCE_WR(ctx, i/4, 0x00010588);
for(i = 0x640; i< 0x680; i += 4)
INSTANCE_WR(ctx, i/4, 0x00030303);
for(i = 0x6c0; i< 0x700; i += 4)
INSTANCE_WR(ctx, i/4, 0x0008aae4);
for(i = 0x700; i< 0x740; i += 4)
INSTANCE_WR(ctx, i/4, 0x01012000);
for(i = 0x740; i< 0x780; i += 4)
INSTANCE_WR(ctx, i/4, 0x00080008);
INSTANCE_WR(ctx, 0x85c/4, 0x00040000);
INSTANCE_WR(ctx, 0x860/4, 0x00010000);
for(i = 0x864; i< 0x874; i += 4)
INSTANCE_WR(ctx, i/4, 0x00040004);
for(i = 0x1f18; i<= 0x3088 ; i+= 16) {
INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
}
for(i = 0x30b8; i< 0x30c8; i += 4)
INSTANCE_WR(ctx, i/4, 0x0000ffff);
INSTANCE_WR(ctx, 0x344c/4, 0x3f800000);
INSTANCE_WR(ctx, 0x3808/4, 0x3f800000);
INSTANCE_WR(ctx, 0x381c/4, 0x3f800000);
INSTANCE_WR(ctx, 0x3848/4, 0x40000000);
INSTANCE_WR(ctx, 0x384c/4, 0x3f800000);
INSTANCE_WR(ctx, 0x3850/4, 0x3f000000);
INSTANCE_WR(ctx, 0x3858/4, 0x40000000);
INSTANCE_WR(ctx, 0x385c/4, 0x3f800000);
INSTANCE_WR(ctx, 0x3864/4, 0xbf800000);
INSTANCE_WR(ctx, 0x386c/4, 0xbf800000);
}
static void nv34_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
INSTANCE_WR(ctx, 0x40c/4, 0x01000101);
INSTANCE_WR(ctx, 0x420/4, 0x00000111);
INSTANCE_WR(ctx, 0x424/4, 0x00000060);
INSTANCE_WR(ctx, 0x440/4, 0x00000080);
INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
INSTANCE_WR(ctx, 0x448/4, 0x00000001);
INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
INSTANCE_WR(ctx, 0x480/4, 0xffff0000);
for(i = 0x4d4; i< 0x4dc; i += 4)
INSTANCE_WR(ctx, i/4, 0x0fff0000);
INSTANCE_WR(ctx, 0x4e0/4, 0x00011100);
for(i = 0x4fc; i< 0x53c; i += 4)
INSTANCE_WR(ctx, i/4, 0x07ff0000);
INSTANCE_WR(ctx, 0x544/4, 0x4b7fffff);
INSTANCE_WR(ctx, 0x57c/4, 0x00000080);
INSTANCE_WR(ctx, 0x580/4, 0x30201000);
INSTANCE_WR(ctx, 0x584/4, 0x70605040);
INSTANCE_WR(ctx, 0x588/4, 0xb8a89888);
INSTANCE_WR(ctx, 0x58c/4, 0xf8e8d8c8);
INSTANCE_WR(ctx, 0x5a0/4, 0xb0000000);
for(i = 0x5f0; i< 0x630; i += 4)
INSTANCE_WR(ctx, i/4, 0x00010588);
for(i = 0x630; i< 0x670; i += 4)
INSTANCE_WR(ctx, i/4, 0x00030303);
for(i = 0x6b0; i< 0x6f0; i += 4)
INSTANCE_WR(ctx, i/4, 0x0008aae4);
for(i = 0x6f0; i< 0x730; i += 4)
INSTANCE_WR(ctx, i/4, 0x01012000);
for(i = 0x730; i< 0x770; i += 4)
INSTANCE_WR(ctx, i/4, 0x00080008);
INSTANCE_WR(ctx, 0x850/4, 0x00040000);
INSTANCE_WR(ctx, 0x854/4, 0x00010000);
for(i = 0x858; i< 0x868; i += 4)
INSTANCE_WR(ctx, i/4, 0x00040004);
for(i = 0x15ac; i<= 0x271c ; i+= 16) {
INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
}
for(i = 0x274c; i< 0x275c; i += 4)
INSTANCE_WR(ctx, i/4, 0x0000ffff);
INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000);
INSTANCE_WR(ctx, 0x2e9c/4, 0x3f800000);
INSTANCE_WR(ctx, 0x2eb0/4, 0x3f800000);
INSTANCE_WR(ctx, 0x2edc/4, 0x40000000);
INSTANCE_WR(ctx, 0x2ee0/4, 0x3f800000);
INSTANCE_WR(ctx, 0x2ee4/4, 0x3f000000);
INSTANCE_WR(ctx, 0x2eec/4, 0x40000000);
INSTANCE_WR(ctx, 0x2ef0/4, 0x3f800000);
INSTANCE_WR(ctx, 0x2ef8/4, 0xbf800000);
INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000);
}
static void nv35_36_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
INSTANCE_WR(ctx, 0x40c/4, 0x00000101);
INSTANCE_WR(ctx, 0x420/4, 0x00000111);
INSTANCE_WR(ctx, 0x424/4, 0x00000060);
INSTANCE_WR(ctx, 0x440/4, 0x00000080);
INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
INSTANCE_WR(ctx, 0x448/4, 0x00000001);
INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
INSTANCE_WR(ctx, 0x488/4, 0xffff0000);
for(i = 0x4dc; i< 0x4e4; i += 4)
INSTANCE_WR(ctx, i/4, 0x0fff0000);
INSTANCE_WR(ctx, 0x4e8/4, 0x00011100);
for(i = 0x504; i< 0x544; i += 4)
INSTANCE_WR(ctx, i/4, 0x07ff0000);
INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff);
INSTANCE_WR(ctx, 0x588/4, 0x00000080);
INSTANCE_WR(ctx, 0x58c/4, 0x30201000);
INSTANCE_WR(ctx, 0x590/4, 0x70605040);
INSTANCE_WR(ctx, 0x594/4, 0xb8a89888);
INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8);
INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000);
for(i = 0x604; i< 0x644; i += 4)
INSTANCE_WR(ctx, i/4, 0x00010588);
for(i = 0x644; i< 0x684; i += 4)
INSTANCE_WR(ctx, i/4, 0x00030303);
for(i = 0x6c4; i< 0x704; i += 4)
INSTANCE_WR(ctx, i/4, 0x0008aae4);
for(i = 0x704; i< 0x744; i += 4)
INSTANCE_WR(ctx, i/4, 0x01012000);
for(i = 0x744; i< 0x784; i += 4)
INSTANCE_WR(ctx, i/4, 0x00080008);
INSTANCE_WR(ctx, 0x860/4, 0x00040000);
INSTANCE_WR(ctx, 0x864/4, 0x00010000);
for(i = 0x868; i< 0x878; i += 4)
INSTANCE_WR(ctx, i/4, 0x00040004);
for(i = 0x1f1c; i<= 0x308c ; i+= 16) {
INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
}
for(i = 0x30bc; i< 0x30cc; i += 4)
INSTANCE_WR(ctx, i/4, 0x0000ffff);
INSTANCE_WR(ctx, 0x3450/4, 0x3f800000);
INSTANCE_WR(ctx, 0x380c/4, 0x3f800000);
INSTANCE_WR(ctx, 0x3820/4, 0x3f800000);
INSTANCE_WR(ctx, 0x384c/4, 0x40000000);
INSTANCE_WR(ctx, 0x3850/4, 0x3f800000);
INSTANCE_WR(ctx, 0x3854/4, 0x3f000000);
INSTANCE_WR(ctx, 0x385c/4, 0x40000000);
INSTANCE_WR(ctx, 0x3860/4, 0x3f800000);
INSTANCE_WR(ctx, 0x3868/4, 0xbf800000);
INSTANCE_WR(ctx, 0x3870/4, 0xbf800000);
}
int nv20_graph_create_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
unsigned int ctx_size;
unsigned int idoffs = 0x28/4;
int ret;
switch (dev_priv->chipset) {
case 0x20:
ctx_size = NV20_GRCTX_SIZE;
ctx_init = nv20_graph_context_init;
idoffs = 0;
break;
case 0x25:
case 0x28:
ctx_size = NV25_GRCTX_SIZE;
ctx_init = nv25_graph_context_init;
break;
case 0x2a:
ctx_size = NV2A_GRCTX_SIZE;
ctx_init = nv2a_graph_context_init;
idoffs = 0;
break;
case 0x30:
case 0x31:
ctx_size = NV30_31_GRCTX_SIZE;
ctx_init = nv30_31_graph_context_init;
break;
case 0x34:
ctx_size = NV34_GRCTX_SIZE;
ctx_init = nv34_graph_context_init;
break;
case 0x35:
case 0x36:
ctx_size = NV35_36_GRCTX_SIZE;
ctx_init = nv35_36_graph_context_init;
break;
default:
ctx_size = 0;
ctx_init = nv35_36_graph_context_init;
DRM_ERROR("Please contact the devs if you want your NV%x"
" card to work\n", dev_priv->chipset);
return -ENOSYS;
break;
}
if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
NVOBJ_FLAG_ZERO_ALLOC,
&chan->ramin_grctx)))
return ret;
/* Initialise default context values */
ctx_init(dev, chan->ramin_grctx->gpuobj);
/* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
INSTANCE_WR(chan->ramin_grctx->gpuobj, idoffs, (chan->id<<24)|0x1);
/* CTX_USER */
INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
chan->ramin_grctx->instance >> 4);
return 0;
}
void nv20_graph_destroy_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
if (chan->ramin_grctx)
nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0);
}
int nv20_graph_load_context(struct nouveau_channel *chan)
{
struct drm_device
#define HC_SIMA_HDBFM 0x0033
#define HC_SIMA_HFBBMSKL 0x0034
#define HC_SIMA_HROP 0x0035
#define HC_SIMA_HFogLF 0x0036
#define HC_SIMA_HFogCL 0x0037
#define HC_SIMA_HFogCH 0x0038
#define HC_SIMA_HFogStL 0x0039
#define HC_SIMA_HFogStH 0x003a
#define HC_SIMA_HFogOOdMF 0x003b
#define HC_SIMA_HFogOOdEF 0x003c
#define HC_SIMA_HFogEndL 0x003d
#define HC_SIMA_HFogDenst 0x003e
/*---- start of texture 0 setting ----
*/
#define HC_SIMA_HTX0L0BasL 0x0040
#define HC_SIMA_HTX0L1BasL 0x0041
#define HC_SIMA_HTX0L2BasL 0x0042
#define HC_SIMA_HTX0L3BasL 0x0043
#define HC_SIMA_HTX0L4BasL 0x0044
#define HC_SIMA_HTX0L5BasL 0x0045
#define HC_SIMA_HTX0L6BasL 0x0046
#define HC_SIMA_HTX0L7BasL 0x0047
#define HC_SIMA_HTX0L8BasL 0x0048
#define HC_SIMA_HTX0L9BasL 0x0049
#define HC_SIMA_HTX0LaBasL 0x004a
#define HC_SIMA_HTX0LbBasL 0x004b
#define HC_SIMA_HTX0LcBasL 0x004c
#define HC_SIMA_HTX0LdBasL 0x004d
#define HC_SIMA_HTX0LeBasL 0x004e
#define HC_SIMA_HTX0LfBasL 0x004f
#define HC_SIMA_HTX0L10BasL 0x0050
#define HC_SIMA_HTX0L11BasL 0x0051
#define HC_SIMA_HTX0L012BasH 0x0052
#define HC_SIMA_HTX0L345BasH 0x0053
#define HC_SIMA_HTX0L678BasH 0x0054
#define HC_SIMA_HTX0L9abBasH 0x0055
#define HC_SIMA_HTX0LcdeBasH 0x0056
#define HC_SIMA_HTX0Lf1011BasH 0x0057
#define HC_SIMA_HTX0L0Pit 0x0058
#define HC_SIMA_HTX0L1Pit 0x0059
#define HC_SIMA_HTX0L2Pit 0x005a
#define HC_SIMA_HTX0L3Pit 0x005b
#define HC_SIMA_HTX0L4Pit 0x005c
#define HC_SIMA_HTX0L5Pit 0x005d
#define HC_SIMA_HTX0L6Pit 0x005e
#define HC_SIMA_HTX0L7Pit 0x005f
#define HC_SIMA_HTX0L8Pit 0x0060
#define HC_SIMA_HTX0L9Pit 0x0061
#define HC_SIMA_HTX0LaPit 0x0062
#define HC_SIMA_HTX0LbPit 0x0063
#define HC_SIMA_HTX0LcPit 0x0064
#define HC_SIMA_HTX0LdPit 0x0065
#define HC_SIMA_HTX0LePit 0x0066
#define HC_SIMA_HTX0LfPit 0x0067
#define HC_SIMA_HTX0L10Pit 0x0068
#define HC_SIMA_HTX0L11Pit 0x0069
#define HC_SIMA_HTX0L0_5WE 0x006a
#define HC_SIMA_HTX0L6_bWE 0x006b
#define HC_SIMA_HTX0Lc_11WE 0x006c
#define HC_SIMA_HTX0L0_5HE 0x006d
#define HC_SIMA_HTX0L6_bHE 0x006e
#define HC_SIMA_HTX0Lc_11HE 0x006f
#define HC_SIMA_HTX0L0OS 0x0070
#define HC_SIMA_HTX0TB 0x0071
#define HC_SIMA_HTX0MPMD 0x0072
#define HC_SIMA_HTX0CLODu 0x0073
#define HC_SIMA_HTX0FM 0x0074
#define HC_SIMA_HTX0TRCH 0x0075
#define HC_SIMA_HTX0TRCL 0
NV_WRITE(NV10_PGRAPH_RDI_INDEX, rdi_index);
for (i = 0; i < writecount; i++)
NV_WRITE(NV10_PGRAPH_RDI_DATA, 0);
nouveau_wait_for_idle(dev);
}
int nv20_graph_init(struct drm_device *dev) {
struct drm_nouveau_private *dev_priv =
(struct drm_nouveau_private *)dev->dev_private;
uint32_t tmp, vramsz;
int ret, i;
NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
~NV_PMC_ENABLE_PGRAPH);
NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
NV_PMC_ENABLE_PGRAPH);
if (!dev_priv->ctx_table) {
/* Create Context Pointer Table */
dev_priv->ctx_table_size = 32 * 4;
if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0,
dev_priv->ctx_table_size, 16,
NVOBJ_FLAG_ZERO_ALLOC,
&dev_priv->ctx_table)))
return ret;
}
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE,
dev_priv->ctx_table->instance >> 4
#define HC_SIMA_HTX1L9abBasH (HC_SIMA_HTX0L9abBasH + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LcdeBasH (HC_SIMA_HTX0LcdeBasH + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1Lf1011BasH (HC_SIMA_HTX0Lf1011BasH + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L0Pit (HC_SIMA_HTX0L0Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L1Pit (HC_SIMA_HTX0L1Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L2Pit (HC_SIMA_HTX0L2Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L3Pit (HC_SIMA_HTX0L3Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L4Pit (HC_SIMA_HTX0L4Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L5Pit (HC_SIMA_HTX0L5Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L6Pit (HC_SIMA_HTX0L6Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L7Pit (HC_SIMA_HTX0L7Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L8Pit (HC_SIMA_HTX0L8Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L9Pit (HC_SIMA_HTX0L9Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LaPit (HC_SIMA_HTX0LaPit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LbPit (HC_SIMA_HTX0LbPit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LcPit (HC_SIMA_HTX0LcPit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LdPit (HC_SIMA_HTX0LdPit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LePit (HC_SIMA_HTX0LePit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LfPit (HC_SIMA_HTX0LfPit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L10Pit (HC_SIMA_HTX0L10Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L11Pit (HC_SIMA_HTX0L11Pit + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L0_5WE (HC_SIMA_HTX0L0_5WE + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L6_bWE (HC_SIMA_HTX0L6_bWE + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1Lc_11WE (HC_SIMA_HTX0Lc_11WE + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L0_5HE (HC_SIMA_HTX0L0_5HE + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L6_bHE (HC_SIMA_HTX0L6_bHE + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1Lc_11HE (HC_SIMA_HTX0Lc_11HE + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1L0OS (HC_SIMA_HTX0L0OS + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1TB (HC_SIMA_HTX0TB + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1MPMD (HC_SIMA_HTX0MPMD + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1CLODu (HC_SIMA_HTX0CLODu + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1FM (HC_SIMA_HTX0FM + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1TRCH (HC_SIMA_HTX0TRCH + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1TRCL (HC_SIMA_HTX0TRCL + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1TBC (HC_SIMA_HTX0TBC + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1TRAH (HC_SIMA_HTX0TRAH + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LTC (HC_SIMA_HTX0LTC + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LTA (HC_SIMA_HTX0LTA + HC_SIMA_TX0TX1_OFF)
#define HC_SIM
NV_WRITE(0x400B84, 0x24000000);
NV_WRITE(0x400098, 0x00000040);
NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038);
NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
#define HC_SIMA_HTX1TBLRAa (HC_SIMA_HTX0TBLRAa + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1TBLRFog (HC_SIMA_HTX0TBLRFog + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1BumpM00 (HC_SIMA_HTX0BumpM00 + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1BumpM01 (HC_SIMA_HTX0BumpM01 + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1BumpM10 (HC_SIMA_HTX0BumpM10 + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1BumpM11 (HC_SIMA_HTX0BumpM11 + HC_SIMA_TX0TX1_OFF)
#define HC_SIMA_HTX1LScale (HC_SIMA_HTX0LScale + HC_SIMA_TX0TX1_OFF)
/*---- end of texture 1 setting ---- 0xaf
*/
#define HC_SIMA_HTXSMD 0x00b0
#define HC_SIMA_HenFIFOAT 0x00b1
#define HC_SIMA_HFBDrawFirst 0x00b2
#define HC_SIMA_HFBBasL 0x00b3
#define HC_SIMA_HTArbRCM 0x00b4
#define HC_SIMA_HTArbRZ 0x00b5
#define HC_SIMA_HTArbWZ 0x00b6
#define HC_SIMA_HTArbRTX 0x00b7
#define HC_SIMA_HTArbRCW 0x00b8
#define HC_SIMA_HTArbE2 0x00b9
#define HC_SIMA_HGEMITout 0x00ba
#define HC_SIMA_HFthRTXD 0x00bb
#define HC_SIMA_HFthRTXA 0x00bc
/* Define the texture palette 0
*/
#define HC_SIMA_HTP0 0x0100
#define HC_SIMA_HTP1 0x0200
#define HC_SIMA_FOGTABLE 0x0300
#define HC_SIMA_STIPPLE 0x0400
#define HC_SIMA_HE3Fire 0x0440
#define HC_SIMA_TRANS_SET 0x0441
#define HC_SIMA_HREngSt 0x0442
#define HC_SIMA_HRFIFOempty 0x0443
#define HC_SIMA_HRFIFOfull 0x0444
#define HC_SIMA_HRErr 0x0445
#define HC_SIMA_FIFOstatus 0x0446
/******************************************************************************
** Define the AGP command header.
******************************************************************************/
#define HC_ACMD_MASK 0xfe000000
#define HC_ACMD_SUB_MASK 0x0c000000
#define HC_ACMD_HCmdA 0xee000000
#define HC_ACMD_HCmdB 0xec000000
#define HC_ACMD_HCmdC 0xea000000
#
/* which is NV40_PGRAPH_TILE0(i) ?? */
NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0010+i*4);
NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TILE(i)));
}
#define HC_ACMD_H3COUNT_MASK 0x01fff000
#define HC_ACMD_H3COUNT_SHIFT 12
#define HC_ACMD_H4ID_MASK 0x000001ff
#define HC_ACMD_H4COUNT_MASK 0x01fffe00
#define HC_ACMD_H4COUNT_SHIFT 9
/********************************************************************************
** Define Header
********************************************************************************/
#define HC_HEADER2 0xF210F110
/********************************************************************************
** Define Dummy Value
********************************************************************************/
#define HC_DUMMY 0xCCCCCCCC
/********************************************************************************
** Define for DMA use
********************************************************************************/
#define HALCYON_HEADER2 0XF210F110
#define HALCYON_FIRECMD 0XEE100000
#define HALCYON_FIREMASK 0XFFF00000
#define HALCYON_CMDB 0XEC000000
#define HALCYON_CMDBMASK 0XFFFE0000
#define HALCYON_SUB_ADDR0 0X00000000
#define HALCYON_HEADER1MASK 0XFFFFFC00
#define HALCYON_HEADER1 0XF0000000
#define HC_SubA_HAGPBstL 0x0060
#define HC_SubA_HAGPBendL 0x0061
#define HC_SubA_HAGPCMNT 0x0062
#define HC_SubA_HAGPBpL 0x0063
#define HC_SubA_HAGPBpH 0x0064
#define HC_HAGPCMNT_MASK 0x00800000
#define HC_HCmdErrClr_MASK 0x00400000
#define HC_HAGPBendH_MASK 0x0000ff00
#define HC_HAGPBstH_MASK 0x000000ff
#define HC_HAGPBendH_SHIFT 8
#define HC_HAGPBstH_SHIFT 0
#define HC_HAGPBpL_MASK 0x00fffffc
#define HC_HAGPBpID_MASK 0x00000003
#define HC_HAGPBpID_PAUSE 0x00000000
#define HC_HAGPBpID_JUMP 0x00000001
#define HC_HAGPBpID_STOP 0x00000002
#define HC_HAGPBpH_MASK 0x00ffffff
#define VIA_VIDEO_HEADER5 0xFE040000
#define VIA_VIDEO_HEADER6 0xFE050000
#define VIA_VIDEO_HEADER7 0xFE060000
#define VIA_VIDEOMASK 0xFFFF0000
#endif
|
