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/*
 * Copyright (C) 2007 Arthur Huillet.
 *
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

/*
 * Authors:
 *   Arthur Huillet <arthur.huillet AT free DOT fr>
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drm.h"
#include "nouveau_drv.h"
#include "nouveau_reg.h"

/*TODO: add a "card_type" attribute*/
typedef struct{
	uint32_t oclass; /* object class for this software method */
	uint32_t mthd; /* method number */
	void (*method_code)(struct drm_device *dev, uint32_t oclass, uint32_t mthd); /* pointer to the function that does the work */
 } nouveau_software_method_t;


 /* This function handles the NV04 setcontext software methods.
One function for all because they are very similar.*/
static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t oclass, uint32_t mthd) {
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t inst_loc = NV_READ(NV04_PGRAPH_CTX_SWITCH4) & 0xFFFF;
	uint32_t value_to_set = 0, bit_to_set = 0;

	switch ( oclass ) {
		case 0x4a:
			switch ( mthd ) {
				case 0x188 :
				case 0x18c :
					bit_to_set = 0;
					break;
				case 0x198 :
					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
					break;
				case 0x2fc :
					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
					break;
				default : ;
				};
			break;
		case 0x5c:
			switch ( mthd ) {
				case 0x184:
					bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/
					break;
				case 0x188:
				case 0x18c:
					bit_to_set = 0;
					break;
				case 0x198:
					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
					break;
				case 0x2fc :
					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
					break;
			};
			break;
		case 0x5f:
			switch ( mthd ) {
				case 0x184 :
					bit_to_set = 1 << 12; /*CHROMA_KEY_ENABLE*/
					break;
				case 0x188 :
					bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/
					break;
				case 0x18c :
				case 0x190 :
					bit_to_set = 0;
					break;
				case 0x19c :
					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
					break;
				case 0x2fc :
					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
					break;
			};
			break;
		case 0x61:
			switch ( mthd ) {
				case 0x188 :
					bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/
					break;
				case 0x18c :
				case 0x190 :
					bit_to_set = 0;
					break;
				case 0x19c :
					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
					break;
				case 0x2fc :
					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
					break;
			};
			break;
		case 0x77:
			switch ( mthd ) {
				case 0x198 :
					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
					break;
				case 0x304 :
					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; //PATCH_CONFIG
					break;
			};
			break;
		default :;
		};

	value_to_set = (NV_READ(0x00700000 | inst_loc << 4))| bit_to_set;

	/*RAMIN*/
	nouveau_wait_for_idle(dev);
	NV_WRITE(0x00700000 | inst_loc << 4, value_to_set);

	/*DRM_DEBUG("CTX_SWITCH1 value is %#x\n", NV_READ(NV04_PGRAPH_CTX_SWITCH1));*/
	NV_WRITE(NV04_PGRAPH_CTX_SWITCH1, value_to_set);

	/*DRM_DEBUG("CTX_CACHE1 + xxx value is %#x\n", NV_READ(NV04_PGRAPH_CTX_CACHE1 + (((NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2)));*/
	NV_WRITE(NV04_PGRAPH_CTX_CACHE1 + (((NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2), value_to_set);
}

 nouveau_software_method_t nouveau_sw_methods[] = {
	/*NV04 context software methods*/
	{ 0x4a, 0x188, nouveau_NV04_setcontext_sw_method },
	{ 0x4a, 0x18c, nouveau_NV04_setcontext_sw_method },
	{ 0x4a, 0x198, nouveau_NV04_setcontext_sw_method },
	{ 0x4a, 0x2fc, nouveau_NV04_setcontext_sw_method },
	{ 0x5c, 0x184, nouveau_NV04_setcontext_sw_method },
	{ 0x5c, 0x188, nouveau_NV04_setcontext_sw_method },
	{ 0x5c, 0x18c, nouveau_NV04_setcontext_sw_method },
	{ 0x5c, 0x198, nouveau_NV04_setcontext_sw_method },
	{ 0x5c, 0x2fc, nouveau_NV04_setcontext_sw_method },
	{ 0x5f, 0x184, nouveau_NV04_setcontext_sw_method },
	{ 0x5f, 0x188, nouveau_NV04_setcontext_sw_method },
	{ 0x5f, 0x18c, nouveau_NV04_setcontext_sw_method },
	{ 0x5f, 0x190, nouveau_NV04_setcontext_sw_method },
	{ 0x5f, 0x19c, nouveau_NV04_setcontext_sw_method },
	{ 0x5f, 0x2fc, nouveau_NV04_setcontext_sw_method },
	{ 0x61, 0x188, nouveau_NV04_setcontext_sw_method },
	{ 0x61, 0x18c, nouveau_NV04_setcontext_sw_method },
	{ 0x61, 0x190, nouveau_NV04_setcontext_sw_method },
	{ 0x61, 0x19c, nouveau_NV04_setcontext_sw_method },
	{ 0x61, 0x2fc, nouveau_NV04_setcontext_sw_method },
	{ 0x77, 0x198, nouveau_NV04_setcontext_sw_method },
	{ 0x77, 0x304, nouveau_NV04_setcontext_sw_method },
	/*terminator*/
	{ 0x0, 0x0, NULL, },
 };

 int nouveau_sw_method_execute(struct drm_device *dev, uint32_t oclass, uint32_t method) {
	int i = 0;
	while ( nouveau_sw_methods[ i ] . method_code != NULL )
		{
		if ( nouveau_sw_methods[ i ] . oclass == oclass && nouveau_sw_methods[ i ] . mthd == method )
			{
			nouveau_sw_methods[ i ] . method_code(dev, oclass, method);
			return 0;
			}
		i ++;
		}

	 return 1;
 }


hl opt">)+1, 0x00000000); } pte++; } nvbe->is_bound = 0; } return 0; } static void nouveau_sgdma_destroy(struct drm_ttm_backend *be) { DRM_DEBUG("\n"); if (be) { struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be; if (nvbe) { if (nvbe->pagelist) be->func->clear(be); drm_ctl_free(nvbe, sizeof(*nvbe), DRM_MEM_TTM); } } } static struct drm_ttm_backend_func nouveau_sgdma_backend = { .needs_ub_cache_adjust = nouveau_sgdma_needs_ub_cache_adjust, .populate = nouveau_sgdma_populate, .clear = nouveau_sgdma_clear, .bind = nouveau_sgdma_bind, .unbind = nouveau_sgdma_unbind, .destroy = nouveau_sgdma_destroy }; struct drm_ttm_backend * nouveau_sgdma_init_ttm(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_sgdma_be *nvbe; if (!dev_priv->gart_info.sg_ctxdma) return NULL; nvbe = drm_ctl_calloc(1, sizeof(*nvbe), DRM_MEM_TTM); if (!nvbe) return NULL; nvbe->dev = dev; nvbe->backend.func = &nouveau_sgdma_backend; return &nvbe->backend; } int nouveau_sgdma_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *gpuobj = NULL; uint32_t aper_size, obj_size; int i, ret; if (dev_priv->card_type < NV_50) { aper_size = (64 * 1024 * 1024); obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 4; obj_size += 8; /* ctxdma header */ } else { /* 1 entire VM page table */ aper_size = (512 * 1024 * 1024); obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 8; } if ((ret = nouveau_gpuobj_new(dev, NULL, obj_size, 16, NVOBJ_FLAG_ALLOW_NO_REFS | NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &gpuobj))) { DRM_ERROR("Error creating sgdma object: %d\n", ret); return ret; } dev_priv->gart_info.sg_dummy_page = alloc_page(GFP_KERNEL|__GFP_DMA32); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) set_page_locked(dev_priv->gart_info.sg_dummy_page); #else SetPageLocked(dev_priv->gart_info.sg_dummy_page); #endif dev_priv->gart_info.sg_dummy_bus = pci_map_page(dev->pdev, dev_priv->gart_info.sg_dummy_page, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); if (dev_priv->card_type < NV_50) { /* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and * confirmed to work on c51. Perhaps means NV_DMA_TARGET_PCIE * on those cards? */ INSTANCE_WR(gpuobj, 0, NV_CLASS_DMA_IN_MEMORY | (1 << 12) /* PT present */ | (0 << 13) /* PT *not* linear */ | (NV_DMA_ACCESS_RW << 14) | (NV_DMA_TARGET_PCI << 16)); INSTANCE_WR(gpuobj, 1, aper_size - 1); for (i=2; i<2+(aper_size>>12); i++) { INSTANCE_WR(gpuobj, i, dev_priv->gart_info.sg_dummy_bus | 3); } } else { for (i=0; i<obj_size; i+=8) { INSTANCE_WR(gpuobj, (i+0)/4, dev_priv->gart_info.sg_dummy_bus | 0x21); INSTANCE_WR(gpuobj, (i+4)/4, 0); } } dev_priv->gart_info.type = NOUVEAU_GART_SGDMA; dev_priv->gart_info.aper_base = 0; dev_priv->gart_info.aper_size = aper_size; dev_priv->gart_info.sg_ctxdma = gpuobj; return 0; } void nouveau_sgdma_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; if (dev_priv->gart_info.sg_dummy_page) { pci_unmap_page(dev->pdev, dev_priv->gart_info.sg_dummy_bus, NV_CTXDMA_PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); unlock_page(dev_priv->gart_info.sg_dummy_page); __free_page(dev_priv->gart_info.sg_dummy_page); dev_priv->gart_info.sg_dummy_page = NULL; dev_priv->gart_info.sg_dummy_bus = 0; } nouveau_gpuobj_del(dev, &dev_priv->gart_info.sg_ctxdma); } int nouveau_sgdma_nottm_hack_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_ttm_backend *be; struct drm_scatter_gather sgreq; struct drm_mm_node mm_node; struct drm_bo_mem_reg mem; int ret; dev_priv->gart_info.sg_be = nouveau_sgdma_init_ttm(dev); if (!dev_priv->gart_info.sg_be) return -ENOMEM; be = dev_priv->gart_info.sg_be; /* Hack the aperture size down to the amount of system memory * we're going to bind into it. */ if (dev_priv->gart_info.aper_size > 32*1024*1024) dev_priv->gart_info.aper_size = 32*1024*1024; sgreq.size = dev_priv->gart_info.aper_size; if ((ret = drm_sg_alloc(dev, &sgreq))) { DRM_ERROR("drm_sg_alloc failed: %d\n", ret); return ret; } dev_priv->gart_info.sg_handle = sgreq.handle; if ((ret = be->func->populate(be, dev->sg->pages, dev->sg->pagelist, dev->bm.dummy_read_page))) { DRM_ERROR("failed populate: %d\n", ret); return ret; } mm_node.start = 0; mem.mm_node = &mm_node; if ((ret = be->func->bind(be, &mem))) { DRM_ERROR("failed bind: %d\n", ret); return ret; } return 0; } void nouveau_sgdma_nottm_hack_takedown(struct drm_device *dev) { } int nouveau_sgdma_get_page(struct drm_device *dev, uint32_t offset, uint32_t *page) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma; int pte; pte = (offset >> NV_CTXDMA_PAGE_SHIFT); if (dev_priv->card_type < NV_50) { *page = INSTANCE_RD(gpuobj, (pte + 2)) & ~NV_CTXDMA_PAGE_MASK; return 0; } DRM_ERROR("Unimplemented on NV50\n"); return -EINVAL; }