/* $Id$ * ffb_drv.c: Creator/Creator3D direct rendering driver. * * Copyright (C) 2000 David S. Miller (davem@redhat.com) */ #include #include #include #include #include #include "drmP.h" #include "ffb_drv.h" #define DRIVER_AUTHOR "David S. Miller" #define DRIVER_NAME "ffb" #define DRIVER_DESC "Creator/Creator3D" #define DRIVER_DATE "20000517" #define DRIVER_MAJOR 0 #define DRIVER_MINOR 0 #define DRIVER_PATCHLEVEL 1 typedef struct _ffb_position_t { int node; int root; } ffb_position_t; static ffb_position_t *ffb_position; static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance) { volatile unsigned char *strap_bits; unsigned char val; strap_bits = (volatile unsigned char *) (ffb_priv->card_phys_base + 0x00200000UL); /* Don't ask, you have to read the value twice for whatever * reason to get correct contents. */ val = upa_readb(strap_bits); val = upa_readb(strap_bits); switch (val & 0x78) { case (0x0 << 5) | (0x0 << 3): ffb_priv->ffb_type = ffb1_prototype; printk("ffb%d: Detected FFB1 pre-FCS prototype\n", instance); break; case (0x0 << 5) | (0x1 << 3): ffb_priv->ffb_type = ffb1_standard; printk("ffb%d: Detected FFB1\n", instance); break; case (0x0 << 5) | (0x3 << 3): ffb_priv->ffb_type = ffb1_speedsort; printk("ffb%d: Detected FFB1-SpeedSort\n", instance); break; case (0x1 << 5) | (0x0 << 3): ffb_priv->ffb_type = ffb2_prototype; printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n", instance); break; case (0x1 << 5) | (0x1 << 3): ffb_priv->ffb_type = ffb2_vertical; printk("ffb%d: Detected FFB2/vertical\n", instance); break; case (0x1 << 5) | (0x2 << 3): ffb_priv->ffb_type = ffb2_vertical_plus; printk("ffb%d: Detected FFB2+/vertical\n", instance); break; case (0x2 << 5) | (0x0 << 3): ffb_priv->ffb_type = ffb2_horizontal; printk("ffb%d: Detected FFB2/horizontal\n", instance); break; case (0x2 << 5) | (0x2 << 3): ffb_priv->ffb_type = ffb2_horizontal; printk("ffb%d: Detected FFB2+/horizontal\n", instance); break; default: ffb_priv->ffb_type = ffb2_vertical; printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n", instance, val); break; }; } static void ffb_apply_upa_parent_ranges(int parent, struct linux_prom64_registers *regs) { struct linux_prom64_ranges ranges[PROMREG_MAX]; char name[128]; int len, i; prom_getproperty(parent, "name", name, sizeof(name)); if (strcmp(name, "upa") != 0) return; len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges)); if (len <= 0) return; len /= sizeof(struct linux_prom64_ranges); for (i = 0; i < len; i++) { struct linux_prom64_ranges *rng = &ranges[i]; u64 phys_addr = regs->phys_addr; if (phys_addr >= rng->ot_child_base && phys_addr < (rng->ot_child_base + rng->or_size)) { regs->phys_addr -= rng->ot_child_base; regs->phys_addr += rng->ot_parent_base; return; } } return; } static int ffb_init_one(struct drm_device *dev, int prom_node, int parent_node, int instance) { struct linux_prom64_registers regs[2*PROMREG_MAX]; ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; int i; ffb_priv->prom_node = prom_node; if (prom_getproperty(ffb_priv->prom_node, "reg", (void *)regs, sizeof(regs)) <= 0) { return -EINVAL; } ffb_apply_upa_parent_ranges(parent_node, ®s[0]); ffb_priv->card_phys_base = regs[0].phys_addr; ffb_priv->regs = (ffb_fbcPtr) (regs[0].phys_addr + 0x00600000UL); get_ffb_type(ffb_priv, instance); for (i = 0; i < FFB_MAX_CTXS; i++) ffb_priv->hw_state[i] = NULL; return 0; } static int __init ffb_count_siblings(int root) { int node, child, count = 0; child = prom_getchild(root); for (node = prom_searchsiblings(child, "SUNW,ffb"); node; node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb")) count++; return count; } static int __init ffb_scan_siblings(int root, int instance) { int node, child; child = prom_getchild(root); for (node = prom_searchsiblings(child, "SUNW,ffb"); node; node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb")) { ffb_position[instance].node = node; ffb_position[instance].root = root; instance++; } return instance; } static drm_map_t *ffb_find_map(struct file *filp, unsigned long off) { drm_file_t *priv = filp->private_data; struct drm_device *dev; drm_map_list_t *r_list; struct list_head *list; drm_map_t *map; if (!priv || (dev = priv->dev) == NULL) return NULL; list_for_each(list, &dev->maplist->head) { unsigned long uoff; r_list = (drm_map_list_t *)list; map = r_list->map; if (!map) continue; uoff = (map->offset & 0xffffffff); if (uoff == off) return map; } return NULL; } unsigned long ffb_get_unmapped_area(struct file *filp, unsigned long hint, unsigned long len, unsigned long pgoff, unsigned long flags) { drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT); unsigned long addr = -ENOMEM; if (!map) return get_unmapped_area(NULL, hint, len, pgoff, flags); if (map->type == _DRM_FRAME_BUFFER || map->type == _DRM_REGISTERS) { #ifdef HAVE_ARCH_FB_UNMAPPED_AREA addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags); #else addr = get_unmapped_area(NULL, hint, len, pgoff, flags); #endif } else if (map->type == _DRM_SHM && SHMLBA > PAGE_SIZE) { unsigned long slack = SHMLBA - PAGE_SIZE; addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags); if (!(addr & ~PAGE_MASK)) { unsigned long kvirt = (unsigned long) map->handle; if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) { unsigned long koff, aoff; koff = kvirt & (SHMLBA - 1); aoff = addr & (SHMLBA - 1); if (koff < aoff) koff += SHMLBA; addr += (koff - aoff); } } } else { addr = get_unmapped_area(NULL, hint, len, pgoff, flags); } return addr; } /* This functions must be here since it references drm_numdevs) * which drm_drv.h declares. */ static int ffb_driver_firstopen(struct drm_device *dev) { ffb_dev_priv_t *ffb_priv; struct drm_device *temp_dev; int ret = 0; int i; /* Check for the case where no device was found. */ if (ffb_position == NULL) return -ENODEV; /* Find our instance number by finding our device in dev structure */ for (i = 0; i < drm_numdevs; i++) { temp_dev = &(drm_device[i]); if(temp_dev == dev) break; } if (i == drm_numdevs) return -ENODEV; ffb_priv = kmalloc(sizeof(ffb_dev_priv_t), GFP_KERNEL); if (!ffb_priv) return -ENOMEM; memset(ffb_priv, 0, sizeof(*ffb_priv)); dev->dev_private = ffb_priv; ret = ffb_init_one(dev, ffb_position[i].node, ffb_position[i].root, i); return ret; } #include "drm_pciids.h" static struct pci_device_id pciidlist[] = { ffb_PCI_IDS }; static struct drm_driver ffb_driver = { .release = ffb_driver_reclaim_buffers_locked, .firstopen = ffb_driver_firstopen, .lastclose = ffb_driver_lastclose, .unload = ffb_driver_unload, .kernel_context_switch = ffb_context_switch, .kernel_context_switch_unlock = ffb_driver_kernel_context_switch_unlock, .get_map_ofs = ffb_driver_get_map_ofs, .get_reg_ofs = ffb_driver_get_reg_ofs, .reclaim_buffers = drm_core_reclaim_buffers, fops = { .owner = THIS_MODULE, .open = drm_open, .release = drm_release, .ioctl = drm_ioctl, .mmap = drm_mmap, .fasync = drm_fasync, .poll = drm_poll, .get_unmapped_area = ffb_get_unmapped_area, }, }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) { return drm_probe(pdev, ent, &driver); } static struct pci_driver pci_driver = { .name = DRIVER_NAME, .id_table = pciidlist, .probe = probe, .remove = __devexit_p(drm_cleanup_pci), }; static int __init ffb_init(void) { return drm_init(&pci_driver, pciidlist, &driver); } static void __exit ffb_exit(void) { drm_exit(&pci_driver); } module_init(ffb_init); module_exit(ffb_exit)); MODULE_AUTHOR( DRIVER_AUTHOR ); MODULE_DESCRIPTION( DRIVER_DESC ); MODULE_LICENSE("GPL and additional rights"); 58'>158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 
/*
 * Copyright (C) 2006 Ben Skeggs.
 *
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

/*
 * Authors:
 *   Ben Skeggs <darktama@iinet.net.au>
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drm.h"
#include "nouveau_drv.h"
#include "nouveau_reg.h"
#include "nouveau_swmthd.h"

/* needed for interrupt based vpll changes */
#include "nv50_display.h"
#include "nv50_crtc.h"
#include "nv50_output.h"

void
nouveau_irq_preinstall(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* Master disable */
	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
}

int
nouveau_irq_postinstall(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* Master enable */
	NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);

	return 0;
}

void
nouveau_irq_uninstall(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* Master disable */
	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
}

static void
nouveau_fifo_irq_handler(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	uint32_t status, reassign;

	reassign = NV_READ(NV03_PFIFO_CACHES) & 1;
	while ((status = NV_READ(NV03_PFIFO_INTR_0))) {
		uint32_t chid, get;

		NV_WRITE(NV03_PFIFO_CACHES, 0);

		chid = engine->fifo.channel_id(dev);
		get  = NV_READ(NV03_PFIFO_CACHE1_GET);

		if (status & NV_PFIFO_INTR_CACHE_ERROR) {
			uint32_t mthd, data;
			int ptr;

			ptr = get >> 2;
			if (dev_priv->card_type < NV_40) {
				mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr));
				data = NV_READ(NV04_PFIFO_CACHE1_DATA(ptr));
			} else {
				mthd = NV_READ(NV40_PFIFO_CACHE1_METHOD(ptr));
				data = NV_READ(NV40_PFIFO_CACHE1_DATA(ptr));
			}

			DRM_INFO("PFIFO_CACHE_ERROR - "
				 "Ch %d/%d Mthd 0x%04x Data 0x%08x\n",
				 chid, (mthd >> 13) & 7, mthd & 0x1ffc, data);

			NV_WRITE(NV03_PFIFO_CACHE1_GET, get + 4);
			NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 1);

			status &= ~NV_PFIFO_INTR_CACHE_ERROR;
			NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
		}

		if (status & NV_PFIFO_INTR_DMA_PUSHER) {
			DRM_INFO("PFIFO_DMA_PUSHER - Ch %d\n", chid);

			status &= ~NV_PFIFO_INTR_DMA_PUSHER;
			NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);

			NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
			if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT) != get)
				NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, get + 4);
		}

		if (status) {
			DRM_INFO("Unhandled PFIFO_INTR - 0x%08x\n", status);
			NV_WRITE(NV03_PFIFO_INTR_0, status);
			NV_WRITE(NV03_PMC_INTR_EN_0, 0);
		}

		NV_WRITE(NV03_PFIFO_CACHES, reassign);
	}

	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
}

struct nouveau_bitfield_names {
	uint32_t mask;
	const char * name;
};

static struct nouveau_bitfield_names nouveau_nstatus_names[] =
{
	{ NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
	{ NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
	{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
	{ NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
};

static struct nouveau_bitfield_names nouveau_nstatus_names_nv10[] =
{
	{ NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
	{ NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
	{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
	{ NV10_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
};

static struct nouveau_bitfield_names nouveau_nsource_names[] =
{
	{ NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
	{ NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
	{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
	{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
	{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
	{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
	{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
	{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
	{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
	{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
	{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
	{ NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
	{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
	{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
	{ NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
	{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
	{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
	{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
	{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
};

static void
nouveau_print_bitfield_names(uint32_t value,
                             const struct nouveau_bitfield_names *namelist,
                             const int namelist_len)
{
	int i;
	for(i=0; i<namelist_len; ++i) {
		uint32_t mask = namelist[i].mask;
		if(value & mask) {
			printk(" %s", namelist[i].name);
			value &= ~mask;
		}
	}
	if(value)
		printk(" (unknown bits 0x%08x)", value);
}

static int
nouveau_graph_chid_from_grctx(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t inst;
	int i;

	if (dev_priv->card_type < NV_40)
		return dev_priv->Engine.fifo.channels;
	else
	if (dev_priv->card_type < NV_50)
		inst = (NV_READ(0x40032c) & 0xfffff) << 4;
	else
		inst = NV_READ(0x40032c) & 0xfffff;

	for (i = 0; i < dev_priv->Engine.fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->fifos[i];

		if (!chan || !chan->ramin_grctx)
			continue;

		if (dev_priv->card_type < NV_50) {
			if (inst == chan->ramin_grctx->instance)
				break;
		} else {
			if (inst == INSTANCE_RD(chan->ramin_grctx->gpuobj, 0))
				break;
		}
	}

	return i;
}

static int
nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	int channel;

	if (dev_priv->card_type < NV_10)
		channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
	else
	if (dev_priv->card_type < NV_40)
		channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
	else
		channel = nouveau_graph_chid_from_grctx(dev);

	if (channel >= engine->fifo.channels || !dev_priv->fifos[channel]) {
		DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
		return -EINVAL;
	}

	*channel_ret = channel;
	return 0;
}

struct nouveau_pgraph_trap {
	int channel;
	int class;
	int subc, mthd, size;
	uint32_t data, data2;
	uint32_t nsource, nstatus;
};

static void
nouveau_graph_trap_info(struct drm_device *dev,
			struct nouveau_pgraph_trap *trap)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t address;

	trap->nsource = trap->nstatus = 0;
	if (dev_priv->card_type < NV_50) {
		trap->nsource = NV_READ(NV03_PGRAPH_NSOURCE);
		trap->nstatus = NV_READ(NV03_PGRAPH_NSTATUS);
	}

	if (nouveau_graph_trapped_channel(dev, &trap->channel))
		trap->channel = -1;
	address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);

	trap->mthd = address & 0x1FFC;
	trap->data = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
	if (dev_priv->card_type < NV_10) {
		trap->subc  = (address >> 13) & 0x7;
	} else {
		trap->subc  = (address >> 16) & 0x7;
		trap->data2 = NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
	}

	if (dev_priv->card_type < NV_10) {
		trap->class = NV_READ(0x400180 + trap->subc*4) & 0xFF;
	} else if (dev_priv->card_type < NV_40) {
		trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFF;
	} else if (dev_priv->card_type < NV_50) {
		trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFFF;
	} else {
		trap->class = NV_READ(0x400814);
	}
}

static void
nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
			     struct nouveau_pgraph_trap *trap)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t nsource = trap->nsource, nstatus = trap->nstatus;

	DRM_INFO("%s - nSource:", id);
	nouveau_print_bitfield_names(nsource, nouveau_nsource_names,
	                             ARRAY_SIZE(nouveau_nsource_names));
	printk(", nStatus:");
	if (dev_priv->card_type < NV_10)
		nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names,
	                             ARRAY_SIZE(nouveau_nstatus_names));
	else
		nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names_nv10,
	                             ARRAY_SIZE(nouveau_nstatus_names_nv10));
	printk("\n");

	DRM_INFO("%s - Ch %d/%d Class 0x%04x Mthd 0x%04x Data 0x%08x:0x%08x\n",
		 id, trap->channel, trap->subc, trap->class, trap->mthd,
		 trap->data2, trap->data);
}

static inline void
nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
{
	struct nouveau_pgraph_trap trap;
	int unhandled = 0;

	nouveau_graph_trap_info(dev, &trap);

	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
		/* NV4 (nvidia TNT 1) reports software methods with
		 * PGRAPH NOTIFY ILLEGAL_MTHD
		 */
		DRM_DEBUG("Got NV04 software method method %x for class %#x\n",
			  trap.mthd, trap.class);

		if (nouveau_sw_method_execute(dev, trap.class, trap.mthd)) {
			DRM_ERROR("Unable to execute NV04 software method %x "
				  "for object class %x. Please report.\n",
				  trap.mthd, trap.class);
			unhandled = 1;
		}
	} else {
		unhandled = 1;
	}

	if (unhandled)
		nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
}

static inline void
nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
{
	struct nouveau_pgraph_trap trap;
	int unhandled = 0;

	nouveau_graph_trap_info(dev, &trap);
	trap.nsource = nsource;

	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
		if (trap.channel >= 0 && trap.mthd == 0x0150) {
			nouveau_fence_handler(dev, trap.channel);
		} else
		if (nouveau_sw_method_execute(dev, trap.class, trap.mthd)) {
			unhandled = 1;
		}
	} else {
		unhandled = 1;
	}

	if (unhandled)
		nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap);
}

static inline void
nouveau_pgraph_intr_context_switch(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	uint32_t chid;

	chid = engine->fifo.channel_id(dev);
	DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid);

	switch(dev_priv->card_type) {
	case NV_04:
	case NV_05:
		nouveau_nv04_context_switch(dev);
		break;
	case NV_10:
	case NV_11:
	case NV_17:
		nouveau_nv10_context_switch(dev);
		break;
	default:
		DRM_ERROR("Context switch not implemented\n");
		break;
	}
}

static void
nouveau_pgraph_irq_handler(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t status;

	while ((status = NV_READ(NV03_PGRAPH_INTR))) {
		uint32_t nsource = NV_READ(NV03_PGRAPH_NSOURCE);

		if (status & NV_PGRAPH_INTR_NOTIFY) {
			nouveau_pgraph_intr_notify(dev, nsource);

			status &= ~NV_PGRAPH_INTR_NOTIFY;
			NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
		}

		if (status & NV_PGRAPH_INTR_ERROR) {
			nouveau_pgraph_intr_error(dev, nsource);

			status &= ~NV_PGRAPH_INTR_ERROR;
			NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
		}

		if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
			nouveau_pgraph_intr_context_switch(dev);

			status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
			NV_WRITE(NV03_PGRAPH_INTR,
				 NV_PGRAPH_INTR_CONTEXT_SWITCH);
		}

		if (status) {
			DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status);
			NV_WRITE(NV03_PGRAPH_INTR, status);
		}

		if ((NV_READ(NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
			NV_WRITE(NV04_PGRAPH_FIFO, 1);
	}

	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
}

static void
nv50_pgraph_irq_handler(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t status;

	status = NV_READ(NV03_PGRAPH_INTR);

	if (status & 0x00000020) {
		nouveau_pgraph_intr_error(dev,
					  NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD);

		status &= ~0x00000020;
		NV_WRITE(NV03_PGRAPH_INTR, 0x00000020);
	}

	if (status & 0x00100000) {
		nouveau_pgraph_intr_error(dev,
					  NV03_PGRAPH_NSOURCE_DATA_ERROR);

		status &= ~0x00100000;
		NV_WRITE(NV03_PGRAPH_INTR, 0x00100000);
	}

	if (status & 0x00200000) {
		nouveau_pgraph_intr_error(dev,
					  NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);

		status &= ~0x00200000;
		NV_WRITE(NV03_PGRAPH_INTR, 0x00200000);
	}

	if (status) {
		DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status);
		NV_WRITE(NV03_PGRAPH_INTR, status);
	}

	{
		const int isb = (1 << 16) | (1 << 0);

		if ((NV_READ(0x400500) & isb) != isb)
			NV_WRITE(0x400500, NV_READ(0x400500) | isb);
	}

	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
}

static void
nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (crtc&1) {
		NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
	}

	if (crtc&2) {
		NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
	}
}

static void
nouveau_nv50_display_irq_handler(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t val = NV_READ(NV50_PDISPLAY_SUPERVISOR);

	DRM_INFO("NV50_DISPLAY_INTR - 0x%08X\n", val);

	/* vblank interrupts */
	if (val & NV50_PDISPLAY_SUPERVISOR_CRTCn) {
		NV_WRITE(NV50_PDISPLAY_SUPERVISOR, val & NV50_PDISPLAY_SUPERVISOR_CRTCn);
		val &= ~NV50_PDISPLAY_SUPERVISOR_CRTCn;
	}

	/* clock setting amongst other things. */
	if (val & NV50_PDISPLAY_SUPERVISOR_CLK_MASK) {
		uint32_t state = (val & NV50_PDISPLAY_SUPERVISOR_CLK_MASK) >> NV50_PDISPLAY_SUPERVISOR_CLK_MASK__SHIFT;

		NV50_DEBUG("state %d\n", state);

		/* Set pll */
		if (state == 2) {
			struct nv50_display *display = nv50_get_display(dev);
			struct nv50_output *output = NULL;
			struct nv50_crtc *crtc = NULL;
			int crtc_index;

			uint32_t unk30 = NV_READ(NV50_PDISPLAY_UNK30_CTRL);

			for (crtc_index = 0; crtc_index < 2; crtc_index++) {
				bool clock_change = false;
				bool clock_ack = false;

				if (crtc_index == 0 && (unk30 & NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK0))
					clock_change = true;

				if (crtc_index == 1 && (unk30 & NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK1))
					clock_change = true;

				if (clock_change)
					clock_ack = true;

				if (display->last_crtc == crtc_index)
					clock_ack = true;

				list_for_each_entry(crtc, &display->crtcs, item) {
					if (crtc->index == crtc_index)
						break;
				}

				if (clock_change)
					crtc->set_clock(crtc);

				NV50_DEBUG("index %d clock_change %d clock_ack %d\n", crtc_index, clock_change, clock_ack);

				if (!clock_ack)
					continue;

				crtc->set_clock_mode(crtc);

				list_for_each_entry(output, &display->outputs, item) {
					if (!output->crtc)
						continue;

					if (output->crtc == crtc)
						output->set_clock_mode(output);
				}
			}
		}

		NV_WRITE(NV50_PDISPLAY_UNK30_CTRL, NV50_PDISPLAY_UNK30_CTRL_PENDING);
		NV_WRITE(NV50_PDISPLAY_SUPERVISOR, val & NV50_PDISPLAY_SUPERVISOR_CLK_MASK);

		val &= ~NV50_PDISPLAY_SUPERVISOR_CLK_MASK;
	}

	if (val)
		DRM_ERROR("unsupported NV50_DISPLAY_INTR - 0x%08X\n", val);

	NV_WRITE(NV50_PDISPLAY_SUPERVISOR, val);
}

static void
nouveau_nv50_i2c_irq_handler(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	DRM_INFO("NV50_I2C_INTR - 0x%08X\n", NV_READ(NV50_I2C_CONTROLLER));

	/* This seems to be the way to acknowledge an interrupt. */
	NV_WRITE(NV50_I2C_CONTROLLER, 0x7FFF7FFF);
}

irqreturn_t
nouveau_irq_handler(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device*)arg;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t status;

	status = NV_READ(NV03_PMC_INTR_0);
	if (!status)
		return IRQ_NONE;

	if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
		nouveau_fifo_irq_handler(dev);
		status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
	}

	if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
		if (dev_priv->card_type >= NV_50)
			nv50_pgraph_irq_handler(dev);
		else
			nouveau_pgraph_irq_handler(dev);

		status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
	}

	if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
		nouveau_crtc_irq_handler(dev, (status>>24)&3);
		status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
	}

	if (status & NV_PMC_INTR_0_NV50_DISPLAY_PENDING) {
		nouveau_nv50_display_irq_handler(dev);
		status &= ~NV_PMC_INTR_0_NV50_DISPLAY_PENDING;
	}

	if (status & NV_PMC_INTR_0_NV50_I2C_PENDING) {
		nouveau_nv50_i2c_irq_handler(dev);
		status &= ~NV_PMC_INTR_0_NV50_I2C_PENDING;
	}

	if (status)
		DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);

	return IRQ_HANDLED;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-20 17:33:04 +0000