/* drmP.h -- Private header for Direct Rendering Manager -*- linux-c -*- * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Rickard E. (Rik) Faith * Gareth Hughes * */ #ifndef _DRM_P_H_ #define _DRM_P_H_ #if defined(_KERNEL) || defined(__KERNEL__) typedef struct drm_device drm_device_t; typedef struct drm_file drm_file_t; #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(__FreeBSD__) #include #include #include #include #if __FreeBSD_version >= 500000 #include #include #include #else /* __FreeBSD_version >= 500000 */ #include #include #endif /* __FreeBSD_version < 500000 */ #elif defined(__NetBSD__) #include #include #include #include #include #include #include #include #include #include #include #include #elif defined(__OpenBSD__) #include #include #endif #include #include "drm.h" #include "drm_linux_list.h" #include "drm_atomic.h" #ifdef __FreeBSD__ #include #ifdef DRM_DEBUG #undef DRM_DEBUG #define DRM_DEBUG_DEFAULT_ON 1 #endif /* DRM_DEBUG */ #endif #if defined(DRM_LINUX) && DRM_LINUX && !defined(__amd64__) #include #include #include #include #else /* Either it was defined when it shouldn't be (FreeBSD amd64) or it isn't * supported on this OS yet. */ #undef DRM_LINUX #define DRM_LINUX 0 #endif #define DRM_HASH_SIZE 16 /* Size of key hash table */ #define DRM_KERNEL_CONTEXT 0 /* Change drm_resctx if changed */ #define DRM_RESERVED_CONTEXTS 1 /* Change drm_resctx if changed */ #define DRM_MEM_DMA 0 #define DRM_MEM_SAREA 1 #define DRM_MEM_DRIVER 2 #define DRM_MEM_MAGIC 3 #define DRM_MEM_IOCTLS 4 #define DRM_MEM_MAPS 5 #define DRM_MEM_BUFS 6 #define DRM_MEM_SEGS 7 #define DRM_MEM_PAGES 8 #define DRM_MEM_FILES 9 #define DRM_MEM_QUEUES 10 #define DRM_MEM_CMDS 11 #define DRM_MEM_MAPPINGS 12 #define DRM_MEM_BUFLISTS 13 #define DRM_MEM_AGPLISTS 14 #define DRM_MEM_TOTALAGP 15 #define DRM_MEM_BOUNDAGP 16 #define DRM_MEM_CTXBITMAP 17 #define DRM_MEM_STUB 18 #define DRM_MEM_SGLISTS 19 #define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8) /* Internal types and structures */ #define DRM_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) #define DRM_MIN(a,b) ((a)<(b)?(a):(b)) #define DRM_MAX(a,b) ((a)>(b)?(a):(b)) #define DRM_IF_VERSION(maj, min) (maj << 16 | min) MALLOC_DECLARE(M_DRM); #define __OS_HAS_AGP 1 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) #define DRM_DEV_UID 0 #define DRM_DEV_GID 0 #define wait_queue_head_t atomic_t #define DRM_WAKEUP(w) wakeup((void *)w) #define DRM_WAKEUP_INT(w) wakeup(w) #define DRM_INIT_WAITQUEUE(queue) do {} while (0) #if defined(__FreeBSD__) && __FreeBSD_version < 502109 #define bus_alloc_resource_any(dev, type, rid, flags) \ bus_alloc_resource(dev, type, rid, 0ul, ~0ul, 1, flags) #endif #if defined(__FreeBSD__) && __FreeBSD_version >= 500000 #define DRM_CURPROC curthread #define DRM_STRUCTPROC struct thread #define DRM_SPINTYPE struct mtx #define DRM_SPININIT(l,name) mtx_init(&l, name, NULL, MTX_DEF) #define DRM_SPINUNINIT(l) mtx_destroy(&l) #define DRM_SPINLOCK(l) mtx_lock(l) #define DRM_SPINUNLOCK(u) mtx_unlock(u); #define DRM_SPINLOCK_ASSERT(l) mtx_assert(l, MA_OWNED) #define DRM_CURRENTPID curthread->td_proc->p_pid #define DRM_LOCK() mtx_lock(&dev->dev_lock) #define DRM_UNLOCK() mtx_unlock(&dev->dev_lock) #define DRM_SYSCTL_HANDLER_ARGS (SYSCTL_HANDLER_ARGS) #else /* __FreeBSD__ && __FreeBSD_version >= 500000 */ #define DRM_CURPROC curproc #define DRM_STRUCTPROC struct proc #define DRM_SPINTYPE struct simplelock #define DRM_SPININIT(l,name) #define DRM_SPINUNINIT(l) #define DRM_SPINLOCK(l) #define DRM_SPINUNLOCK(u) #define DRM_SPINLOCK_ASSERT(l) #define DRM_CURRENTPID curproc->p_pid #define DRM_LOCK() #define DRM_UNLOCK() #define DRM_SYSCTL_HANDLER_ARGS SYSCTL_HANDLER_ARGS #define spldrm() spltty() #endif /* __NetBSD__ || __OpenBSD__ */ /* Currently our DRMFILE (filp) is a void * which is actually the pid * of the current process. It should be a per-open unique pointer, but * code for that is not yet written */ #define DRMFILE void * #define DRM_IRQ_ARGS void *arg typedef void irqreturn_t; #define IRQ_HANDLED /* nothing */ #define IRQ_NONE /* nothing */ #if defined(__FreeBSD__) #define DRM_DEVICE \ drm_device_t *dev = kdev->si_drv1 #define DRM_IOCTL_ARGS struct cdev *kdev, u_long cmd, caddr_t data, \ int flags, DRM_STRUCTPROC *p, DRMFILE filp #define PAGE_ALIGN(addr) round_page(addr) #define DRM_SUSER(p) suser(p) #define DRM_AGP_FIND_DEVICE() agp_find_device() #define DRM_MTRR_WC MDF_WRITECOMBINE #define jiffies ticks #else /* __FreeBSD__ */ #if defined(__NetBSD__) #define DRM_DEVICE \ drm_device_t *dev = device_lookup(&drm_cd, minor(kdev)) #elif defined(__OpenBSD__) #define DRM_DEVICE \ drm_device_t *dev = (device_lookup(&drm_cd, \ minor(kdev)))->dv_cfdata->cf_driver->cd_devs[minor(kdev)] #endif /* __OpenBSD__ */ #define DRM_IOCTL_ARGS dev_t kdev, u_long cmd, caddr_t data, \ int flags, DRM_STRUCTPROC *p, DRMFILE filp #define CDEV_MAJOR 34 #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) #define DRM_SUSER(p) suser(p->p_ucred, &p->p_acflag) #define DRM_AGP_FIND_DEVICE() agp_find_device(0) #define DRM_MTRR_WC MTRR_TYPE_WC #define jiffies hardclock_ticks typedef drm_device_t *device_t; extern struct cfdriver drm_cd; #endif /* !__FreeBSD__ */ typedef unsigned long dma_addr_t; typedef u_int32_t u32; typedef u_int16_t u16; typedef u_int8_t u8; /* DRM_READMEMORYBARRIER() prevents reordering of reads. * DRM_WRITEMEMORYBARRIER() prevents reordering of writes. * DRM_MEMORYBARRIER() prevents reordering of reads and writes. */ #if defined(__i386__) #define DRM_READMEMORYBARRIER() __asm __volatile( \ "lock; addl $0,0(%%esp)" : : : "memory"); #define DRM_WRITEMEMORYBARRIER() __asm __volatile("" : : : "memory"); #define DRM_MEMORYBARRIER() __asm __volatile( \ "lock; addl $0,0(%%esp)" : : : "memory"); #elif defined(__alpha__) #define DRM_READMEMORYBARRIER() alpha_mb(); #define DRM_WRITEMEMORYBARRIER() alpha_wmb(); #define DRM_MEMORYBARRIER() alpha_mb(); #elif defined(__amd64__) #define DRM_READMEMORYBARRIER() __asm __volatile( \ "lock; addl $0,0(%%rsp)" : : : "memory"); #define DRM_WRITEMEMORYBARRIER() __asm __volatile("" : : : "memory"); #define DRM_MEMORYBARRIER() __asm __volatile( \ "lock; addl $0,0(%%rsp)" : : : "memory"); #endif #ifdef __FreeBSD__ #define DRM_READ8(map, offset) \ *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) #define DRM_READ16(map, offset) \ *(volatile u_int16_t *) (((unsigned long)(map)->handle) + (offset)) #define DRM_READ32(map, offset) \ *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) #define DRM_WRITE8(map, offset, val) \ *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) = val #define DRM_WRITE16(map, offset, val) \ *(volatile u_int16_t *) (((unsigned long)(map)->handle) + (offset)) = val #define DRM_WRITE32(map, offset, val) \ *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) = val #define DRM_VERIFYAREA_READ( uaddr, size ) \ (!useracc(__DECONST(caddr_t, uaddr), size, VM_PROT_READ)) #else /* __FreeBSD__ */ typedef vaddr_t vm_offset_t; #define DRM_READ8(map, offset) \ bus_space_read_1( (map)->bst, (map)->bsh, (offset)) #define DRM_READ16(map, offset) \ bus_space_read_2( (map)->bst, (map)->bsh, (offset)) #define DRM_READ32(map, offset) \ bus_space_read_4( (map)->bst, (map)->bsh, (offset)) #define DRM_WRITE8(map, offset, val) \ bus_space_write_1((map)->bst, (map)->bsh, (offset), (val)) #define DRM_WRITE16(map, offset, val) \ bus_space_write_2((map)->bst, (map)->bsh, (offset), (val)) #define DRM_WRITE32(map, offset, val) \ bus_space_write_4((map)->bst, (map)->bsh, (offset), (val)) #define DRM_VERIFYAREA_READ( uaddr, size ) \ (!uvm_useracc((caddr_t)uaddr, size, VM_PROT_READ)) #endif /* !__FreeBSD__ */ #define DRM_COPY_TO_USER_IOCTL(user, kern, size) \ if ( IOCPARM_LEN(cmd) != size) \ return EINVAL; \ *user = kern; #define DRM_COPY_FROM_USER_IOCTL(kern, user, size) \ if ( IOCPARM_LEN(cmd) != size) \ return EINVAL; \ kern = *user; #define DRM_COPY_TO_USER(user, kern, size) \ copyout(kern, user, size) #define DRM_COPY_FROM_USER(kern, user, size) \ copyin(user, kern, size) #define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \ copyin(arg2, arg1, arg3) #define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3) \ copyout(arg2, arg1, arg3) #if __FreeBSD_version > 500000 #define DRM_GET_USER_UNCHECKED(val, uaddr) \ ((val) = fuword32(uaddr), 0) #else #define DRM_GET_USER_UNCHECKED(val, uaddr) \ ((val) = fuword(uaddr), 0) #endif #define cpu_to_le32(x) htole32(x) #define le32_to_cpu(x) le32toh(x) #define DRM_ERR(v) v #define DRM_HZ hz #define DRM_UDELAY(udelay) DELAY(udelay) #define DRM_TIME_SLICE (hz/20) /* Time slice for GLXContexts */ #define DRM_GET_PRIV_SAREA(_dev, _ctx, _map) do { \ (_map) = (_dev)->context_sareas[_ctx]; \ } while(0) #define DRM_GET_PRIV_WITH_RETURN(_priv, _filp) \ do { \ if (_filp != (DRMFILE)(intptr_t)DRM_CURRENTPID) { \ DRM_ERROR("filp doesn't match curproc\n"); \ return EINVAL; \ } \ _priv = drm_find_file_by_proc(dev, DRM_CURPROC); \ if (_priv == NULL) { \ DRM_ERROR("can't find authenticator\n"); \ return EINVAL; \ } \ } while (0) #define LOCK_TEST_WITH_RETURN(dev, filp) \ do { \ if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) || \ dev->lock.filp != filp) { \ DRM_ERROR("%s called without lock held\n", \ __FUNCTION__); \ return EINVAL; \ } \ } while (0) #define DRM_GETSAREA() \ do { \ drm_local_map_t *map; \ DRM_SPINLOCK_ASSERT(&dev->dev_lock); \ TAILQ_FOREACH(map, &dev->maplist, link) { \ if (map->type == _DRM_SHM && \ map->flags & _DRM_CONTAINS_LOCK) { \ dev_priv->sarea = map; \ break; \ } \ } \ } while (0) #if defined(__FreeBSD__) && __FreeBSD_version > 500000 #define DRM_WAIT_ON( ret, queue, timeout, condition ) \ for ( ret = 0 ; !ret && !(condition) ; ) { \ DRM_UNLOCK(); \ mtx_lock(&dev->irq_lock); \ if (!(condition)) \ ret = msleep(&(queue), &dev->irq_lock, \ PZERO | PCATCH, "drmwtq", (timeout)); \ mtx_unlock(&dev->irq_lock); \ DRM_LOCK(); \ } #else #define DRM_WAIT_ON( ret, queue, timeout, condition ) \ for ( ret = 0 ; !ret && !(condition) ; ) { \ int s = spldrm(); \ if (!(condition)) \ ret = tsleep( &(queue), PZERO | PCATCH, \ "drmwtq", (timeout) ); \ splx(s); \ } #endif #define DRM_ERROR(fmt, arg...) \ printf("error: [" DRM_NAME ":pid%d:%s] *ERROR* " fmt, \ DRM_CURRENTPID, __func__ , ## arg) #define DRM_INFO(fmt, arg...) printf("info: [" DRM_NAME "] " fmt , ## arg) #define DRM_DEBUG(fmt, arg...) do { \ if (drm_debug_flag) \ printf("[" DRM_NAME ":pid%d:%s] " fmt, DRM_CURRENTPID, \ __func__ , ## arg); \ } while (0) typedef struct drm_pci_id_list { int vendor; int device; long driver_private; char *name; } drm_pci_id_list_t; typedef struct drm_ioctl_desc { int (*func)(DRM_IOCTL_ARGS); int auth_needed; int root_only; } drm_ioctl_desc_t; typedef struct drm_magic_entry { drm_magic_t magic; struct drm_file *priv; struct drm_magic_entry *next; } drm_magic_entry_t; typedef struct drm_magic_head { struct drm_magic_entry *head; struct drm_magic_entry *tail; } drm_magic_head_t; typedef struct drm_buf { int idx; /* Index into master buflist */ int total; /* Buffer size */ int order; /* log-base-2(total) */ int used; /* Amount of buffer in use (for DMA) */ unsigned long offset; /* Byte offset (used internally) */ void *address; /* Address of buffer */ unsigned long bus_address; /* Bus address of buffer */ struct drm_buf *next; /* Kernel-only: used for free list */ __volatile__ int pending; /* On hardware DMA queue */ DRMFILE filp; /* Unique identifier of holding process */ int context; /* Kernel queue for this buffer */ enum { DRM_LIST_NONE = 0, DRM_LIST_FREE = 1, DRM_LIST_WAIT = 2, DRM_LIST_PEND = 3, DRM_LIST_PRIO = 4, DRM_LIST_RECLAIM = 5 } list; /* Which list we're on */ int dev_priv_size; /* Size of buffer private stoarge */ void *dev_private; /* Per-buffer private storage */ } drm_buf_t; typedef struct drm_freelist { int initialized; /* Freelist in use */ atomic_t count; /* Number of free buffers */ drm_buf_t *next; /* End pointer */ int low_mark; /* Low water mark */ int high_mark; /* High water mark */ } drm_freelist_t; typedef struct drm_buf_entry { int buf_size; int buf_count; drm_buf_t *buflist; int seg_count; int page_order; vm_offset_t *seglist; dma_addr_t *seglist_bus; drm_freelist_t freelist; } drm_buf_entry_t; typedef TAILQ_HEAD(drm_file_list, drm_file) drm_file_list_t; struct drm_file { TAILQ_ENTRY(drm_file) link; int authenticated; int minor; pid_t pid; uid_t uid; int refs; drm_magic_t magic; unsigned long ioctl_count; void *driver_priv; }; typedef struct drm_lock_data { drm_hw_lock_t *hw_lock; /* Hardware lock */ DRMFILE filp; /* Unique identifier of holding process (NULL is kernel)*/ int lock_queue; /* Queue of blocked processes */ unsigned long lock_time; /* Time of last lock in jiffies */ } drm_lock_data_t; /* This structure, in the drm_device_t, is always initialized while the device * is open. dev->dma_lock protects the incrementing of dev->buf_use, which * when set marks that no further bufs may be allocated until device teardown * occurs (when the last open of the device has closed). The high/low * watermarks of bufs are only touched by the X Server, and thus not * concurrently accessed, so no locking is needed. */ typedef struct drm_device_dma { drm_buf_entry_t bufs[DRM_MAX_ORDER+1]; int buf_count; drm_buf_t **buflist; /* Vector of pointers info bufs */ int seg_count; int page_count; unsigned long *pagelist; unsigned long byte_count; enum { _DRM_DMA_USE_AGP = 0x01, _DRM_DMA_USE_SG = 0x02 } flags; } drm_device_dma_t; typedef struct drm_agp_mem { void *handle; unsigned long bound; /* address */ int pages; struct drm_agp_mem *prev; struct drm_agp_mem *next; } drm_agp_mem_t; typedef struct drm_agp_head { device_t agpdev; struct agp_info info; const char *chipset; drm_agp_mem_t *memory; unsigned long mode; int enabled; int acquired; unsigned long base; int mtrr; int cant_use_aperture; unsigned long page_mask; } drm_agp_head_t; typedef struct drm_sg_mem { unsigned long handle; void *virtual; int pages; dma_addr_t *busaddr; } drm_sg_mem_t; typedef TAILQ_HEAD(drm_map_list, drm_local_map) drm_map_list_t; typedef struct drm_local_map { unsigned long offset; /* Physical address (0 for SAREA)*/ unsigned long size; /* Physical size (bytes) */ drm_map_type_t type; /* Type of memory mapped */ drm_map_flags_t flags; /* Flags */ void *handle; /* User-space: "Handle" to pass to mmap */ /* Kernel-space: kernel-virtual address */ int mtrr; /* Boolean: MTRR used */ /* Private data */ int rid; /* PCI resource ID for bus_space */ int kernel_owned; /* Boolean: 1 = initmapped, 0 = addmapped */ struct resource *bsr; bus_space_tag_t bst; bus_space_handle_t bsh; TAILQ_ENTRY(drm_local_map) link; } drm_local_map_t; TAILQ_HEAD(drm_vbl_sig_list, drm_vbl_sig); typedef struct drm_vbl_sig { TAILQ_ENTRY(drm_vbl_sig) link; unsigned int sequence; int signo; int pid; } drm_vbl_sig_t; /** * DRM device functions structure */ struct drm_device { #if defined(__NetBSD__) || defined(__OpenBSD__) struct device device; /* softc is an extension of struct device */ #endif /* Beginning of driver-config section */ int (*preinit)(struct drm_device *, unsigned long flags); int (*postinit)(struct drm_device *, unsigned long flags); void (*prerelease)(struct drm_device *, void *filp); void (*pretakedown)(struct drm_device *); int (*postcleanup)(struct drm_device *); int (*presetup)(struct drm_device *); int (*postsetup)(struct drm_device *); int (*open_helper)(struct drm_device *, drm_file_t *); void (*free_filp_priv)(struct drm_device *, drm_file_t *); void (*release)(struct drm_device *, void *filp); int (*dma_ioctl)(DRM_IOCTL_ARGS); void (*dma_ready)(struct drm_device *); int (*dma_quiescent)(struct drm_device *); int (*dma_flush_block_and_flush)(struct drm_device *, int context, drm_lock_flags_t flags); int (*dma_flush_unblock)(struct drm_device *, int context, drm_lock_flags_t flags); int (*context_ctor)(struct drm_device *dev, int context); int (*context_dtor)(struct drm_device *dev, int context); int (*kernel_context_switch)(struct drm_device *dev, int old, int new); int (*kernel_context_switch_unlock)(struct drm_device *dev); void (*irq_preinstall)(drm_device_t *dev); void (*irq_postinstall)(drm_device_t *dev); void (*irq_uninstall)(drm_device_t *dev); void (*irq_handler)(DRM_IRQ_ARGS); int (*vblank_wait)(drm_device_t *dev, unsigned int *sequence); drm_ioctl_desc_t *driver_ioctls; int max_driver_ioctl; int dev_priv_size; int driver_major; int driver_minor; int driver_patchlevel; const char *driver_name; /* Simple driver name */ const char *driver_desc; /* Longer driver name */ const char *driver_date; /* Date of last major changes. */ unsigned use_agp :1; unsigned require_agp :1; unsigned use_sg :1; unsigned use_dma :1; unsigned use_pci_dma :1; unsigned use_dma_queue :1; unsigned use_irq :1; unsigned use_vbl_irq :1; unsigned use_mtrr :1; /* End of driver-config section */ char *unique; /* Unique identifier: e.g., busid */ int unique_len; /* Length of unique field */ #ifdef __FreeBSD__ device_t device; /* Device instance from newbus */ #endif struct cdev *devnode; /* Device number for mknod */ int if_version; /* Highest interface version set */ int flags; /* Flags to open(2) */ /* Locks */ #if defined(__FreeBSD__) && __FreeBSD_version > 500000 struct mtx dma_lock; /* protects dev->dma */ struct mtx irq_lock; /* protects irq condition checks */ struct mtx dev_lock; /* protects everything else */ #endif /* Usage Counters */ int open_count; /* Outstanding files open */ int buf_use; /* Buffers in use -- cannot alloc */ /* Performance counters */ unsigned long counters; drm_stat_type_t types[15]; atomic_t counts[15]; /* Authentication */ drm_file_list_t files; drm_magic_head_t magiclist[DRM_HASH_SIZE]; /* Linked list of mappable regions. Protected by dev_lock */ drm_map_list_t maplist; drm_local_map_t **context_sareas; int max_context; drm_lock_data_t lock; /* Information on hardware lock */ /* DMA queues (contexts) */ drm_device_dma_t *dma; /* Optional pointer for DMA support */ /* Context support */ int irq; /* Interrupt used by board */ int irq_enabled; /* True if the irq handler is enabled */ #ifdef __FreeBSD__ int irqrid; /* Interrupt used by board */ struct resource *irqr; /* Resource for interrupt used by board */ #elif defined(__NetBSD__) || defined(__OpenBSD__) struct pci_attach_args pa; pci_intr_handle_t ih; #endif void *irqh; /* Handle from bus_setup_intr */ int pci_domain; int pci_bus; int pci_slot; int pci_func; atomic_t context_flag; /* Context swapping flag */ int last_context; /* Last current context */ int vbl_queue; /* vbl wait channel */ atomic_t vbl_received; #ifdef __FreeBSD__ struct sigio *buf_sigio; /* Processes waiting for SIGIO */ #elif defined(__NetBSD__) pid_t buf_pgid; #endif /* Sysctl support */ struct drm_sysctl_info *sysctl; drm_agp_head_t *agp; drm_sg_mem_t *sg; /* Scatter gather memory */ atomic_t *ctx_bitmap; void *dev_private; drm_local_map_t *agp_buffer_map; }; extern int drm_debug_flag; /* Device setup support (drm_drv.c) */ #ifdef __FreeBSD__ int drm_probe(device_t nbdev, drm_pci_id_list_t *idlist); int drm_attach(device_t nbdev, drm_pci_id_list_t *idlist); int drm_detach(device_t nbdev); d_ioctl_t drm_ioctl; d_open_t drm_open; d_close_t drm_close; d_read_t drm_read; d_poll_t drm_poll; d_mmap_t drm_mmap; #elif defined(__NetBSD__) || defined(__OpenBSD__) int drm_probe(struct pci_attach_args *pa, drm_pci_id_list_t *idlist); int drm_attach(struct pci_attach_args *pa, dev_t kdev, drm_pci_id_list_t *idlist); dev_type_ioctl(drm_ioctl); dev_type_open(drm_open); dev_type_close(drm_close); dev_type_read(drm_read); dev_type_poll(drm_poll); dev_type_mmap(drm_mmap); #endif /* File operations helpers (drm_fops.c) */ #ifdef __FreeBSD__ extern int drm_open_helper(struct cdev *kdev, int flags, int fmt, DRM_STRUCTPROC *p, drm_device_t *dev); extern drm_file_t *drm_find_file_by_proc(drm_device_t *dev, DRM_STRUCTPROC *p); #elif defined(__NetBSD__) || defined(__OpenBSD__) extern int drm_open_helper(dev_t kdev, int flags, int fmt, DRM_STRUCTPROC *p, drm_device_t *dev); extern drm_file_t *drm_find_file_by_proc(drm_device_t *dev, DRM_STRUCTPROC *p); #endif /* __NetBSD__ || __OpenBSD__ */ /* Memory management support (drm_memory.c) */ void drm_mem_init(void); void drm_mem_uninit(void); void *drm_alloc(size_t size, int area); void *drm_calloc(size_t nmemb, size_t size, int area); void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area); void drm_free(void *pt, size_t size, int area); void *drm_ioremap(drm_device_t *dev, drm_local_map_t *map); void drm_ioremapfree(drm_local_map_t *map); int drm_mtrr_add(unsigned long offset, size_t size, int flags); int drm_mtrr_del(unsigned long offset, size_t size, int flags); int drm_context_switch(drm_device_t *dev, int old, int new); int drm_context_switch_complete(drm_device_t *dev, int new); int drm_ctxbitmap_init(drm_device_t *dev); void drm_ctxbitmap_cleanup(drm_device_t *dev); void drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle); int drm_ctxbitmap_next(drm_device_t *dev); /* Locking IOCTL support (drm_lock.c) */ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context); int drm_lock_transfer(drm_device_t *dev, __volatile__ unsigned int *lock, unsigned int context); int drm_lock_free(drm_device_t *dev, __volatile__ unsigned int *lock, unsigned int context); /* Buffer management support (drm_bufs.c) */ unsigned long drm_get_resource_start(drm_device_t *dev, unsigned int resource); unsigned long drm_get_resource_len(drm_device_t *dev, unsigned int resource); int drm_initmap(drm_device_t *dev, unsigned long start, unsigned long len, unsigned int resource, int type, int flags); void drm_remove_map(drm_device_t *dev, drm_local_map_t *map); int drm_order(unsigned long size); /* DMA support (drm_dma.c) */ int drm_dma_setup(drm_device_t *dev); void drm_dma_takedown(drm_device_t *dev); void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf); void drm_reclaim_buffers(drm_device_t *dev, DRMFILE filp); /* IRQ support (drm_irq.c) */ int drm_irq_install(drm_device_t *dev); int drm_irq_uninstall(drm_device_t *dev); irqreturn_t drm_irq_handler(DRM_IRQ_ARGS); void drm_driver_irq_preinstall(drm_device_t *dev); void drm_driver_irq_postinstall(drm_device_t *dev); void drm_driver_irq_uninstall(drm_device_t *dev); int drm_vblank_wait(drm_device_t *dev, unsigned int *vbl_seq); void drm_vbl_send_signals(drm_device_t *dev); /* AGP/GART support (drm_agpsupport.c) */ int drm_device_is_agp(drm_device_t *dev); drm_agp_head_t *drm_agp_init(void); void drm_agp_uninit(void); void drm_agp_do_release(void); void *drm_agp_allocate_memory(size_t pages, u32 type); int drm_agp_free_memory(void *handle); int drm_agp_bind_memory(void *handle, off_t start); int drm_agp_unbind_memory(void *handle); /* Scatter Gather Support (drm_scatter.c) */ void drm_sg_cleanup(drm_sg_mem_t *entry); #ifdef __FreeBSD__ /* sysctl support (drm_sysctl.h) */ extern int drm_sysctl_init(drm_device_t *dev); extern int drm_sysctl_cleanup(drm_device_t *dev); #endif /* __FreeBSD__ */ /* ATI PCIGART support (ati_pcigart.c) */ int drm_ati_pcigart_init(drm_device_t *dev, unsigned long *addr, dma_addr_t *bus_addr); int drm_ati_pcigart_cleanup(drm_device_t *dev, unsigned long addr, dma_addr_t bus_addr); /* Locking IOCTL support (drm_drv.c) */ int drm_lock(DRM_IOCTL_ARGS); int drm_unlock(DRM_IOCTL_ARGS); int drm_version(DRM_IOCTL_ARGS); int drm_setversion(DRM_IOCTL_ARGS); /* Misc. IOCTL support (drm_ioctl.c) */ int drm_irq_by_busid(DRM_IOCTL_ARGS); int drm_getunique(DRM_IOCTL_ARGS); int drm_setunique(DRM_IOCTL_ARGS); int drm_getmap(DRM_IOCTL_ARGS); int drm_getclient(DRM_IOCTL_ARGS); int drm_getstats(DRM_IOCTL_ARGS); int drm_noop(DRM_IOCTL_ARGS); /* Context IOCTL support (drm_context.c) */ int drm_resctx(DRM_IOCTL_ARGS); int drm_addctx(DRM_IOCTL_ARGS); int drm_modctx(DRM_IOCTL_ARGS); int drm_getctx(DRM_IOCTL_ARGS); int drm_switchctx(DRM_IOCTL_ARGS); int drm_newctx(DRM_IOCTL_ARGS); int drm_rmctx(DRM_IOCTL_ARGS); int drm_setsareactx(DRM_IOCTL_ARGS); int drm_getsareactx(DRM_IOCTL_ARGS); /* Drawable IOCTL support (drm_drawable.c) */ int drm_adddraw(DRM_IOCTL_ARGS); int drm_rmdraw(DRM_IOCTL_ARGS); /* Authentication IOCTL support (drm_auth.c) */ int drm_getmagic(DRM_IOCTL_ARGS); int drm_authmagic(DRM_IOCTL_ARGS); /* Buffer management support (drm_bufs.c) */ int drm_addmap(DRM_IOCTL_ARGS); int drm_rmmap(DRM_IOCTL_ARGS); int drm_addbufs(DRM_IOCTL_ARGS); int drm_infobufs(DRM_IOCTL_ARGS); int drm_markbufs(DRM_IOCTL_ARGS); int drm_freebufs(DRM_IOCTL_ARGS); int drm_mapbufs(DRM_IOCTL_ARGS); /* DMA support (drm_dma.c) */ int drm_dma(DRM_IOCTL_ARGS); /* IRQ support (drm_irq.c) */ int drm_control(DRM_IOCTL_ARGS); int drm_wait_vblank(DRM_IOCTL_ARGS); /* AGP/GART support (drm_agpsupport.c) */ int drm_agp_acquire(DRM_IOCTL_ARGS); int drm_agp_release(DRM_IOCTL_ARGS); int drm_agp_enable(DRM_IOCTL_ARGS); int drm_agp_info(DRM_IOCTL_ARGS); int drm_agp_alloc(DRM_IOCTL_ARGS); int drm_agp_free(DRM_IOCTL_ARGS); int drm_agp_unbind(DRM_IOCTL_ARGS); int drm_agp_bind(DRM_IOCTL_ARGS); /* Scatter Gather Support (drm_scatter.c) */ int drm_sg_alloc(DRM_IOCTL_ARGS); int drm_sg_free(DRM_IOCTL_ARGS); /* consistent PCI memory functions (drm_pci.c) */ void *drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, dma_addr_t maxaddr, dma_addr_t *busaddr); void drm_pci_free(drm_device_t *dev, size_t size, void *vaddr, dma_addr_t busaddr); /* Inline replacements for DRM_IOREMAP macros */ static __inline__ void drm_core_ioremap(struct drm_local_map *map, struct drm_device *dev) { map->handle = drm_ioremap(dev, map); } static __inline__ void drm_core_ioremapfree(struct drm_local_map *map, struct drm_device *dev) { if ( map->handle && map->size ) drm_ioremapfree(map); } static __inline__ struct drm_local_map *drm_core_findmap(struct drm_device *dev, unsigned long offset) { drm_local_map_t *map; DRM_SPINLOCK_ASSERT(&dev->dev_lock); TAILQ_FOREACH(map, &dev->maplist, link) { if (map->offset == offset) return map; } return NULL; } static __inline__ void drm_core_dropmap(struct drm_map *map) { } #endif /* __KERNEL__ */ #endif /* _DRM_P_H_ */ 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 
/* mach64_drv.h -- Private header for mach64 driver -*- linux-c -*-
 * Created: Fri Nov 24 22:07:58 2000 by gareth@valinux.com
 */
/*
 * Copyright 2000 Gareth Hughes
 * Copyright 2002 Frank C. Earl
 * Copyright 2002-2003 Leif Delgass
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Gareth Hughes <gareth@valinux.com>
 *    Frank C. Earl <fearl@airmail.net>
 *    Leif Delgass <ldelgass@retinalburn.net>
 *    José Fonseca <j_r_fonseca@yahoo.co.uk>
 */

#ifndef __MACH64_DRV_H__
#define __MACH64_DRV_H__

/* General customization:
 */

#define DRIVER_AUTHOR		"Gareth Hughes, Leif Delgass, José Fonseca"

#define DRIVER_NAME		"mach64"
#define DRIVER_DESC		"DRM module for the ATI Rage Pro"
#define DRIVER_DATE		"20060718"

#define DRIVER_MAJOR		2
#define DRIVER_MINOR		0
#define DRIVER_PATCHLEVEL	0

/* FIXME: remove these when not needed */
/* Development driver options */
#define MACH64_EXTRA_CHECKING     0	/* Extra sanity checks for DMA/freelist management */
#define MACH64_VERBOSE		  0	/* Verbose debugging output */

typedef struct drm_mach64_freelist {
	struct list_head list;	/* List pointers for free_list, placeholders, or pending list */
	struct drm_buf *buf;		/* Pointer to the buffer */
	int discard;		/* This flag is set when we're done (re)using a buffer */
	u32 ring_ofs;		/* dword offset in ring of last descriptor for this buffer */
} drm_mach64_freelist_t;

typedef struct drm_mach64_descriptor_ring {
	void *start;		/* write pointer (cpu address) to start of descriptor ring */
	u32 start_addr;		/* bus address of beginning of descriptor ring */
	int size;		/* size of ring in bytes */

	u32 head_addr;		/* bus address of descriptor ring head */
	u32 head;		/* dword offset of descriptor ring head */
	u32 tail;		/* dword offset of descriptor ring tail */
	u32 tail_mask;		/* mask used to wrap ring */
	int space;		/* number of free bytes in ring */
} drm_mach64_descriptor_ring_t;

typedef struct drm_mach64_private {
	drm_mach64_sarea_t *sarea_priv;

	int is_pci;
	drm_mach64_dma_mode_t driver_mode;	/* Async DMA, sync DMA, or MMIO */

	int usec_timeout;	/* Timeout for the wait functions */

	drm_mach64_descriptor_ring_t ring;	/* DMA descriptor table (ring buffer) */
	int ring_running;	/* Is bus mastering is enabled */

	struct list_head free_list;	/* Free-list head */
	struct list_head placeholders;	/* Placeholder list for buffers held by clients */
	struct list_head pending;	/* Buffers pending completion */

	u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES];	/* dword ring offsets of most recent frame swaps */

	unsigned int fb_bpp;
	unsigned int front_offset, front_pitch;
	unsigned int back_offset, back_pitch;

	unsigned int depth_bpp;
	unsigned int depth_offset, depth_pitch;

	atomic_t vbl_received;          /**< Number of vblanks received. */

	u32 front_offset_pitch;
	u32 back_offset_pitch;
	u32 depth_offset_pitch;

	drm_local_map_t *sarea;
	drm_local_map_t *fb;
	drm_local_map_t *mmio;
	drm_local_map_t *ring_map;
	drm_local_map_t *dev_buffers;	/* this is a pointer to a structure in dev */
	drm_local_map_t *agp_textures;
} drm_mach64_private_t;

extern struct drm_ioctl_desc mach64_ioctls[];
extern int mach64_max_ioctl;

				/* mach64_dma.c */
extern int mach64_dma_init(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
extern int mach64_dma_idle(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
extern int mach64_dma_flush(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
extern int mach64_engine_reset(struct drm_device *dev, void *data,
			       struct drm_file *file_priv);
extern int mach64_dma_buffers(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
extern void mach64_driver_lastclose(struct drm_device * dev);

extern int mach64_init_freelist(struct drm_device * dev);
extern void mach64_destroy_freelist(struct drm_device * dev);
extern struct drm_buf *mach64_freelist_get(drm_mach64_private_t * dev_priv);
extern int mach64_freelist_put(drm_mach64_private_t * dev_priv,
			       struct drm_buf * copy_buf);

extern int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv,
				   int entries);
extern int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv);
extern int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n);
extern int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv);
extern int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv);
extern void mach64_dump_engine_info(drm_mach64_private_t * dev_priv);
extern void mach64_dump_ring_info(drm_mach64_private_t * dev_priv);
extern int mach64_do_engine_reset(drm_mach64_private_t * dev_priv);

extern int mach64_add_buf_to_ring(drm_mach64_private_t *dev_priv,
                                  drm_mach64_freelist_t *_entry);
extern int mach64_add_hostdata_buf_to_ring(drm_mach64_private_t *dev_priv,
                                           drm_mach64_freelist_t *_entry);

extern int mach64_do_dma_idle(drm_mach64_private_t * dev_priv);
extern int mach64_do_dma_flush(drm_mach64_private_t * dev_priv);
extern int mach64_do_cleanup_dma(struct drm_device * dev);

				/* mach64_state.c */
extern int mach64_dma_clear(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
extern int mach64_dma_swap(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
extern int mach64_dma_vertex(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
extern int mach64_dma_blit(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
extern int mach64_get_param(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);

extern u32 mach64_get_vblank_counter(struct drm_device *dev, int crtc);
extern int mach64_enable_vblank(struct drm_device *dev, int crtc);
extern void mach64_disable_vblank(struct drm_device *dev, int crtc);
extern irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS);
extern void mach64_driver_irq_preinstall(struct drm_device *dev);
extern int mach64_driver_irq_postinstall(struct drm_device *dev);
extern void mach64_driver_irq_uninstall(struct drm_device *dev);

/* ================================================================
 * Registers
 */

#define MACH64_AGP_BASE				0x0148
#define MACH64_AGP_CNTL				0x014c
#define MACH64_ALPHA_TST_CNTL			0x0550

#define MACH64_DSP_CONFIG			0x0420
#define MACH64_DSP_ON_OFF			0x0424
#define MACH64_EXT_MEM_CNTL			0x04ac
#define MACH64_GEN_TEST_CNTL			0x04d0
#define MACH64_HW_DEBUG				0x047c
#define MACH64_MEM_ADDR_CONFIG			0x0434
#define MACH64_MEM_BUF_CNTL			0x042c
#define MACH64_MEM_CNTL				0x04b0

#define MACH64_BM_ADDR				0x0648
#define MACH64_BM_COMMAND			0x0188
#define MACH64_BM_DATA				0x0648
#define MACH64_BM_FRAME_BUF_OFFSET		0x0180
#define MACH64_BM_GUI_TABLE			0x01b8
#define MACH64_BM_GUI_TABLE_CMD			0x064c
#	define MACH64_CIRCULAR_BUF_SIZE_16KB		(0 << 0)
#	define MACH64_CIRCULAR_BUF_SIZE_32KB		(1 << 0)
#	define MACH64_CIRCULAR_BUF_SIZE_64KB		(2 << 0)
#	define MACH64_CIRCULAR_BUF_SIZE_128KB		(3 << 0)
#	define MACH64_LAST_DESCRIPTOR			(1 << 31)
#define MACH64_BM_HOSTDATA			0x0644
#define MACH64_BM_STATUS			0x018c
#define MACH64_BM_SYSTEM_MEM_ADDR		0x0184
#define MACH64_BM_SYSTEM_TABLE			0x01bc
#define MACH64_BUS_CNTL				0x04a0
#	define MACH64_BUS_MSTR_RESET			(1 << 1)
#	define MACH64_BUS_APER_REG_DIS			(1 << 4)
#	define MACH64_BUS_FLUSH_BUF			(1 << 2)
#	define MACH64_BUS_MASTER_DIS			(1 << 6)
#	define MACH64_BUS_EXT_REG_EN			(1 << 27)

#define MACH64_CLR_CMP_CLR			0x0700
#define MACH64_CLR_CMP_CNTL			0x0708
#define MACH64_CLR_CMP_MASK			0x0704
#define MACH64_CONFIG_CHIP_ID			0x04e0
#define MACH64_CONFIG_CNTL			0x04dc
#define MACH64_CONFIG_STAT0			0x04e4
#define MACH64_CONFIG_STAT1			0x0494
#define MACH64_CONFIG_STAT2			0x0498
#define MACH64_CONTEXT_LOAD_CNTL		0x072c
#define MACH64_CONTEXT_MASK			0x0720
#define MACH64_COMPOSITE_SHADOW_ID		0x0798
#define MACH64_CRC_SIG				0x04e8
#define MACH64_CUSTOM_MACRO_CNTL		0x04d4

#define MACH64_DP_BKGD_CLR			0x06c0
#define MACH64_DP_FOG_CLR			0x06c4
#define MACH64_DP_FGRD_BKGD_CLR			0x06e0
#define MACH64_DP_FRGD_CLR			0x06c4
#define MACH64_DP_FGRD_CLR_MIX			0x06dc

#define MACH64_DP_MIX				0x06d4
#	define BKGD_MIX_NOT_D				(0 << 0)
#	define BKGD_MIX_ZERO				(1 << 0)
#	define BKGD_MIX_ONE				(2 << 0)
#	define MACH64_BKGD_MIX_D			(3 << 0)
#	define BKGD_MIX_NOT_S				(4 << 0)
#	define BKGD_MIX_D_XOR_S				(5 << 0)
#	define BKGD_MIX_NOT_D_XOR_S			(6 << 0)
#	define MACH64_BKGD_MIX_S			(7 << 0)
#	define BKGD_MIX_NOT_D_OR_NOT_S			(8 << 0)
#	define BKGD_MIX_D_OR_NOT_S			(9 << 0)
#	define BKGD_MIX_NOT_D_OR_S			(10 << 0)
#	define BKGD_MIX_D_OR_S				(11 << 0)
#	define BKGD_MIX_D_AND_S				(12 << 0)
#	define BKGD_MIX_NOT_D_AND_S			(13 << 0)
#	define BKGD_MIX_D_AND_NOT_S			(14 << 0)
#	define BKGD_MIX_NOT_D_AND_NOT_S			(15 << 0)
#	define BKGD_MIX_D_PLUS_S_DIV2			(23 << 0)
#	define FRGD_MIX_NOT_D				(0 << 16)
#	define FRGD_MIX_ZERO				(1 << 16)
#	define FRGD_MIX_ONE				(2 << 16)
#	define FRGD_MIX_D				(3 << 16)
#	define FRGD_MIX_NOT_S				(4 << 16)
#	define FRGD_MIX_D_XOR_S				(5 << 16)
#	define FRGD_MIX_NOT_D_XOR_S			(6 << 16)
#	define MACH64_FRGD_MIX_S			(7 << 16)
#	define FRGD_MIX_NOT_D_OR_NOT_S			(8 << 16)
#	define FRGD_MIX_D_OR_NOT_S			(9 << 16)
#	define FRGD_MIX_NOT_D_OR_S			(10 << 16)
#	define FRGD_MIX_D_OR_S				(11 << 16)
#	define FRGD_MIX_D_AND_S				(12 << 16)
#	define FRGD_MIX_NOT_D_AND_S			(13 << 16)
#	define FRGD_MIX_D_AND_NOT_S			(14 << 16)
#	define FRGD_MIX_NOT_D_AND_NOT_S			(15 << 16)
#	define FRGD_MIX_D_PLUS_S_DIV2			(23 << 16)

#define MACH64_DP_PIX_WIDTH			0x06d0
#	define MACH64_HOST_TRIPLE_ENABLE		(1 << 13)
#	define MACH64_BYTE_ORDER_MSB_TO_LSB		(0 << 24)
#	define MACH64_BYTE_ORDER_LSB_TO_MSB		(1 << 24)

#define MACH64_DP_SRC				0x06d8
#	define MACH64_BKGD_SRC_BKGD_CLR			(0 << 0)
#	define MACH64_BKGD_SRC_FRGD_CLR			(1 << 0)
#	define MACH64_BKGD_SRC_HOST			(2 << 0)
#	define MACH64_BKGD_SRC_BLIT			(3 << 0)
#	define MACH64_BKGD_SRC_PATTERN			(4 << 0)
#	define MACH64_BKGD_SRC_3D			(5 << 0)
#	define MACH64_FRGD_SRC_BKGD_CLR			(0 << 8)
#	define MACH64_FRGD_SRC_FRGD_CLR			(1 << 8)
#	define MACH64_FRGD_SRC_HOST			(2 << 8)
#	define MACH64_FRGD_SRC_BLIT			(3 << 8)
#	define MACH64_FRGD_SRC_PATTERN			(4 << 8)
#	define MACH64_FRGD_SRC_3D			(5 << 8)
#	define MACH64_MONO_SRC_ONE			(0 << 16)
#	define MACH64_MONO_SRC_PATTERN			(1 << 16)
#	define MACH64_MONO_SRC_HOST			(2 << 16)
#	define MACH64_MONO_SRC_BLIT			(3 << 16)

#define MACH64_DP_WRITE_MASK			0x06c8

#define MACH64_DST_CNTL				0x0530
#	define MACH64_DST_X_RIGHT_TO_LEFT		(0 << 0)
#	define MACH64_DST_X_LEFT_TO_RIGHT		(1 << 0)
#	define MACH64_DST_Y_BOTTOM_TO_TOP		(0 << 1)
#	define MACH64_DST_Y_TOP_TO_BOTTOM		(1 << 1)
#	define MACH64_DST_X_MAJOR			(0 << 2)
#	define MACH64_DST_Y_MAJOR			(1 << 2)
#	define MACH64_DST_X_TILE			(1 << 3)
#	define MACH64_DST_Y_TILE			(1 << 4)
#	define MACH64_DST_LAST_PEL			(1 << 5)
#	define MACH64_DST_POLYGON_ENABLE		(1 << 6)
#	define MACH64_DST_24_ROTATION_ENABLE		(1 << 7)

#define MACH64_DST_HEIGHT_WIDTH			0x0518
#define MACH64_DST_OFF_PITCH			0x0500
#define MACH64_DST_WIDTH_HEIGHT			0x06ec
#define MACH64_DST_X_Y				0x06e8
#define MACH64_DST_Y_X				0x050c

#define MACH64_FIFO_STAT			0x0710
#	define MACH64_FIFO_SLOT_MASK			0x0000ffff
#	define MACH64_FIFO_ERR				(1 << 31)

#define MACH64_GEN_TEST_CNTL			0x04d0
#	define MACH64_GUI_ENGINE_ENABLE			(1 << 8)
#define MACH64_GUI_CMDFIFO_DEBUG		0x0170
#define MACH64_GUI_CMDFIFO_DATA			0x0174
#define MACH64_GUI_CNTL				0x0178
#       define MACH64_CMDFIFO_SIZE_MASK                 0x00000003ul
#       define MACH64_CMDFIFO_SIZE_192                  0x00000000ul
#       define MACH64_CMDFIFO_SIZE_128                  0x00000001ul
#       define MACH64_CMDFIFO_SIZE_64                   0x00000002ul
#define MACH64_GUI_STAT				0x0738
#	define MACH64_GUI_ACTIVE			(1 << 0)
#define MACH64_GUI_TRAJ_CNTL			0x0730

#define MACH64_HOST_CNTL			0x0640
#define MACH64_HOST_DATA0			0x0600

#define MACH64_ONE_OVER_AREA			0x029c
#define MACH64_ONE_OVER_AREA_UC			0x0300

#define MACH64_PAT_REG0				0x0680
#define MACH64_PAT_REG1				0x0684

#define MACH64_SC_LEFT                          0x06a0
#define MACH64_SC_RIGHT                         0x06a4
#define MACH64_SC_LEFT_RIGHT                    0x06a8
#define MACH64_SC_TOP                           0x06ac
#define MACH64_SC_BOTTOM                        0x06b0
#define MACH64_SC_TOP_BOTTOM                    0x06b4

#define MACH64_SCALE_3D_CNTL			0x05fc
#define MACH64_SCRATCH_REG0			0x0480
#define MACH64_SCRATCH_REG1			0x0484
#define MACH64_SECONDARY_TEX_OFF		0x0778
#define MACH64_SETUP_CNTL			0x0304
#define MACH64_SRC_CNTL				0x05b4
#	define MACH64_SRC_BM_ENABLE			(1 << 8)
#	define MACH64_SRC_BM_SYNC			(1 << 9)
#	define MACH64_SRC_BM_OP_FRAME_TO_SYSTEM		(0 << 10)
#	define MACH64_SRC_BM_OP_SYSTEM_TO_FRAME		(1 << 10)
#	define MACH64_SRC_BM_OP_REG_TO_SYSTEM		(2 << 10)
#	define MACH64_SRC_BM_OP_SYSTEM_TO_REG		(3 << 10)
#define MACH64_SRC_HEIGHT1			0x0594
#define MACH64_SRC_HEIGHT2			0x05ac
#define MACH64_SRC_HEIGHT1_WIDTH1		0x0598
#define MACH64_SRC_HEIGHT2_WIDTH2		0x05b0
#define MACH64_SRC_OFF_PITCH			0x0580
#define MACH64_SRC_WIDTH1			0x0590
#define MACH64_SRC_Y_X				0x058c

#define MACH64_TEX_0_OFF			0x05c0
#define MACH64_TEX_CNTL				0x0774
#define MACH64_TEX_SIZE_PITCH			0x0770
#define MACH64_TIMER_CONFIG			0x0428

#define MACH64_VERTEX_1_ARGB			0x0254
#define MACH64_VERTEX_1_S			0x0240
#define MACH64_VERTEX_1_SECONDARY_S		0x0328
#define MACH64_VERTEX_1_SECONDARY_T		0x032c
#define MACH64_VERTEX_1_SECONDARY_W		0x0330
#define MACH64_VERTEX_1_SPEC_ARGB		0x024c
#define MACH64_VERTEX_1_T			0x0244
#define MACH64_VERTEX_1_W			0x0248
#define MACH64_VERTEX_1_X_Y			0x0258
#define MACH64_VERTEX_1_Z			0x0250
#define MACH64_VERTEX_2_ARGB			0x0274
#define MACH64_VERTEX_2_S			0x0260
#define MACH64_VERTEX_2_SECONDARY_S		0x0334
#define MACH64_VERTEX_2_SECONDARY_T		0x0338
#define MACH64_VERTEX_2_SECONDARY_W		0x033c
#define MACH64_VERTEX_2_SPEC_ARGB		0x026c
#define MACH64_VERTEX_2_T			0x0264
#define MACH64_VERTEX_2_W			0x0268
#define MACH64_VERTEX_2_X_Y			0x0278
#define MACH64_VERTEX_2_Z			0x0270
#define MACH64_VERTEX_3_ARGB			0x0294
#define MACH64_VERTEX_3_S			0x0280
#define MACH64_VERTEX_3_SECONDARY_S		0x02a0
#define MACH64_VERTEX_3_SECONDARY_T		0x02a4
#define MACH64_VERTEX_3_SECONDARY_W		0x02a8
#define MACH64_VERTEX_3_SPEC_ARGB		0x028c
#define MACH64_VERTEX_3_T			0x0284
#define MACH64_VERTEX_3_W			0x0288
#define MACH64_VERTEX_3_X_Y			0x0298
#define MACH64_VERTEX_3_Z			0x0290

#define MACH64_Z_CNTL				0x054c
#define MACH64_Z_OFF_PITCH			0x0548

#define MACH64_CRTC_VLINE_CRNT_VLINE		0x0410
#	define MACH64_CRTC_VLINE_MASK		        0x000007ff
#	define MACH64_CRTC_CRNT_VLINE_MASK		0x07ff0000
#define MACH64_CRTC_OFF_PITCH			0x0414
#define MACH64_CRTC_INT_CNTL			0x0418
#	define MACH64_CRTC_VBLANK			(1 << 0)
#	define MACH64_CRTC_VBLANK_INT_EN		(1 << 1)
#	define MACH64_CRTC_VBLANK_INT			(1 << 2)
#	define MACH64_CRTC_VLINE_INT_EN			(1 << 3)
#	define MACH64_CRTC_VLINE_INT			(1 << 4)
#	define MACH64_CRTC_VLINE_SYNC			(1 << 5)	/* 0=even, 1=odd */
#	define MACH64_CRTC_FRAME			(1 << 6)	/* 0=even, 1=odd */
#	define MACH64_CRTC_SNAPSHOT_INT_EN		(1 << 7)
#	define MACH64_CRTC_SNAPSHOT_INT			(1 << 8)
#	define MACH64_CRTC_I2C_INT_EN			(1 << 9)
#	define MACH64_CRTC_I2C_INT			(1 << 10)
#	define MACH64_CRTC2_VBLANK			(1 << 11)	/* LT Pro */
#	define MACH64_CRTC2_VBLANK_INT_EN		(1 << 12)	/* LT Pro */
#	define MACH64_CRTC2_VBLANK_INT			(1 << 13)	/* LT Pro */
#	define MACH64_CRTC2_VLINE_INT_EN		(1 << 14)	/* LT Pro */
#	define MACH64_CRTC2_VLINE_INT			(1 << 15)	/* LT Pro */
#	define MACH64_CRTC_CAPBUF0_INT_EN		(1 << 16)
#	define MACH64_CRTC_CAPBUF0_INT			(1 << 17)
#	define MACH64_CRTC_CAPBUF1_INT_EN		(1 << 18)
#	define MACH64_CRTC_CAPBUF1_INT			(1 << 19)
#	define MACH64_CRTC_OVERLAY_EOF_INT_EN		(1 << 20)
#	define MACH64_CRTC_OVERLAY_EOF_INT		(1 << 21)
#	define MACH64_CRTC_ONESHOT_CAP_INT_EN		(1 << 22)
#	define MACH64_CRTC_ONESHOT_CAP_INT		(1 << 23)
#	define MACH64_CRTC_BUSMASTER_EOL_INT_EN		(1 << 24)
#	define MACH64_CRTC_BUSMASTER_EOL_INT		(1 << 25)
#	define MACH64_CRTC_GP_INT_EN			(1 << 26)
#	define MACH64_CRTC_GP_INT			(1 << 27)
#	define MACH64_CRTC2_VLINE_SYNC			(1 << 28) /* LT Pro */	/* 0=even, 1=odd */
#	define MACH64_CRTC_SNAPSHOT2_INT_EN		(1 << 29)	/* LT Pro */
#	define MACH64_CRTC_SNAPSHOT2_INT		(1 << 30)	/* LT Pro */
#	define MACH64_CRTC_VBLANK2_INT			(1 << 31)
#	define MACH64_CRTC_INT_ENS				\
		(						\
			MACH64_CRTC_VBLANK_INT_EN |		\
			MACH64_CRTC_VLINE_INT_EN |		\
			MACH64_CRTC_SNAPSHOT_INT_EN |		\
			MACH64_CRTC_I2C_INT_EN |		\
			MACH64_CRTC2_VBLANK_INT_EN |		\
			MACH64_CRTC2_VLINE_INT_EN |		\
			MACH64_CRTC_CAPBUF0_INT_EN |		\
			MACH64_CRTC_CAPBUF1_INT_EN |		\
			MACH64_CRTC_OVERLAY_EOF_INT_EN |	\
			MACH64_CRTC_ONESHOT_CAP_INT_EN |	\
			MACH64_CRTC_BUSMASTER_EOL_INT_EN |	\
			MACH64_CRTC_GP_INT_EN |			\
			MACH64_CRTC_SNAPSHOT2_INT_EN |		\
			0					\
		)
#	define MACH64_CRTC_INT_ACKS			\
		(					\
			MACH64_CRTC_VBLANK_INT |	\
			MACH64_CRTC_VLINE_INT |		\
			MACH64_CRTC_SNAPSHOT_INT |	\
			MACH64_CRTC_I2C_INT |		\
			MACH64_CRTC2_VBLANK_INT |	\
			MACH64_CRTC2_VLINE_INT |	\
			MACH64_CRTC_CAPBUF0_INT |	\
			MACH64_CRTC_CAPBUF1_INT |	\
			MACH64_CRTC_OVERLAY_EOF_INT |	\
			MACH64_CRTC_ONESHOT_CAP_INT |	\
			MACH64_CRTC_BUSMASTER_EOL_INT |	\
			MACH64_CRTC_GP_INT |		\
			MACH64_CRTC_SNAPSHOT2_INT |	\
			MACH64_CRTC_VBLANK2_INT |	\
			0				\
		)

#define MACH64_DATATYPE_CI8				2
#define MACH64_DATATYPE_ARGB1555			3
#define MACH64_DATATYPE_RGB565				4
#define MACH64_DATATYPE_ARGB8888			6
#define MACH64_DATATYPE_RGB332				7
#define MACH64_DATATYPE_Y8				8
#define MACH64_DATATYPE_RGB8				9
#define MACH64_DATATYPE_VYUY422				11
#define MACH64_DATATYPE_YVYU422				12
#define MACH64_DATATYPE_AYUV444				14
#define MACH64_DATATYPE_ARGB4444			15

#define MACH64_READ(reg)	DRM_READ32(dev_priv->mmio, (reg) )
#define MACH64_WRITE(reg,val)	DRM_WRITE32(dev_priv->mmio, (reg), (val) )

#define DWMREG0		0x0400
#define DWMREG0_END	0x07ff
#define DWMREG1		0x0000
#define DWMREG1_END	0x03ff

#define ISREG0(r)	(((r) >= DWMREG0) && ((r) <= DWMREG0_END))
#define DMAREG0(r)	(((r) - DWMREG0) >> 2)
#define DMAREG1(r)	((((r) - DWMREG1) >> 2 ) | 0x0100)
#define DMAREG(r)	(ISREG0(r) ? DMAREG0(r) : DMAREG1(r))

#define MMREG0		0x0000
#define MMREG0_END	0x00ff

#define ISMMREG0(r)	(((r) >= MMREG0) && ((r) <= MMREG0_END))
#define MMSELECT0(r)	(((r) << 2) + DWMREG0)
#define MMSELECT1(r)	(((((r) & 0xff) << 2) + DWMREG1))
#define MMSELECT(r)	(ISMMREG0(r) ? MMSELECT0(r) : MMSELECT1(r))

/* ================================================================
 * DMA constants
 */

/* DMA descriptor field indices:
 * The descriptor fields are loaded into the read-only
 * BM_* system bus master registers during a bus-master operation
 */
#define MACH64_DMA_FRAME_BUF_OFFSET	0	/* BM_FRAME_BUF_OFFSET */
#define MACH64_DMA_SYS_MEM_ADDR		1	/* BM_SYSTEM_MEM_ADDR */
#define MACH64_DMA_COMMAND		2	/* BM_COMMAND */
#define MACH64_DMA_RESERVED		3	/* BM_STATUS */

/* BM_COMMAND descriptor field flags */
#define MACH64_DMA_HOLD_OFFSET		(1<<30)	/* Don't increment DMA_FRAME_BUF_OFFSET */
#define MACH64_DMA_EOL			(1<<31)	/* End of descriptor list flag */

#define MACH64_DMA_CHUNKSIZE	        0x1000	/* 4kB per DMA descriptor */
#define MACH64_APERTURE_OFFSET	        0x7ff800	/* frame-buffer offset for gui-masters */

/* ================================================================
 * Ring operations
 *
 * Since the Mach64 bus master engine requires polling, these functions end
 * up being called frequently, hence being inline.
 */

static __inline__ void mach64_ring_start(drm_mach64_private_t * dev_priv)
{
	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;

	DRM_DEBUG("head_addr: 0x%08x head: %d tail: %d space: %d\n",
		  ring->head_addr, ring->head, ring->tail, ring->space);

	if (mach64_do_wait_for_idle(dev_priv) < 0) {
		mach64_do_engine_reset(dev_priv);
	}

	if (dev_priv->driver_mode != MACH64_MODE_MMIO) {
		/* enable bus mastering and block 1 registers */
		MACH64_WRITE(MACH64_BUS_CNTL,
			     (MACH64_READ(MACH64_BUS_CNTL) &
			      ~MACH64_BUS_MASTER_DIS)
			     | MACH64_BUS_EXT_REG_EN);
		mach64_do_wait_for_idle(dev_priv);
	}

	/* reset descriptor table ring head */
	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
		     ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);

	dev_priv->ring_running = 1;
}

static __inline__ void mach64_ring_resume(drm_mach64_private_t * dev_priv,
					  drm_mach64_descriptor_ring_t * ring)
{
	DRM_DEBUG("head_addr: 0x%08x head: %d tail: %d space: %d\n",
		  ring->head_addr, ring->head, ring->tail, ring->space);

	/* reset descriptor table ring head */
	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
		     ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);

	if (dev_priv->driver_mode == MACH64_MODE_MMIO) {
		mach64_do_dispatch_pseudo_dma(dev_priv);
	} else {
		/* enable GUI bus mastering, and sync the bus master to the GUI */
		MACH64_WRITE(MACH64_SRC_CNTL,
			     MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
			     MACH64_SRC_BM_OP_SYSTEM_TO_REG);

		/* kick off the transfer */
		MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0);
		if (dev_priv->driver_mode == MACH64_MODE_DMA_SYNC) {
			if ((mach64_do_wait_for_idle(dev_priv)) < 0) {
				DRM_ERROR("idle failed, resetting engine\n");
				mach64_dump_engine_info(dev_priv);
				mach64_do_engine_reset(dev_priv);
				return;
			}
			mach64_do_release_used_buffers(dev_priv);
		}
	}
}

/**
 * Poll the ring head and make sure the bus master is alive.
 * 
 * Mach64's bus master engine will stop if there are no more entries to process.
 * This function polls the engine for the last processed entry and calls 
 * mach64_ring_resume if there is an unprocessed entry.
 * 
 * Note also that, since we update the ring tail while the bus master engine is 
 * in operation, it is possible that the last tail update was too late to be 
 * processed, and the bus master engine stops at the previous tail position. 
 * Therefore it is important to call this function frequently. 
 */
static __inline__ void mach64_ring_tick(drm_mach64_private_t * dev_priv,
					drm_mach64_descriptor_ring_t * ring)
{
	DRM_DEBUG("head_addr: 0x%08x head: %d tail: %d space: %d\n",
		  ring->head_addr, ring->head, ring->tail, ring->space);

	if (!dev_priv->ring_running) {
		mach64_ring_start(dev_priv);

		if (ring->head != ring->tail) {
			mach64_ring_resume(dev_priv, ring);
		}
	} else {
		/* GUI_ACTIVE must be read before BM_GUI_TABLE to
		 * correctly determine the ring head
		 */
		int gui_active =
		    MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE;

		ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0;

		if (gui_active) {
			/* If not idle, BM_GUI_TABLE points one descriptor
			 * past the current head
			 */
			if (ring->head_addr == ring->start_addr) {
				ring->head_addr += ring->size;
			}
			ring->head_addr -= 4 * sizeof(u32);
		}

		if (ring->head_addr < ring->start_addr ||
		    ring->head_addr >= ring->start_addr + ring->size) {
			DRM_ERROR("bad ring head address: 0x%08x\n",
				  ring->head_addr);
			mach64_dump_ring_info(dev_priv);
			mach64_do_engine_reset(dev_priv);
			return;
		}

		ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32);

		if (!gui_active && ring->head != ring->tail) {
			mach64_ring_resume(dev_priv, ring);
		}
	}
}

static __inline__ void mach64_ring_stop(drm_mach64_private_t * dev_priv)
{
	DRM_DEBUG("head_addr: 0x%08x head: %d tail: %d space: %d\n",
		  dev_priv->ring.head_addr, dev_priv->ring.head,
		  dev_priv->ring.tail, dev_priv->ring.space);

	/* restore previous SRC_CNTL to disable busmastering */
	mach64_do_wait_for_fifo(dev_priv, 1);
	MACH64_WRITE(MACH64_SRC_CNTL, 0);

	/* disable busmastering but keep the block 1 registers enabled */
	mach64_do_wait_for_idle(dev_priv);
	MACH64_WRITE(MACH64_BUS_CNTL, MACH64_READ(MACH64_BUS_CNTL)
		     | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN);

	dev_priv->ring_running = 0;
}

static __inline__ void
mach64_update_ring_snapshot(drm_mach64_private_t * dev_priv)
{
	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;

	DRM_DEBUG("\n");

	mach64_ring_tick(dev_priv, ring);

	ring->space = (ring->head - ring->tail) * sizeof(u32);
	if (ring->space <= 0) {
		ring->space += ring->size;
	}
}

/* ================================================================
 * DMA macros
 * 
 * Mach64's ring buffer doesn't take register writes directly. These 
 * have to be written indirectly in DMA buffers. These macros simplify 
 * the task of setting up a buffer, writing commands to it, and 
 * queuing the buffer in the ring. 
 */

#define DMALOCALS				\
	drm_mach64_freelist_t *_entry = NULL;	\
	struct drm_buf *_buf = NULL;		\
	u32 *_buf_wptr; int _outcount

#define GETBUFPTR( __buf )						\
((dev_priv->is_pci) ?							\
	((u32 *)(__buf)->address) :					\
	((u32 *)((char *)dev_priv->dev_buffers->handle + (__buf)->offset)))

#define GETBUFADDR( __buf ) ((u32)(__buf)->bus_address)

#define GETRINGOFFSET() (_entry->ring_ofs)

static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t *
						    dev_priv,
						    drm_mach64_freelist_t **
						    entry, struct drm_buf * buf)
{
	struct list_head *ptr;
#if MACH64_EXTRA_CHECKING
	if (list_empty(&dev_priv->pending)) {
		DRM_ERROR("Empty pending list in \n");
		return -EINVAL;
	}
#endif
	ptr = dev_priv->pending.prev;
	*entry = list_entry(ptr, drm_mach64_freelist_t, list);
	while ((*entry)->buf != buf) {
		if (ptr == &dev_priv->pending) {
			return -EFAULT;
		}
		ptr = ptr->prev;
		*entry = list_entry(ptr, drm_mach64_freelist_t, list);
	}
	return 0;
}

#define DMASETPTR( _p )				\
do {						\
	_buf = (_p);				\
	_outcount = 0;				\
	_buf_wptr = GETBUFPTR( _buf );		\
} while(0)

/* FIXME: use a private set of smaller buffers for state emits, clears, and swaps? */
#define DMAGETPTR( file_priv, dev_priv, n )				\
do {									\
	if ( MACH64_VERBOSE ) {						\
		DRM_INFO( "DMAGETPTR( %d )\n", (n) );			\
	}								\
	_buf = mach64_freelist_get( dev_priv );				\
	if (_buf == NULL) {						\
		DRM_ERROR("couldn't get buffer in DMAGETPTR\n");	\
		return -EAGAIN;					\
	}								\
	if (_buf->pending) {						\
	        DRM_ERROR("pending buf in DMAGETPTR\n");		\
		return -EFAULT;					\
	}								\
	_buf->file_priv = file_priv;					\
	_outcount = 0;							\
									\
        _buf_wptr = GETBUFPTR( _buf );					\
} while (0)

#define DMAOUTREG( reg, val )					\
do {								\
	if ( MACH64_VERBOSE ) {					\
		DRM_INFO( "   DMAOUTREG( 0x%x = 0x%08x )\n",	\
			  reg, val );				\
	}							\
	_buf_wptr[_outcount++] = cpu_to_le32(DMAREG(reg));	\
	_buf_wptr[_outcount++] = cpu_to_le32((val));		\
	_buf->used += 8;					\
} while (0)

#define DMAADVANCE( dev_priv, _discard )				\
	do {								\
		struct list_head *ptr;					\
		int ret;						\
									\
		if ( MACH64_VERBOSE ) {					\
			DRM_INFO( "DMAADVANCE() in \n" );		\
		}							\
									\
		if (_buf->used <= 0) {					\
			DRM_ERROR( "DMAADVANCE(): sending empty buf %d\n", \
				   _buf->idx );				\
			return -EFAULT;					\
		}							\
		if (_buf->pending) {					\
			/* This is a resued buffer, so we need to find it in the pending list */ \
			if ((ret = mach64_find_pending_buf_entry(dev_priv, &_entry, _buf))) { \
				DRM_ERROR( "DMAADVANCE(): couldn't find pending buf %d\n", _buf->idx );	\
				return ret;				\
			}						\
			if (_entry->discard) {				\
				DRM_ERROR( "DMAADVANCE(): sending discarded pending buf %d\n", _buf->idx ); \
				return -EFAULT;				\
			}						\
		} else {						\
			if (list_empty(&dev_priv->placeholders)) {	\
				DRM_ERROR( "DMAADVANCE(): empty placeholder list\n"); \
				return -EFAULT;				\
			}						\
			ptr = dev_priv->placeholders.next;		\
			list_del(ptr);					\
			_entry = list_entry(ptr, drm_mach64_freelist_t, list); \
			_buf->pending = 1;				\
			_entry->buf = _buf;				\
			list_add_tail(ptr, &dev_priv->pending);		\
		}							\
		_entry->discard = (_discard);				\
		if ((ret = mach64_add_buf_to_ring( dev_priv, _entry ))) \
			return ret;					\
	} while (0)

#define DMADISCARDBUF()							\
	do {								\
		if (_entry == NULL) {					\
			int ret;					\
			if ((ret = mach64_find_pending_buf_entry(dev_priv, &_entry, _buf))) { \
				DRM_ERROR( "couldn't find pending buf %d\n", \
					   _buf->idx );			\
				return ret;				\
			}						\
		}							\
		_entry->discard = 1;					\
	} while(0)

#define DMAADVANCEHOSTDATA( dev_priv )					\
	do {								\
		struct list_head *ptr;					\
		int ret;						\
									\
		if ( MACH64_VERBOSE ) {					\
			DRM_INFO( "DMAADVANCEHOSTDATA() in \n" );	\
		}							\
									\
		if (_buf->used <= 0) {					\
			DRM_ERROR( "DMAADVANCEHOSTDATA(): sending empty buf %d\n", _buf->idx );	\
			return -EFAULT;					\
		}							\
		if (list_empty(&dev_priv->placeholders)) {		\
			DRM_ERROR( "empty placeholder list in DMAADVANCEHOSTDATA()\n" ); \
			return -EFAULT;					\
		}							\
									\
		ptr = dev_priv->placeholders.next;			\
		list_del(ptr);						\
		_entry = list_entry(ptr, drm_mach64_freelist_t, list);	\
		_entry->buf = _buf;					\
		_entry->buf->pending = 1;				\
		list_add_tail(ptr, &dev_priv->pending);			\
		_entry->discard = 1;					\
		if ((ret = mach64_add_hostdata_buf_to_ring( dev_priv, _entry ))) \
			return ret;					\
	} while (0)

#endif				/* __MACH64_DRV_H__ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-27 04:03:19 +0000