/* mga_drv.h -- Private header for the Matrox g200/g400 driver * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: Rickard E. (Rik) Faith * Jeff Hartmann * */ #ifndef _MGA_DRV_H_ #define _MGA_DRV_H_ #define MGA_BUF_IN_USE 0 #define MGA_BUF_SWAP_PENDING 1 #define MGA_BUF_FORCE_FIRE 2 #define MGA_BUF_NEEDS_OVERFLOW 3 typedef struct { u_int32_t buffer_status; int num_dwords; int max_dwords; u_int32_t *current_dma_ptr; u_int32_t *head; u_int32_t phys_head; unsigned int prim_age; int sec_used; int idx; } drm_mga_prim_buf_t; typedef struct _drm_mga_freelist { __volatile__ unsigned int age; drm_buf_t *buf; struct _drm_mga_freelist *next; struct _drm_mga_freelist *prev; } drm_mga_freelist_t; #define MGA_IN_DISPATCH 0 #define MGA_IN_FLUSH 1 #define MGA_IN_WAIT 2 #define MGA_IN_GETBUF 3 typedef struct _drm_mga_private { u_int32_t dispatch_status; unsigned int next_prim_age; __volatile__ unsigned int last_prim_age; int reserved_map_idx; int buffer_map_idx; drm_mga_sarea_t *sarea_priv; int primary_size; int warp_ucode_size; int chipset; unsigned int frontOffset; unsigned int backOffset; unsigned int depthOffset; unsigned int textureOffset; unsigned int textureSize; int cpp; unsigned int stride; int sgram; int use_agp; drm_mga_warp_index_t WarpIndex[MGA_MAX_G400_PIPES]; unsigned int WarpPipe; unsigned int vertexsize; atomic_t pending_bufs; void *status_page; unsigned long real_status_page; u_int8_t *ioremap; drm_mga_prim_buf_t **prim_bufs; drm_mga_prim_buf_t *next_prim; drm_mga_prim_buf_t *last_prim; drm_mga_prim_buf_t *current_prim; int current_prim_idx; drm_mga_freelist_t *head; drm_mga_freelist_t *tail; int flush_queue; /* Processes waiting until flush */ int wait_queue; /* Processes waiting until interrupt */ int buf_queue; /* Processes waiting for a free buf */ /* Some validated register values: */ u_int32_t mAccess; } drm_mga_private_t; /* mga_drv.c */ extern int mga_init(device_t); extern void mga_cleanup(device_t); extern d_ioctl_t mga_version; extern d_open_t mga_open; extern d_close_t mga_close; extern d_ioctl_t mga_ioctl; extern d_ioctl_t mga_unlock; /* mga_dma.c */ extern int mga_dma_schedule(drm_device_t *dev, int locked); extern int mga_irq_install(drm_device_t *dev, int irq); extern int mga_irq_uninstall(drm_device_t *dev); extern d_ioctl_t mga_dma; extern d_ioctl_t mga_control; extern d_ioctl_t mga_lock; /* mga_dma_init does init and release */ extern int mga_dma_cleanup(drm_device_t *dev); extern d_ioctl_t mga_dma_init; extern d_ioctl_t mga_flush_ioctl; extern void mga_flush_write_combine(void); extern unsigned int mga_create_sync_tag(drm_device_t *dev); extern drm_buf_t *mga_freelist_get(drm_device_t *dev); extern int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf); extern int mga_advance_primary(drm_device_t *dev); extern void mga_reclaim_buffers(drm_device_t *dev, pid_t pid); /* mga_bufs.c */ extern d_ioctl_t mga_addbufs; extern d_ioctl_t mga_infobufs; extern d_ioctl_t mga_markbufs; extern d_ioctl_t mga_freebufs; extern d_ioctl_t mga_mapbufs; extern d_ioctl_t mga_addmap; /* mga_state.c */ extern d_ioctl_t mga_clear_bufs; extern d_ioctl_t mga_swap_bufs; extern d_ioctl_t mga_iload; extern d_ioctl_t mga_vertex; extern d_ioctl_t mga_indices; /* mga_context.c */ extern d_ioctl_t mga_resctx; extern d_ioctl_t mga_addctx; extern d_ioctl_t mga_modctx; extern d_ioctl_t mga_getctx; extern d_ioctl_t mga_switchctx; extern d_ioctl_t mga_newctx; extern d_ioctl_t mga_rmctx; extern int mga_context_switch(drm_device_t *dev, int old, int new); extern int mga_context_switch_complete(drm_device_t *dev, int new); typedef enum { TT_GENERAL, TT_BLIT, TT_VECTOR, TT_VERTEX } transferType_t; typedef struct { drm_mga_freelist_t *my_freelist; int discard; int dispatched; } drm_mga_buf_priv_t; #define DWGREG0 0x1c00 #define DWGREG0_END 0x1dff #define DWGREG1 0x2c00 #define DWGREG1_END 0x2dff #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) #define ADRINDEX0(r) (u_int8_t)((r - DWGREG0) >> 2) #define ADRINDEX1(r) (u_int8_t)(((r - DWGREG1) >> 2) | 0x80) #define ADRINDEX(r) (ISREG0(r) ? ADRINDEX0(r) : ADRINDEX1(r)) #define MGA_VERBOSE 0 #define MGA_NUM_PRIM_BUFS 8 #define PRIMLOCALS u_int8_t tempIndex[4]; u_int32_t *dma_ptr; u_int32_t phys_head; \ int outcount, num_dwords #define PRIM_OVERFLOW(dev, dev_priv, length) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ if( test_bit(MGA_BUF_NEEDS_OVERFLOW, \ &tmp_buf->buffer_status)) { \ mga_advance_primary(dev); \ mga_dma_schedule(dev, 1); \ tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ } else if( tmp_buf->max_dwords - tmp_buf->num_dwords < length ||\ tmp_buf->sec_used > MGA_DMA_BUF_NR/2) { \ set_bit(MGA_BUF_FORCE_FIRE, &tmp_buf->buffer_status); \ mga_advance_primary(dev); \ mga_dma_schedule(dev, 1); \ tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ } \ if(MGA_VERBOSE) \ DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ dma_ptr = tmp_buf->current_dma_ptr; \ num_dwords = tmp_buf->num_dwords; \ phys_head = tmp_buf->phys_head; \ outcount = 0; \ } while(0) #define PRIMGETPTR(dev_priv) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ if(MGA_VERBOSE) \ DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ dma_ptr = tmp_buf->current_dma_ptr; \ num_dwords = tmp_buf->num_dwords; \ phys_head = tmp_buf->phys_head; \ outcount = 0; \ } while(0) #define PRIMPTR(prim_buf) do { \ if(MGA_VERBOSE) \ DRM_DEBUG("PRIMPTR in %s\n", __FUNCTION__); \ dma_ptr = prim_buf->current_dma_ptr; \ num_dwords = prim_buf->num_dwords; \ phys_head = prim_buf->phys_head; \ outcount = 0; \ } while(0) #define PRIMFINISH(prim_buf) do { \ if (MGA_VERBOSE) { \ DRM_DEBUG( "PRIMFINISH in %s\n", __FUNCTION__); \ if (outcount & 3) \ DRM_DEBUG(" --- truncation\n"); \ } \ prim_buf->num_dwords = num_dwords; \ prim_buf->current_dma_ptr = dma_ptr; \ } while(0) #define PRIMADVANCE(dev_priv) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ if (MGA_VERBOSE) { \ DRM_DEBUG("PRIMADVANCE in %s\n", __FUNCTION__); \ if (outcount & 3) \ DRM_DEBUG(" --- truncation\n"); \ } \ tmp_buf->num_dwords = num_dwords; \ tmp_buf->current_dma_ptr = dma_ptr; \ } while (0) #define PRIMUPDATE(dev_priv) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ tmp_buf->sec_used++; \ } while (0) #define AGEBUF(dev_priv, buf_priv) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ buf_priv->my_freelist->age = tmp_buf->prim_age; \ } while (0) #define PRIMOUTREG(reg, val) do { \ tempIndex[outcount]=ADRINDEX(reg); \ dma_ptr[1+outcount] = val; \ if (MGA_VERBOSE) \ DRM_DEBUG(" PRIMOUT %d: 0x%x -- 0x%x\n", \ num_dwords + 1 + outcount, ADRINDEX(reg), val); \ if( ++outcount == 4) { \ outcount = 0; \ dma_ptr[0] = *(u_int32_t *)tempIndex; \ dma_ptr+=5; \ num_dwords += 5; \ } \ }while (0) /* A reduced set of the mga registers. */ #define MGAREG_MGA_EXEC 0x0100 #define MGAREG_ALPHACTRL 0x2c7c #define MGAREG_AR0 0x1c60 #define MGAREG_AR1 0x1c64 #define MGAREG_AR2 0x1c68 #define MGAREG_AR3 0x1c6c #define MGAREG_AR4 0x1c70 #define MGAREG_AR5 0x1c74 #define MGAREG_AR6 0x1c78 #define MGAREG_CXBNDRY 0x1c80 #define MGAREG_CXLEFT 0x1ca0 #define MGAREG_CXRIGHT 0x1ca4 #define MGAREG_DMAPAD 0x1c54 #define MGAREG_DSTORG 0x2cb8 #define MGAREG_DWGCTL 0x1c00 #define MGAREG_DWGSYNC 0x2c4c #define MGAREG_FCOL 0x1c24 #define MGAREG_FIFOSTATUS 0x1e10 #define MGAREG_FOGCOL 0x1cf4 #define MGAREG_FXBNDRY 0x1c84 #define MGAREG_FXLEFT 0x1ca8 #define MGAREG_FXRIGHT 0x1cac #define MGAREG_ICLEAR 0x1e18 #define MGAREG_IEN 0x1e1c #define MGAREG_LEN 0x1c5c #define MGAREG_MACCESS 0x1c04 #define MGAREG_PITCH 0x1c8c #define MGAREG_PLNWT 0x1c1c #define MGAREG_PRIMADDRESS 0x1e58 #define MGAREG_PRIMEND 0x1e5c #define MGAREG_PRIMPTR 0x1e50 #define MGAREG_SECADDRESS 0x2c40 #define MGAREG_SECEND 0x2c44 #define MGAREG_SETUPADDRESS 0x2cd0 #define MGAREG_SETUPEND 0x2cd4 #define MGAREG_SOFTRAP 0x2c48 #define MGAREG_SRCORG 0x2cb4 #define MGAREG_STATUS 0x1e14 #define MGAREG_STENCIL 0x2cc8 #define MGAREG_STENCILCTL 0x2ccc #define MGAREG_TDUALSTAGE0 0x2cf8 #define MGAREG_TDUALSTAGE1 0x2cfc #define MGAREG_TEXBORDERCOL 0x2c5c #define MGAREG_TEXCTL 0x2c30 #define MGAREG_TEXCTL2 0x2c3c #define MGAREG_TEXFILTER 0x2c58 #define MGAREG_TEXHEIGHT 0x2c2c #define MGAREG_TEXORG 0x2c24 #define MGAREG_TEXORG1 0x2ca4 #define MGAREG_TEXORG2 0x2ca8 #define MGAREG_TEXORG3 0x2cac #define MGAREG_TEXORG4 0x2cb0 #define MGAREG_TEXTRANS 0x2c34 #define MGAREG_TEXTRANSHIGH 0x2c38 #define MGAREG_TEXWIDTH 0x2c28 #define MGAREG_WACCEPTSEQ 0x1dd4 #define MGAREG_WCODEADDR 0x1e6c #define MGAREG_WFLAG 0x1dc4 #define MGAREG_WFLAG1 0x1de0 #define MGAREG_WFLAGNB 0x1e64 #define MGAREG_WFLAGNB1 0x1e08 #define MGAREG_WGETMSB 0x1dc8 #define MGAREG_WIADDR 0x1dc0 #define MGAREG_WIADDR2 0x1dd8 #define MGAREG_WMISC 0x1e70 #define MGAREG_WVRTXSZ 0x1dcc #define MGAREG_YBOT 0x1c9c #define MGAREG_YDST 0x1c90 #define MGAREG_YDSTLEN 0x1c88 #define MGAREG_YDSTORG 0x1c94 #define MGAREG_YTOP 0x1c98 #define MGAREG_ZORG 0x1c0c /* Warp registers */ #define MGAREG_WR0 0x2d00 #define MGAREG_WR1 0x2d04 #define MGAREG_WR2 0x2d08 #define MGAREG_WR3 0x2d0c #define MGAREG_WR4 0x2d10 #define MGAREG_WR5 0x2d14 #define MGAREG_WR6 0x2d18 #define MGAREG_WR7 0x2d1c #define MGAREG_WR8 0x2d20 #define MGAREG_WR9 0x2d24 #define MGAREG_WR10 0x2d28 #define MGAREG_WR11 0x2d2c #define MGAREG_WR12 0x2d30 #define MGAREG_WR13 0x2d34 #define MGAREG_WR14 0x2d38 #define MGAREG_WR15 0x2d3c #define MGAREG_WR16 0x2d40 #define MGAREG_WR17 0x2d44 #define MGAREG_WR18 0x2d48 #define MGAREG_WR19 0x2d4c #define MGAREG_WR20 0x2d50 #define MGAREG_WR21 0x2d54 #define MGAREG_WR22 0x2d58 #define MGAREG_WR23 0x2d5c #define MGAREG_WR24 0x2d60 #define MGAREG_WR25 0x2d64 #define MGAREG_WR26 0x2d68 #define MGAREG_WR27 0x2d6c #define MGAREG_WR28 0x2d70 #define MGAREG_WR29 0x2d74 #define MGAREG_WR30 0x2d78 #define MGAREG_WR31 0x2d7c #define MGAREG_WR32 0x2d80 #define MGAREG_WR33 0x2d84 #define MGAREG_WR34 0x2d88 #define MGAREG_WR35 0x2d8c #define MGAREG_WR36 0x2d90 #define MGAREG_WR37 0x2d94 #define MGAREG_WR38 0x2d98 #define MGAREG_WR39 0x2d9c #define MGAREG_WR40 0x2da0 #define MGAREG_WR41 0x2da4 #define MGAREG_WR42 0x2da8 #define MGAREG_WR43 0x2dac #define MGAREG_WR44 0x2db0 #define MGAREG_WR45 0x2db4 #define MGAREG_WR46 0x2db8 #define MGAREG_WR47 0x2dbc #define MGAREG_WR48 0x2dc0 #define MGAREG_WR49 0x2dc4 #define MGAREG_WR50 0x2dc8 #define MGAREG_WR51 0x2dcc #define MGAREG_WR52 0x2dd0 #define MGAREG_WR53 0x2dd4 #define MGAREG_WR54 0x2dd8 #define MGAREG_WR55 0x2ddc #define MGAREG_WR56 0x2de0 #define MGAREG_WR57 0x2de4 #define MGAREG_WR58 0x2de8 #define MGAREG_WR59 0x2dec #define MGAREG_WR60 0x2df0 #define MGAREG_WR61 0x2df4 #define MGAREG_WR62 0x2df8 #define MGAREG_WR63 0x2dfc #define PDEA_pagpxfer_enable 0x2 #define WIA_wmode_suspend 0x0 #define WIA_wmode_start 0x3 #define WIA_wagp_agp 0x4 #define DC_opcod_line_open 0x0 #define DC_opcod_autoline_open 0x1 #define DC_opcod_line_close 0x2 #define DC_opcod_autoline_close 0x3 #define DC_opcod_trap 0x4 #define DC_opcod_texture_trap 0x6 #define DC_opcod_bitblt 0x8 #define DC_opcod_iload 0x9 #define DC_atype_rpl 0x0 #define DC_atype_rstr 0x10 #define DC_atype_zi 0x30 #define DC_atype_blk 0x40 #define DC_atype_i 0x70 #define DC_linear_xy 0x0 #define DC_linear_linear 0x80 #define DC_zmode_nozcmp 0x0 #define DC_zmode_ze 0x200 #define DC_zmode_zne 0x300 #define DC_zmode_zlt 0x400 #define DC_zmode_zlte 0x500 #define DC_zmode_zgt 0x600 #define DC_zmode_zgte 0x700 #define DC_solid_disable 0x0 #define DC_solid_enable 0x800 #define DC_arzero_disable 0x0 #define DC_arzero_enable 0x1000 #define DC_sgnzero_disable 0x0 #define DC_sgnzero_enable 0x2000 #define DC_shftzero_disable 0x0 #define DC_shftzero_enable 0x4000 #define DC_bop_SHIFT 16 #define DC_trans_SHIFT 20 #define DC_bltmod_bmonolef 0x0 #define DC_bltmod_bmonowf 0x8000000 #define DC_bltmod_bplan 0x2000000 #define DC_bltmod_bfcol 0x4000000 #define DC_bltmod_bu32bgr 0x6000000 #define DC_bltmod_bu32rgb 0xe000000 #define DC_bltmod_bu24bgr 0x16000000 #define DC_bltmod_bu24rgb 0x1e000000 #define DC_pattern_disable 0x/* * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _I915_DRM_H_ #define _I915_DRM_H_ /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. */ #include "drm.h" /* Each region is a minimum of 16k, and there are at most 255 of them. */ #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use * of chars for next/prev indices */ #define I915_LOG_MIN_TEX_REGION_SIZE 14 typedef struct drm_i915_init { enum { I915_INIT_DMA = 0x01, I915_CLEANUP_DMA = 0x02, I915_RESUME_DMA = 0x03, /* Since this struct isn't versioned, just used a new * 'func' code to indicate the presence of dri2 sarea * info. */ I915_INIT_DMA2 = 0x04 } func; unsigned int mmio_offset; int sarea_priv_offset; unsigned int ring_start; unsigned int ring_end; unsigned int ring_size; unsigned int front_offset; unsigned int back_offset; unsigned int depth_offset; unsigned int w; unsigned int h; unsigned int pitch; unsigned int pitch_bits; unsigned int back_pitch; unsigned int depth_pitch; unsigned int cpp; unsigned int chipset; unsigned int sarea_handle; } drm_i915_init_t; typedef struct drm_i915_sarea { struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; int last_upload; /* last time texture was uploaded */ int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ int ctxOwner; /* last context to upload state */ int texAge; int pf_enabled; /* is pageflipping allowed? */ int pf_active; int pf_current_page; /* which buffer is being displayed? */ int perf_boxes; /* performance boxes to be displayed */ int width, height; /* screen size in pixels */ drm_handle_t front_handle; int front_offset; int front_size; drm_handle_t back_handle; int back_offset; int back_size; drm_handle_t depth_handle; int depth_offset; int depth_size; drm_handle_t tex_handle; int tex_offset; int tex_size; int log_tex_granularity; int pitch; int rotation; /* 0, 90, 180 or 270 */ int rotated_offset; int rotated_size; int rotated_pitch; int virtualX, virtualY; unsigned int front_tiled; unsigned int back_tiled; unsigned int depth_tiled; unsigned int rotated_tiled; unsigned int rotated2_tiled; int planeA_x; int planeA_y; int planeA_w; int planeA_h; int planeB_x; int planeB_y; int planeB_w; int planeB_h; /* Triple buffering */ drm_handle_t third_handle; int third_offset; int third_size; unsigned int third_tiled; /* buffer object handles for the static buffers. May change * over the lifetime of the client, though it doesn't in our current * implementation. */ unsigned int front_bo_handle; unsigned int back_bo_handle; unsigned int third_bo_handle; unsigned int depth_bo_handle; } drm_i915_sarea_t; /* Driver specific fence types and classes. */ /* The only fence class we support */ #define DRM_I915_FENCE_CLASS_ACCEL 0 /* Fence type that guarantees read-write flush */ #define DRM_I915_FENCE_TYPE_RW 2 /* MI_FLUSH programmed just before the fence */ #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 /* Flags for perf_boxes */ #define I915_BOX_RING_EMPTY 0x1 #define I915_BOX_FLIP 0x2 #define I915_BOX_WAIT 0x4 #define I915_BOX_TEXTURE_LOAD 0x8 #define I915_BOX_LOST_CONTEXT 0x10 /* I915 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_I915_INIT 0x00 #define DRM_I915_FLUSH 0x01 #define DRM_I915_FLIP 0x02 #define DRM_I915_BATCHBUFFER 0x03 #define DRM_I915_IRQ_EMIT 0x04 #define DRM_I915_IRQ_WAIT 0x05 #define DRM_I915_GETPARAM 0x06 #define DRM_I915_SETPARAM 0x07 #define DRM_I915_ALLOC 0x08 #define DRM_I915_FREE 0x09 #define DRM_I915_INIT_HEAP 0x0a #define DRM_I915_CMDBUFFER 0x0b #define DRM_I915_DESTROY_HEAP 0x0c #define DRM_I915_SET_VBLANK_PIPE 0x0d #define DRM_I915_GET_VBLANK_PIPE 0x0e #define DRM_I915_VBLANK_SWAP 0x0f #define DRM_I915_MMIO 0x10 #define DRM_I915_HWS_ADDR 0x11 #define DRM_I915_EXECBUFFER 0x12 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) #define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio) #define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer) /* Asynchronous page flipping: */ typedef struct drm_i915_flip { /* * This is really talking about planes, and we could rename it * except for the fact that some of the duplicated i915_drm.h files * out there check for HAVE_I915_FLIP and so might pick up this * version. */ int pipes; } drm_i915_flip_t; /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. */ typedef struct drm_i915_batchbuffer { int start; /* agp offset */ int used; /* nr bytes in use */ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ } drm_i915_batchbuffer_t; /* As above, but pass a pointer to userspace buffer which can be * validated by the kernel prior to sending to hardware. */ typedef struct drm_i915_cmdbuffer { char __user *buf; /* pointer to userspace command buffer */ int sz; /* nr bytes in buf */ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ } drm_i915_cmdbuffer_t; /* Userspace can request & wait on irq's: */ typedef struct drm_i915_irq_emit { int __user *irq_seq; } drm_i915_irq_emit_t; typedef struct drm_i915_irq_wait { int irq_seq; } drm_i915_irq_wait_t; /* Ioctl to query kernel params: */ #define I915_PARAM_IRQ_ACTIVE 1 #define I915_PARAM_ALLOW_BATCHBUFFER 2 #define I915_PARAM_LAST_DISPATCH 3 #define I915_PARAM_CHIPSET_ID 4 typedef struct drm_i915_getparam { int param; int __user *value; } drm_i915_getparam_t; /* Ioctl to set kernel params: */ #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 typedef struct drm_i915_setparam { int param; int value; } drm_i915_setparam_t; /* A memory manager for regions of shared memory: */ #define I915_MEM_REGION_AGP 1 typedef struct drm_i915_mem_alloc { int region; int alignment; int size; int __user *region_offset; /* offset from start of fb or agp */ } drm_i915_mem_alloc_t; typedef struct drm_i915_mem_free { int region; int region_offset; } drm_i915_mem_free_t; typedef struct drm_i915_mem_init_heap { int region; int size; int start; } drm_i915_mem_init_heap_t; /* Allow memory manager to be torn down and re-initialized (eg on * rotate): */ typedef struct drm_i915_mem_destroy_heap { int region; } drm_i915_mem_destroy_heap_t; /* Allow X server to configure which pipes to monitor for vblank signals */ #define DRM_I915_VBLANK_PIPE_A 1 #define DRM_I915_VBLANK_PIPE_B 2 typedef struct drm_i915_vblank_pipe { int pipe; } drm_i915_vblank_pipe_t; /* Schedule buffer swap at given vertical blank: */ typedef struct drm_i915_vblank_swap { drm_drawable_t drawable; enum drm_vblank_seq_type seqtype; unsigned int sequence; } drm_i915_vblank_swap_t; #define I915_MMIO_READ 0 #define I915_MMIO_WRITE 1 #define I915_MMIO_MAY_READ 0x1 #define I915_MMIO_MAY_WRITE 0x2 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0 #define MMIO_REGS_IA_VERTICES_COUNT 1 #define MMIO_REGS_VS_INVOCATION_COUNT 2 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3 #define MMIO_REGS_GS_INVOCATION_COUNT 4 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5 #define MMIO_REGS_CL_INVOCATION_COUNT 6 #define MMIO_REGS_PS_INVOCATION_COUNT 7 #define MMIO_REGS_PS_DEPTH_COUNT 8 #define MMIO_REGS_DOVSTA 9 #define MMIO_REGS_GAMMA 10 #define MMIO_REGS_FENCE 11 #define MMIO_REGS_FENCE_NEW 12 typedef struct drm_i915_mmio_entry { unsigned int flag; unsigned int offset; unsigned int size; } drm_i915_mmio_entry_t; typedef struct drm_i915_mmio { unsigned int read_write:1; unsigned int reg:31; void __user *data; } drm_i915_mmio_t; typedef struct drm_i915_hws_addr { uint64_t addr; } drm_i915_hws_addr_t; /* * Relocation header is 4 uint32_ts * 0 - 32 bit reloc count * 1 - 32-bit relocation type * 2-3 - 64-bit user buffer handle ptr for another list of relocs. */ #define I915_RELOC_HEADER 4 /* * type 0 relocation has 4-uint32_t stride * 0 - offset into buffer * 1 - delta to add in * 2 - buffer handle * 3 - reserved (for optimisations later). */ /* * type 1 relocation has 4-uint32_t stride. * Hangs off the first item in the op list. * Performed after all valiations are done. * Try to group relocs into the same relocatee together for * performance reasons. * 0 - offset into buffer * 1 - delta to add in * 2 - buffer index in op list. * 3 - relocatee index in op list. */ #define I915_RELOC_TYPE_0 0 #define I915_RELOC0_STRIDE 4 #define I915_RELOC_TYPE_1 1 #define I915_RELOC1_STRIDE 4 struct drm_i915_op_arg { uint64_t next; uint64_t reloc_ptr; int handled; unsigned int pad64; union { struct drm_bo_op_req req; struct drm_bo_arg_rep rep; } d; }; struct drm_i915_execbuffer { uint64_t ops_list; uint32_t num_buffers; struct drm_i915_batchbuffer batch; drm_context_t context; /* for lockless use in the future */ struct drm_fence_arg fence_arg; }; #endif /* _I915_DRM_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-26 18:05:08 +0000