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path: root/radeon/radeon_cs_gem.c
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/*
 * Copyright © 2008 Jérôme Glisse
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 */
/*
 * Authors:
 *      Aapo Tahkola <aet@rasterburn.org>
 *      Nicolai Haehnle <prefect_@gmx.net>
 *      Jérôme Glisse <glisse@freedesktop.org>
 */
#include <assert.h>
#include <errno.h>
#include <stdlib.h>
#include <string.h>
#include <pthread.h>
#include <sys/mman.h>
#include <sys/ioctl.h>
#include "radeon_cs.h"
#include "radeon_cs_int.h"
#include "radeon_bo_int.h"
#include "radeon_cs_gem.h"
#include "radeon_bo_gem.h"
#include "drm.h"
#include "xf86drm.h"
#include "xf86atomic.h"
#include "radeon_drm.h"
#include "bof.h"

#define CS_BOF_DUMP 0

struct radeon_cs_manager_gem {
    struct radeon_cs_manager    base;
    uint32_t                    device_id;
    unsigned                    nbof;
};

#pragma pack(1)
struct cs_reloc_gem {
    uint32_t    handle;
    uint32_t    read_domain;
    uint32_t    write_domain;
    uint32_t    flags;
};

#pragma pack()
#define RELOC_SIZE (sizeof(struct cs_reloc_gem) / sizeof(uint32_t))

struct cs_gem {
    struct radeon_cs_int        base;
    struct drm_radeon_cs        cs;
    struct drm_radeon_cs_chunk  chunks[2];
    unsigned                    nrelocs;
    uint32_t                    *relocs;
    struct radeon_bo_int        **relocs_bo;
};

static pthread_mutex_t id_mutex = PTHREAD_MUTEX_INITIALIZER;
static uint32_t cs_id_source = 0;

/**
 * result is undefined if called with ~0
 */
static uint32_t get_first_zero(const uint32_t n)
{
    /* __builtin_ctz returns number of trailing zeros. */
    return 1 << __builtin_ctz(~n);
}

/**
 * Returns a free id for cs.
 * If there is no free id we return zero
 **/
static uint32_t generate_id(void)
{
    uint32_t r = 0;
    pthread_mutex_lock( &id_mutex );
    /* check for free ids */
    if (cs_id_source != ~r) {
        /* find first zero bit */
        r = get_first_zero(cs_id_source);

        /* set id as reserved */
        cs_id_source |= r;
    }
    pthread_mutex_unlock( &id_mutex );
    return r;
}

/**
 * Free the id for later reuse
 **/
static void free_id(uint32_t id)
{
    pthread_mutex_lock( &id_mutex );

    cs_id_source &= ~id;

    pthread_mutex_unlock( &id_mutex );
}

static struct radeon_cs_int *cs_gem_create(struct radeon_cs_manager *csm,
                                       uint32_t ndw)
{
    struct cs_gem *csg;

    /* max cmd buffer size is 64Kb */
    if (ndw > (64 * 1024 / 4)) {
        return NULL;
    }
    csg = (struct cs_gem*)calloc(1, sizeof(struct cs_gem));
    if (csg == NULL) {
        return NULL;
    }
    csg->base.csm = csm;
    csg->base.ndw = 64 * 1024 / 4;
    csg->base.packets = (uint32_t*)calloc(1, 64 * 1024);
    if (csg->base.packets == NULL) {
        free(csg);
        return NULL;
    }
    csg->base.relocs_total_size = 0;
    csg->base.crelocs = 0;
    csg->base.id = generate_id();
    csg->nrelocs = 4096 / (4 * 4) ;
    csg->relocs_bo = (struct radeon_bo_int**)calloc(1,
                                                csg->nrelocs*sizeof(void*));
    if (csg->relocs_bo == NULL) {
        free(csg->base.packets);
        free(csg);
        return NULL;
    }
    csg->base.relocs = csg->relocs = (uint32_t*)calloc(1, 4096);
    if (csg->relocs == NULL) {
        free(csg->relocs_bo);
        free(csg->base.packets);
        free(csg);
        return NULL;
    }
    csg->chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
    csg->chunks[0].length_dw = 0;
    csg->chunks[0].chunk_data = (uint64_t)(uintptr_t)csg->base.packets;
    csg->chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
    csg->chunks[1].length_dw = 0;
    csg->chunks[1].chunk_data = (uint64_t)(uintptr_t)csg->relocs;
    return (struct radeon_cs_int*)csg;
}

static int cs_gem_write_reloc(struct radeon_cs_int *cs,
                              struct radeon_bo *bo,
                              uint32_t read_domain,
                              uint32_t write_domain,
                              uint32_t flags)
{
    struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
    struct cs_gem *csg = (struct cs_gem*)cs;
    struct cs_reloc_gem *reloc;
    uint32_t idx;
    unsigned i;

    assert(boi->space_accounted);

    /* check domains */
    if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
        /* in one CS a bo can only be in read or write domain but not
         * in read & write domain at the same sime
         */
        return -EINVAL;
    }
    if (read_domain == RADEON_GEM_DOMAIN_CPU) {
        return -EINVAL;
    }
    if (write_domain == RADEON_GEM_DOMAIN_CPU) {
        return -EINVAL;
    }
    /* use bit field hash function to determine
       if this bo is for sure not in this cs.*/
    if ((atomic_read((atomic_t *)radeon_gem_get_reloc_in_cs(bo)) & cs->id)) {
        /* check if bo is already referenced.
         * Scanning from end to begin reduces cycles with mesa because
         * it often relocates same shared dma bo again. */
        for(i = cs->crelocs; i != 0;) {
            --i;
            idx = i * RELOC_SIZE;
            reloc = (struct cs_reloc_gem*)&csg->relocs[idx];
            if (reloc->handle == bo->handle) {
                /* Check domains must be in read or write. As we check already
                 * checked that in argument one of the read or write domain was
                 * set we only need to check that if previous reloc as the read
                 * domain set then the read_domain should also be set for this
                 * new relocation.
                 */
                /* the DDX expects to read and write from same pixmap */
                if (write_domain && (reloc->read_domain & write_domain)) {
                    reloc->read_domain = 0;
                    reloc->write_domain = write_domain;
                } else if (read_domain & reloc->write_domain) {
                    reloc->read_domain = 0;
                } else {
                    if (write_domain != reloc->write_domain)
                        return -EINVAL;
                    if (read_domain != reloc->read_domain)
                        return -EINVAL;
                }

                reloc->read_domain |= read_domain;
                reloc->write_domain |= write_domain;
                /* update flags */
                reloc->flags |= (flags & reloc->flags);
                /* write relocation packet */
                radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000);
                radeon_cs_write_dword((struct radeon_cs *)cs, idx);
                return 0;
            }
        }
    }
    /* new relocation */
    if (csg->base.crelocs >= csg->nrelocs) {
        /* allocate more memory (TODO: should use a slab allocatore maybe) */
        uint32_t *tmp, size;
        size = ((csg->nrelocs + 1) * sizeof(struct radeon_bo*));
        tmp = (uint32_t*)realloc(csg->relocs_bo, size);
        if (tmp == NULL) {
            return -ENOMEM;
        }
        csg->relocs_bo = (struct radeon_bo_int **)tmp;
        size = ((csg->nrelocs + 1) * RELOC_SIZE * 4);
        tmp = (uint32_t*)realloc(csg->relocs, size);
        if (tmp == NULL) {
            return -ENOMEM;
        }
        cs->relocs = csg->relocs = tmp;
        csg->nrelocs += 1;
        csg->chunks[1].chunk_data = (uint64_t)(uintptr_t)csg->relocs;
    }
    csg->relocs_bo[csg->base.crelocs] = boi;
    idx = (csg->base.crelocs++) * RELOC_SIZE;
    reloc = (struct cs_reloc_gem*)&csg->relocs[idx];
    reloc->handle = bo->handle;
    reloc->read_domain = read_domain;
    reloc->write_domain = write_domain;
    reloc->flags = flags;
    csg->chunks[1].length_dw += RELOC_SIZE;
    radeon_bo_ref(bo);
    /* bo might be referenced from another context so have to use atomic opertions */
    atomic_add((atomic_t *)radeon_gem_get_reloc_in_cs(bo), cs->id);
    cs->relocs_total_size += boi->size;
    radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000);
    radeon_cs_write_dword((struct radeon_cs *)cs, idx);
    return 0;
}

static int cs_gem_begin(struct radeon_cs_int *cs,
                        uint32_t ndw,
                        const char *file,
                        const char *func,
                        int line)
{

    if (cs->section_ndw) {
        fprintf(stderr, "CS already in a section(%s,%s,%d)\n",
                cs->section_file, cs->section_func, cs->section_line);
        fprintf(stderr, "CS can't start section(%s,%s,%d)\n",
                file, func, line);
        return -EPIPE;
    }
    cs->section_ndw = ndw;
    cs->section_cdw = 0;
    cs->section_file = file;
    cs->section_func = func;
    cs->section_line = line;

    if (cs->cdw + ndw > cs->ndw) {
        uint32_t tmp, *ptr;

        /* round up the required size to a multiple of 1024 */
        tmp = (cs->cdw + ndw + 0x3FF) & (~0x3FF);
        ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
        if (ptr == NULL) {
            return -ENOMEM;
        }
        cs->packets = ptr;
        cs->ndw = tmp;
    }
    return 0;
}

static int cs_gem_end(struct radeon_cs_int *cs,
                      const char *file,
                      const char *func,
                      int line)

{
    if (!cs->section_ndw) {
        fprintf(stderr, "CS no section to end at (%s,%s,%d)\n",
                file, func, line);
        return -EPIPE;
    }
    if (cs->section_ndw != cs->section_cdw) {
        fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
                cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw);
        fprintf(stderr, "CS section end at (%s,%s,%d)\n",
                file, func, line);

        /* We must reset the section even when there is error. */
        cs->section_ndw = 0;
        return -EPIPE;
    }
    cs->section_ndw = 0;
    return 0;
}

static void cs_gem_dump_bof(struct radeon_cs_int *cs)
{
    struct cs_gem *csg = (struct cs_gem*)cs;
    struct radeon_cs_manager_gem *csm;
    bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
    char tmp[256];
    unsigned i;

    csm = (struct radeon_cs_manager_gem *)cs->csm;
    root = device_id = bcs = blob = array = bo = size = handle = NULL;
    root = bof_object();
    if (root == NULL)
        goto out_err;
    device_id = bof_int32(csm->device_id);
    if (device_id == NULL)
        return;
    if (bof_object_set(root, "device_id", device_id))
        goto out_err;
    bof_decref(device_id);
    device_id = NULL;
    /* dump relocs */
    blob = bof_blob(csg->nrelocs * 16, csg->relocs);
    if (blob == NULL)
        goto out_err;
    if (bof_object_set(root, "reloc", blob))
        goto out_err;
    bof_decref(blob);
    blob = NULL;
    /* dump cs */
    blob = bof_blob(cs->cdw * 4, cs->packets);
    if (blob == NULL)
        goto out_err;
    if (bof_object_set(root, "pm4", blob))
        goto out_err;
    bof_decref(blob);
    blob = NULL;
    /* dump bo */
    array = bof_array();
    if (array == NULL)
        goto out_err;
    for (i = 0; i < csg->base.crelocs; i++) {
        bo = bof_object();
        if (bo == NULL)
            goto out_err;
        size = bof_int32(csg->relocs_bo[i]->size);
        if (size == NULL)
            goto out_err;
        if (bof_object_set(bo, "size", size))
            goto out_err;
        bof_decref(size);
        size = NULL;
        handle = bof_int32(csg->relocs_bo[i]->handle);
        if (handle == NULL)
            goto out_err;
        if (bof_object_set(bo, "handle", handle))
            goto out_err;
        bof_decref(handle);
        handle = NULL;
        radeon_bo_map((struct radeon_bo*)csg->relocs_bo[i], 0);
        blob = bof_blob(csg->relocs_bo[i]->size, csg->relocs_bo[i]->ptr);
        radeon_bo_unmap((struct radeon_bo*)csg->relocs_bo[i]);
        if (blob == NULL)
            goto out_err;
        if (bof_object_set(bo, "data", blob))
            goto out_err;
        bof_decref(blob);
        blob = NULL;
        if (bof_array_append(array, bo))
            goto out_err;
        bof_decref(bo);
        bo = NULL;
    }
    if (bof_object_set(root, "bo", array))
        goto out_err;
    sprintf(tmp, "d-0x%04X-%08d.bof", csm->device_id, csm->nbof++);
    bof_dump_file(root, tmp);
out_err:
    bof_decref(blob);
    bof_decref(array);
    bof_decref(bo);
    bof_decref(size);
    bof_decref(handle);
    bof_decref(device_id);
    bof_decref(root);
}

static int cs_gem_emit(struct radeon_cs_int *cs)
{
    struct cs_gem *csg = (struct cs_gem*)cs;
    uint64_t chunk_array[2];
    unsigned i;
    int r;

#if CS_BOF_DUMP
    cs_gem_dump_bof(cs);
#endif
    csg->chunks[0].length_dw = cs->cdw;

    chunk_array[0] = (uint64_t)(uintptr_t)&csg->chunks[0];
    chunk_array[1] = (uint64_t)(uintptr_t)&csg->chunks[1];

    csg->cs.num_chunks = 2;
    csg->cs.chunks = (uint64_t)(uintptr_t)chunk_array;

    r = drmCommandWriteRead(cs->csm->fd, DRM_RADEON_CS,
                            &csg->cs, sizeof(struct drm_radeon_cs));
    for (i = 0; i < csg->base.crelocs; i++) {
        csg->relocs_bo[i]->space_accounted = 0;
        /* bo might be referenced from another context so have to use atomic opertions */
        atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id);
        radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
        csg->relocs_bo[i] = NULL;
    }

    cs->csm->read_used = 0;
    cs->csm->vram_write_used = 0;
    cs->csm->gart_write_used = 0;
    return r;
}

static int cs_gem_destroy(struct radeon_cs_int *cs)
{
    struct cs_gem *csg = (struct cs_gem*)cs;

    free_id(cs->id);
    free(csg->relocs_bo);
    free(cs->relocs);
    free(cs->packets);
    free(cs);
    return 0;
}

static int cs_gem_erase(struct radeon_cs_int *cs)
{
    struct cs_gem *csg = (struct cs_gem*)cs;
    unsigned i;

    if (csg->relocs_bo) {
        for (i = 0; i < csg->base.crelocs; i++) {
            if (csg->relocs_bo[i]) {
                /* bo might be referenced from another context so have to use atomic opertions */
                atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id);
                radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
                csg->relocs_bo[i] = NULL;
            }
        }
    }
    cs->relocs_total_size = 0;
    cs->cdw = 0;
    cs->section_ndw = 0;
    cs->crelocs = 0;
    csg->chunks[0].length_dw = 0;
    csg->chunks[1].length_dw = 0;
    return 0;
}

static int cs_gem_need_flush(struct radeon_cs_int *cs)
{
    return 0; //(cs->relocs_total_size > (32*1024*1024));
}

static void cs_gem_print(struct radeon_cs_int *cs, FILE *file)
{
    struct radeon_cs_manager_gem *csm;
    unsigned int i;

    csm = (struct radeon_cs_manager_gem *)cs->csm;
    fprintf(file, "VENDORID:DEVICEID 0x%04X:0x%04X\n", 0x1002, csm->device_id);
    for (i = 0; i < cs->cdw; i++) {
        fprintf(file, "0x%08X\n", cs->packets[i]);
    }
}

static struct radeon_cs_funcs radeon_cs_gem_funcs = {
    cs_gem_create,
    cs_gem_write_reloc,
    cs_gem_begin,
    cs_gem_end,
    cs_gem_emit,
    cs_gem_destroy,
    cs_gem_erase,
    cs_gem_need_flush,
    cs_gem_print,
};

static int radeon_get_device_id(int fd, uint32_t *device_id)
{
    struct drm_radeon_info info = {};
    int r;

    *device_id = 0;
    info.request = RADEON_INFO_DEVICE_ID;
    info.value = (uintptr_t)device_id;
    r = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info,
                            sizeof(struct drm_radeon_info));
    return r;
}

struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd)
{
    struct radeon_cs_manager_gem *csm;

    csm = calloc(1, sizeof(struct radeon_cs_manager_gem));
    if (csm == NULL) {
        return NULL;
    }
    csm->base.funcs = &radeon_cs_gem_funcs;
    csm->base.fd = fd;
    radeon_get_device_id(fd, &csm->device_id);
    return &csm->base;
}

void radeon_cs_manager_gem_dtor(struct radeon_cs_manager *csm)
{
    free(csm);
}
0 # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ # define R300_POINTSIZE_X_SHIFT 16 # define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) /* The line width is given in multiples of 6. In default mode lines are classified as vertical lines. HO: horizontal VE: vertical or horizontal HO & VE: no classification */ #define R300_RE_LINE_CNT 0x4234 # define R300_LINESIZE_SHIFT 0 # define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ # define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) # define R300_LINE_CNT_HO (1 << 16) # define R300_LINE_CNT_VE (1 << 17) /* Some sort of scale or clamp value for texcoordless textures. */ #define R300_RE_UNK4238 0x4238 #define R300_RE_SHADE_MODEL 0x4278 # define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa # define R300_RE_SHADE_MODEL_FLAT 0x39595 /* Dangerous */ #define R300_RE_POLYGON_MODE 0x4288 # define R300_PM_ENABLED (1 << 0) # define R300_PM_FRONT_POINT (0 << 0) # define R300_PM_BACK_POINT (0 << 0) # define R300_PM_FRONT_LINE (1 << 4) # define R300_PM_FRONT_FILL (1 << 5) # define R300_PM_BACK_LINE (1 << 7) # define R300_PM_BACK_FILL (1 << 8) /* Not sure why there are duplicate of factor and constant values. My best guess so far is that there are seperate zbiases for test and write. Ordering might be wrong. Some of the tests indicate that fgl has a fallback implementation of zbias via pixel shaders. */ #define R300_RE_ZBIAS_T_FACTOR 0x42A4 #define R300_RE_ZBIAS_T_CONSTANT 0x42A8 #define R300_RE_ZBIAS_W_FACTOR 0x42AC #define R300_RE_ZBIAS_W_CONSTANT 0x42B0 /* This register needs to be set to (1<<1) for RV350 to correctly perform depth test (see --vb-triangles in r300_demo) Don't know about other chips. - Vladimir This is set to 3 when GL_POLYGON_OFFSET_FILL is on. My guess is that there are two bits for each zbias primitive (FILL, LINE, POINT). One to enable depth test and one for depth write. Yet this doesnt explain why depth writes work ... */ #define R300_RE_OCCLUSION_CNTL 0x42B4 # define R300_OCCLUSION_ON (1<<1) #define R300_RE_CULL_CNTL 0x42B8 # define R300_CULL_FRONT (1 << 0) # define R300_CULL_BACK (1 << 1) # define R300_FRONT_FACE_CCW (0 << 2) # define R300_FRONT_FACE_CW (1 << 2) /* BEGIN: Rasterization / Interpolators - many guesses // 0_UNKNOWN_18 has always been set except for clear operations. // TC_CNT is the number of incoming texture coordinate sets (i.e. it depends // on the vertex program, *not* the fragment program) */ #define R300_RS_CNTL_0 0x4300 # define R300_RS_CNTL_TC_CNT_SHIFT 2 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2) # define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */ # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */ #define R300_RS_CNTL_1 0x4304 /* gap */ /* Only used for texture coordinates. // Use the source field to route texture coordinate input from the vertex program // to the desired interpolator. Note that the source field is relative to the // outputs the vertex program *actually* writes. If a vertex program only writes // texcoord[1], this will be source index 0. // Set INTERP_USED on all interpolators that produce data used by the // fragment program. INTERP_USED looks like a swizzling mask, but // I haven't seen it used that way. // // Note: The _UNKNOWN constants are always set in their respective register. // I don't know if this is necessary. */ #define R300_RS_INTERP_0 0x4310 #define R300_RS_INTERP_1 0x4314 # define R300_RS_INTERP_1_UNKNOWN 0x40 #define R300_RS_INTERP_2 0x4318 # define R300_RS_INTERP_2_UNKNOWN 0x80 #define R300_RS_INTERP_3 0x431C # define R300_RS_INTERP_3_UNKNOWN 0xC0 #define R300_RS_INTERP_4 0x4320 #define R300_RS_INTERP_5 0x4324 #define R300_RS_INTERP_6 0x4328 #define R300_RS_INTERP_7 0x432C # define R300_RS_INTERP_SRC_SHIFT 2 # define R300_RS_INTERP_SRC_MASK (7 << 2) # define R300_RS_INTERP_USED 0x00D10000 /* These DWORDs control how vertex data is routed into fragment program // registers, after interpolators. */ #define R300_RS_ROUTE_0 0x4330 #define R300_RS_ROUTE_1 0x4334 #define R300_RS_ROUTE_2 0x4338 #define R300_RS_ROUTE_3 0x433C /* GUESS */ #define R300_RS_ROUTE_4 0x4340 /* GUESS */ #define R300_RS_ROUTE_5 0x4344 /* GUESS */ #define R300_RS_ROUTE_6 0x4348 /* GUESS */ #define R300_RS_ROUTE_7 0x434C /* GUESS */ # define R300_RS_ROUTE_SOURCE_INTERP_0 0 # define R300_RS_ROUTE_SOURCE_INTERP_1 1 # define R300_RS_ROUTE_SOURCE_INTERP_2 2 # define R300_RS_ROUTE_SOURCE_INTERP_3 3 # define R300_RS_ROUTE_SOURCE_INTERP_4 4 # define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ # define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ # define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ # define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ # define R300_RS_ROUTE_DEST_SHIFT 6 # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ /* Special handling for color: When the fragment program uses color, // the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the // color register index. */ # define R300_RS_ROUTE_0_COLOR (1 << 14) # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ /* As above, but for secondary color */ # define R300_RS_ROUTE_1_COLOR1 (1 << 14) # define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 # define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) /* END */ /* BEGIN: Scissors and cliprects // There are four clipping rectangles. Their corner coordinates are inclusive. // Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending // on whether the pixel is inside cliprects 0-3, respectively. For example, // if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned // the number 3 (binary 0011). // Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, // the pixel is rasterized. // // In addition to this, there is a scissors rectangle. Only pixels inside the // scissors rectangle are drawn. (coordinates are inclusive) // // For some reason, the top-left corner of the framebuffer is at (1440, 1440) // for the purpose of clipping and scissors. */ #define R300_RE_CLIPRECT_TL_0 0x43B0 #define R300_RE_CLIPRECT_BR_0 0x43B4 #define R300_RE_CLIPRECT_TL_1 0x43B8 #define R300_RE_CLIPRECT_BR_1 0x43BC #define R300_RE_CLIPRECT_TL_2 0x43C0 #define R300_RE_CLIPRECT_BR_2 0x43C4 #define R300_RE_CLIPRECT_TL_3 0x43C8 #define R300_RE_CLIPRECT_BR_3 0x43CC # define R300_CLIPRECT_OFFSET 1440 # define R300_CLIPRECT_MASK 0x1FFF # define R300_CLIPRECT_X_SHIFT 0 # define R300_CLIPRECT_X_MASK (0x1FFF << 0) # define R300_CLIPRECT_Y_SHIFT 13 # define R300_CLIPRECT_Y_MASK (0x1FFF << 13) #define R300_RE_CLIPRECT_CNTL 0x43D0 # define R300_CLIP_OUT (1 << 0) # define R300_CLIP_0 (1 << 1) # define R300_CLIP_1 (1 << 2) # define R300_CLIP_10 (1 << 3) # define R300_CLIP_2 (1 << 4) # define R300_CLIP_20 (1 << 5) # define R300_CLIP_21 (1 << 6) # define R300_CLIP_210 (1 << 7) # define R300_CLIP_3 (1 << 8) # define R300_CLIP_30 (1 << 9) # define R300_CLIP_31 (1 << 10) # define R300_CLIP_310 (1 << 11) # define R300_CLIP_32 (1 << 12) # define R300_CLIP_320 (1 << 13) # define R300_CLIP_321 (1 << 14) # define R300_CLIP_3210 (1 << 15) /* gap */ #define R300_RE_SCISSORS_TL 0x43E0 #define R300_RE_SCISSORS_BR 0x43E4 # define R300_SCISSORS_OFFSET 1440 # define R300_SCISSORS_X_SHIFT 0 # define R300_SCISSORS_X_MASK (0x1FFF << 0) # define R300_SCISSORS_Y_SHIFT 13 # define R300_SCISSORS_Y_MASK (0x1FFF << 13) /* END */ /* BEGIN: Texture specification // The texture specification dwords are grouped by meaning and not by texture unit. // This means that e.g. the offset for texture image unit N is found in register // TX_OFFSET_0 + (4*N) */ #define R300_TX_FILTER_0 0x4400 # define R300_TX_REPEAT 0 # define R300_TX_MIRRORED 1 # define R300_TX_CLAMP 4 # define R300_TX_CLAMP_TO_EDGE 2 # define R300_TX_CLAMP_TO_BORDER 6 # define R300_TX_WRAP_S_SHIFT 0 # define R300_TX_WRAP_S_MASK (7 << 0) # define R300_TX_WRAP_T_SHIFT 3 # define R300_TX_WRAP_T_MASK (7 << 3) # define R300_TX_WRAP_Q_SHIFT 6 # define R300_TX_WRAP_Q_MASK (7 << 6) # define R300_TX_MAG_FILTER_NEAREST (1 << 9) # define R300_TX_MAG_FILTER_LINEAR (2 << 9) # define R300_TX_MAG_FILTER_MASK (3 << 9) # define R300_TX_MIN_FILTER_NEAREST (1 << 11) # define R300_TX_MIN_FILTER_LINEAR (2 << 11) # define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11) # define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11) # define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) # define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) /* NOTE: NEAREST doesnt seem to exist. Im not seting MAG_FILTER_MASK and (3 << 11) on for all anisotropy modes because that would void selected mag filter */ # define R300_TX_MIN_FILTER_ANISO_NEAREST ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) # define R300_TX_MIN_FILTER_ANISO_LINEAR ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST ((1 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR ((2 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) # define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) # define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) # define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) # define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) # define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) # define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) # define R300_TX_MAX_ANISO_MASK (14 << 21) #define R300_TX_UNK1_0 0x4440 # define R300_LOD_BIAS_MASK 0x1fff #define R300_TX_SIZE_0 0x4480 # define R300_TX_WIDTHMASK_SHIFT 0 # define R300_TX_WIDTHMASK_MASK (2047 << 0) # define R300_TX_HEIGHTMASK_SHIFT 11 # define R300_TX_HEIGHTMASK_MASK (2047 << 11) # define R300_TX_UNK23 (1 << 23) # define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ # define R300_TX_SIZE_MASK (15 << 26) #define R300_TX_FORMAT_0 0x44C0 /* The interpretation of the format word by Wladimir van der Laan */ /* The X, Y, Z and W refer to the layout of the components. They are given meanings as R, G, B and Alpha by the swizzle specification */ # define R300_TX_FORMAT_X8 0x0 # define R300_TX_FORMAT_X16 0x1 # define R300_TX_FORMAT_Y4X4 0x2 # define R300_TX_FORMAT_Y8X8 0x3 # define R300_TX_FORMAT_Y16X16 0x4 # define R300_TX_FORMAT_Z3Y3X2 0x5 # define R300_TX_FORMAT_Z5Y6X5 0x6 # define R300_TX_FORMAT_Z6Y5X5 0x7 # define R300_TX_FORMAT_Z11Y11X10 0x8 # define R300_TX_FORMAT_Z10Y11X11 0x9 # define R300_TX_FORMAT_W4Z4Y4X4 0xA # define R300_TX_FORMAT_W1Z5Y5X5 0xB # define R300_TX_FORMAT_W8Z8Y8X8 0xC # define R300_TX_FORMAT_W2Z10Y10X10 0xD # define R300_TX_FORMAT_W16Z16Y16X16 0xE # define R300_TX_FORMAT_DXT1 0xF # define R300_TX_FORMAT_DXT3 0x10 # define R300_TX_FORMAT_DXT5 0x11 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ /* 0x16 - some 16 bit green format.. ?? */ # define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ /* gap */ /* Floating point formats */ /* Note - hardware supports both 16 and 32 bit floating point */ # define R300_TX_FORMAT_FL_I16 0x18 # define R300_TX_FORMAT_FL_I16A16 0x19 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A # define R300_TX_FORMAT_FL_I32 0x1B # define R300_TX_FORMAT_FL_I32A32 0x1C # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D /* alpha modes, convenience mostly */ /* if you have alpha, pick constant appropriate to the number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ # define R300_TX_FORMAT_ALPHA_1CH 0x000 # define R300_TX_FORMAT_ALPHA_2CH 0x200 # define R300_TX_FORMAT_ALPHA_4CH 0x600 # define R300_TX_FORMAT_ALPHA_NONE 0xA00 /* Swizzling */ /* constants */ # define R300_TX_FORMAT_X 0 # define R300_TX_FORMAT_Y 1 # define R300_TX_FORMAT_Z 2 # define R300_TX_FORMAT_W 3 # define R300_TX_FORMAT_ZERO 4 # define R300_TX_FORMAT_ONE 5 # define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */ # define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */ # define R300_TX_FORMAT_B_SHIFT 18 # define R300_TX_FORMAT_G_SHIFT 15 # define R300_TX_FORMAT_R_SHIFT 12 # define R300_TX_FORMAT_A_SHIFT 9 /* Convenience macro to take care of layout and swizzling */ # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) (\ ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ | (R300_TX_FORMAT_##FMT) \ ) /* These can be ORed with result of R300_EASY_TX_FORMAT() */ /* We don't really know what they do. Take values from a constant color ? */ # define R300_TX_FORMAT_CONST_X (1<<5) # define R300_TX_FORMAT_CONST_Y (2<<5) # define R300_TX_FORMAT_CONST_Z (4<<5) # define R300_TX_FORMAT_CONST_W (8<<5) # define R300_TX_FORMAT_YUV_MODE 0x00800000 #define R300_TX_OFFSET_0 0x4540 /* BEGIN: Guess from R200 */ # define R300_TXO_ENDIAN_NO_SWAP (0 << 0) # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) # define R300_TXO_OFFSET_MASK 0xffffffe0 # define R300_TXO_OFFSET_SHIFT 5 /* END */ #define R300_TX_UNK4_0 0x4580 #define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } /* END */ /* BEGIN: Fragment program instruction set // Fragment programs are written directly into register space. // There are separate instruction streams for texture instructions and ALU // instructions. // In order to synchronize these streams, the program is divided into up // to 4 nodes. Each node begins with a number of TEX operations, followed // by a number of ALU operations. // The first node can have zero TEX ops, all subsequent nodes must have at least // one TEX ops. // All nodes must have at least one ALU op. // // The index of the last node is stored in PFS_CNTL_0: A value of 0 means // 1 node, a value of 3 means 4 nodes. // The total amount of instructions is defined in PFS_CNTL_2. The offsets are // offsets into the respective instruction streams, while *_END points to the // last instruction relative to this offset. */ #define R300_PFS_CNTL_0 0x4600 # define R300_PFS_CNTL_LAST_NODES_SHIFT 0 # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) #define R300_PFS_CNTL_1 0x4604 /* There is an unshifted value here which has so far always been equal to the // index of the highest used temporary register. */ #define R300_PFS_CNTL_2 0x4608 # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) # define R300_PFS_CNTL_ALU_END_SHIFT 6 # define R300_PFS_CNTL_ALU_END_MASK (63 << 0) # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ # define R300_PFS_CNTL_TEX_END_SHIFT 18 # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ /* gap */ /* Nodes are stored backwards. The last active node is always stored in // PFS_NODE_3. // Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The // first node is stored in NODE_2, the second node is stored in NODE_3. // // Offsets are relative to the master offset from PFS_CNTL_2. // LAST_NODE is set for the last node, and only for the last node. */ #define R300_PFS_NODE_0 0x4610 #define R300_PFS_NODE_1 0x4614 #define R300_PFS_NODE_2 0x4618 #define R300_PFS_NODE_3 0x461C # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0 # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0) # define R300_PFS_NODE_ALU_END_SHIFT 6 # define R300_PFS_NODE_ALU_END_MASK (63 << 6) # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12 # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) # define R300_PFS_NODE_TEX_END_SHIFT 17 # define R300_PFS_NODE_TEX_END_MASK (31 << 17) # define R300_PFS_NODE_LAST_NODE (1 << 22) /* TEX // As far as I can tell, texture instructions cannot write into output // registers directly. A subsequent ALU instruction is always necessary, // even if it's just MAD o0, r0, 1, 0 */ #define R300_PFS_TEXI_0 0x4620 # define R300_FPITX_SRC_SHIFT 0 # define R300_FPITX_SRC_MASK (31 << 0) # define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ # define R300_FPITX_DST_SHIFT 6 # define R300_FPITX_DST_MASK (31 << 6) # define R300_FPITX_IMAGE_SHIFT 11 # define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ /* Unsure if these are opcodes, or some kind of bitfield, but this is how * they were set when I checked */ # define R300_FPITX_OPCODE_SHIFT 15 # define R300_FPITX_OP_TEX 1 # define R300_FPITX_OP_TXP 3 # define R300_FPITX_OP_TXB 4 /* ALU // The ALU instructions register blocks are enumerated according to the order // in which fglrx. I assume there is space for 64 instructions, since // each block has space for a maximum of 64 DWORDs, and this matches reported // native limits. // // The basic functional block seems to be one MAD for each color and alpha, // and an adder that adds all components after the MUL. // - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands // - DP4: Use OUTC_DP4, OUTA_DP4 // - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands // - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands // - CMP: If ARG2 < 0, return ARG1, else return ARG0 // - FLR: use FRC+MAD // - XPD: use MAD+MAD // - SGE, SLT: use MAD+CMP // - RSQ: use ABS modifier for argument // - Use OUTC_REPL_ALPHA to write results of an alpha-only operation (e.g. RCP) // into color register // - apparently, there's no quick DST operation // - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" // - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" // - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" // // Operand selection // First stage selects three sources from the available registers and // constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). // fglrx sorts the three source fields: Registers before constants, // lower indices before higher indices; I do not know whether this is necessary. // fglrx fills unused sources with "read constant 0" // According to specs, you cannot select more than two different constants. // // Second stage selects the operands from the sources. This is defined in // INSTR0 (color) and INSTR2 (alpha). You can also select the special constants // zero and one. // Swizzling and negation happens in this stage, as well. // // Important: Color and alpha seem to be mostly separate, i.e. their sources // selection appears to be fully independent (the register storage is probably // physically split into a color and an alpha section). // However (because of the apparent physical split), there is some interaction // WRT swizzling. If, for example, you want to load an R component into an // Alpha operand, this R component is taken from a *color* source, not from // an alpha source. The corresponding register doesn't even have to appear in // the alpha sources list. (I hope this alll makes sense to you) // // Destination selection // The destination register index is in FPI1 (color) and FPI3 (alpha) together // with enable bits. // There are separate enable bits for writing into temporary registers // (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* /DSTA_OUTPUT). // You can write to both at once, or not write at all (the same index // must be used for both). // // Note: There is a special form for LRP // - Argument order is the same as in ARB_fragment_program. // - Operation is MAD // - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP // - Set FPI0/FPI2_SPECIAL_LRP // Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD */ #define R300_PFS_INSTR1_0 0x46C0 # define R300_FPI1_SRC0C_SHIFT 0 # define R300_FPI1_SRC0C_MASK (31 << 0) # define R300_FPI1_SRC0C_CONST (1 << 5) # define R300_FPI1_SRC1C_SHIFT 6 # define R300_FPI1_SRC1C_MASK (31 << 6) # define R300_FPI1_SRC1C_CONST (1 << 11) # define R300_FPI1_SRC2C_SHIFT 12 # define R300_FPI1_SRC2C_MASK (31 << 12) # define R300_FPI1_SRC2C_CONST (1 << 17) # define R300_FPI1_DSTC_SHIFT 18 # define R300_FPI1_DSTC_MASK (31 << 18) # define R300_FPI1_DSTC_REG_X (1 << 23) # define R300_FPI1_DSTC_REG_Y (1 << 24) # define R300_FPI1_DSTC_REG_Z (1 << 25) # define R300_FPI1_DSTC_OUTPUT_X (1 << 26) # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) #define R300_PFS_INSTR3_0 0x47C0 # define R300_FPI3_SRC0A_SHIFT 0 # define R300_FPI3_SRC0A_MASK (31 << 0) # define R300_FPI3_SRC0A_CONST (1 << 5) # define R300_FPI3_SRC1A_SHIFT 6 # define R300_FPI3_SRC1A_MASK (31 << 6) # define R300_FPI3_SRC1A_CONST (1 << 11) # define R300_FPI3_SRC2A_SHIFT 12 # define R300_FPI3_SRC2A_MASK (31 << 12) # define R300_FPI3_SRC2A_CONST (1 << 17) # define R300_FPI3_DSTA_SHIFT 18 # define R300_FPI3_DSTA_MASK (31 << 18) # define R300_FPI3_DSTA_REG (1 << 23) # define R300_FPI3_DSTA_OUTPUT (1 << 24) #define R300_PFS_INSTR0_0 0x48C0 # define R300_FPI0_ARGC_SRC0C_XYZ 0 # define R300_FPI0_ARGC_SRC0C_XXX 1 # define R300_FPI0_ARGC_SRC0C_YYY 2 # define R300_FPI0_ARGC_SRC0C_ZZZ 3 # define R300_FPI0_ARGC_SRC1C_XYZ 4 # define R300_FPI0_ARGC_SRC1C_XXX 5 # define R300_FPI0_ARGC_SRC1C_YYY 6 # define R300_FPI0_ARGC_SRC1C_ZZZ 7 # define R300_FPI0_ARGC_SRC2C_XYZ 8 # define R300_FPI0_ARGC_SRC2C_XXX 9 # define R300_FPI0_ARGC_SRC2C_YYY 10 # define R300_FPI0_ARGC_SRC2C_ZZZ 11 # define R300_FPI0_ARGC_SRC0A 12 # define R300_FPI0_ARGC_SRC1A 13 # define R300_FPI0_ARGC_SRC2A 14 # define R300_FPI0_ARGC_SRC1C_LRP 15 # define R300_FPI0_ARGC_ZERO 20 # define R300_FPI0_ARGC_ONE 21 # define R300_FPI0_ARGC_HALF 22 /* GUESS */ # define R300_FPI0_ARGC_SRC0C_YZX 23 # define R300_FPI0_ARGC_SRC1C_YZX 24 # define R300_FPI0_ARGC_SRC2C_YZX 25 # define R300_FPI0_ARGC_SRC0C_ZXY 26 # define R300_FPI0_ARGC_SRC1C_ZXY 27 # define R300_FPI0_ARGC_SRC2C_ZXY 28 # define R300_FPI0_ARGC_SRC0CA_WZY 29 # define R300_FPI0_ARGC_SRC1CA_WZY 30 # define R300_FPI0_ARGC_SRC2CA_WZY 31 # define R300_FPI0_ARG0C_SHIFT 0 # define R300_FPI0_ARG0C_MASK (31 << 0) # define R300_FPI0_ARG0C_NEG (1 << 5) # define R300_FPI0_ARG0C_ABS (1 << 6) # define R300_FPI0_ARG1C_SHIFT 7 # define R300_FPI0_ARG1C_MASK (31 << 7) # define R300_FPI0_ARG1C_NEG (1 << 12) # define R300_FPI0_ARG1C_ABS (1 << 13) # define R300_FPI0_ARG2C_SHIFT 14 # define R300_FPI0_ARG2C_MASK (31 << 14) # define R300_FPI0_ARG2C_NEG (1 << 19) # define R300_FPI0_ARG2C_ABS (1 << 20) # define R300_FPI0_SPECIAL_LRP (1 << 21) # define R300_FPI0_OUTC_MAD (0 << 23) # define R300_FPI0_OUTC_DP3 (1 << 23) # define R300_FPI0_OUTC_DP4 (2 << 23) # define R300_FPI0_OUTC_MIN (4 << 23) # define R300_FPI0_OUTC_MAX (5 << 23) # define R300_FPI0_OUTC_CMP (8 << 23) # define R300_FPI0_OUTC_FRC (9 << 23) # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) # define R300_FPI0_OUTC_SAT (1 << 30) # define R300_FPI0_UNKNOWN_31 (1 << 31) #define R300_PFS_INSTR2_0 0x49C0 # define R300_FPI2_ARGA_SRC0C_X 0 # define R300_FPI2_ARGA_SRC0C_Y 1 # define R300_FPI2_ARGA_SRC0C_Z 2 # define R300_FPI2_ARGA_SRC1C_X 3 # define R300_FPI2_ARGA_SRC1C_Y 4 # define R300_FPI2_ARGA_SRC1C_Z 5 # define R300_FPI2_ARGA_SRC2C_X 6 # define R300_FPI2_ARGA_SRC2C_Y 7 # define R300_FPI2_ARGA_SRC2C_Z 8 # define R300_FPI2_ARGA_SRC0A 9 # define R300_FPI2_ARGA_SRC1A 10 # define R300_FPI2_ARGA_SRC2A 11 # define R300_FPI2_ARGA_SRC1A_LRP 15 # define R300_FPI2_ARGA_ZERO 16 # define R300_FPI2_ARGA_ONE 17 # define R300_FPI2_ARGA_HALF 18 /* GUESS */ # define R300_FPI2_ARG0A_SHIFT 0 # define R300_FPI2_ARG0A_MASK (31 << 0) # define R300_FPI2_ARG0A_NEG (1 << 5) # define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */ # define R300_FPI2_ARG1A_SHIFT 7 # define R300_FPI2_ARG1A_MASK (31 << 7) # define R300_FPI2_ARG1A_NEG (1 << 12) # define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */ # define R300_FPI2_ARG2A_SHIFT 14 # define R300_FPI2_ARG2A_MASK (31 << 14) # define R300_FPI2_ARG2A_NEG (1 << 19) # define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */ # define R300_FPI2_SPECIAL_LRP (1 << 21) # define R300_FPI2_OUTA_MAD (0 << 23) # define R300_FPI2_OUTA_DP4 (1 << 23) # define R300_FPI2_OUTA_MIN (2 << 23) # define R300_FPI2_OUTA_MAX (3 << 23) # define R300_FPI2_OUTA_CMP (6 << 23) # define R300_FPI2_OUTA_FRC (7 << 23) # define R300_FPI2_OUTA_EX2 (8 << 23) # define R300_FPI2_OUTA_LG2 (9 << 23) # define R300_FPI2_OUTA_RCP (10 << 23) # define R300_FPI2_OUTA_RSQ (11 << 23) # define R300_FPI2_OUTA_SAT (1 << 30) # define R300_FPI2_UNKNOWN_31 (1 << 31) /* END */ /* gap */ #define R300_PP_ALPHA_TEST 0x4BD4 # define R300_REF_ALPHA_MASK 0x000000ff # define R300_ALPHA_TEST_FAIL (0 << 8) # define R300_ALPHA_TEST_LESS (1 << 8) # define R300_ALPHA_TEST_LEQUAL (3 << 8) # define R300_ALPHA_TEST_EQUAL (2 << 8) # define R300_ALPHA_TEST_GEQUAL (6 << 8) # define R300_ALPHA_TEST_GREATER (4 << 8) # define R300_ALPHA_TEST_NEQUAL (5 << 8) # define R300_ALPHA_TEST_PASS (7 << 8) # define R300_ALPHA_TEST_OP_MASK (7 << 8) # define R300_ALPHA_TEST_ENABLE (1 << 11) /* gap */ /* Fragment program parameters in 7.16 floating point */ #define R300_PFS_PARAM_0_X 0x4C00 #define R300_PFS_PARAM_0_Y 0x4C04 #define R300_PFS_PARAM_0_Z 0x4C08 #define R300_PFS_PARAM_0_W 0x4C0C /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */ #define R300_PFS_PARAM_31_X 0x4DF0 #define R300_PFS_PARAM_31_Y 0x4DF4 #define R300_PFS_PARAM_31_Z 0x4DF8 #define R300_PFS_PARAM_31_W 0x4DFC /* Notes: // - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in the application // - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND are set to the same // function (both registers are always set up completely in any case) // - Most blend flags are simply copied from R200 and not tested yet */ #define R300_RB3D_CBLEND 0x4E04 #define R300_RB3D_ABLEND 0x4E08 /* the following only appear in CBLEND */ # define R300_BLEND_ENABLE (1 << 0) # define R300_BLEND_UNKNOWN (3 << 1) # define R300_BLEND_NO_SEPARATE (1 << 3) /* the following are shared between CBLEND and ABLEND */ # define R300_FCN_MASK (3 << 12) # define R300_COMB_FCN_ADD_CLAMP (0 << 12) # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) # define R300_COMB_FCN_SUB_CLAMP (2 << 12) # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) # define R300_SRC_BLEND_GL_ZERO (32 << 16) # define R300_SRC_BLEND_GL_ONE (33 << 16) # define R300_SRC_BLEND_GL_SRC_COLOR (34 << 16) # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) # define R300_SRC_BLEND_GL_DST_COLOR (36 << 16) # define R300_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) # define R300_SRC_BLEND_GL_SRC_ALPHA (38 << 16) # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) # define R300_SRC_BLEND_GL_DST_ALPHA (40 << 16) # define R300_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) # define R300_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) # define R300_SRC_BLEND_MASK (63 << 16) # define R300_DST_BLEND_GL_ZERO (32 << 24) # define R300_DST_BLEND_GL_ONE (33 << 24) # define R300_DST_BLEND_GL_SRC_COLOR (34 << 24) # define R300_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) # define R300_DST_BLEND_GL_DST_COLOR (36 << 24) # define R300_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) # define R300_DST_BLEND_GL_SRC_ALPHA (38 << 24) # define R300_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) # define R300_DST_BLEND_GL_DST_ALPHA (40 << 24) # define R300_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) # define R300_DST_BLEND_MASK (63 << 24) #define R300_RB3D_COLORMASK 0x4E0C # define R300_COLORMASK0_B (1<<0) # define R300_COLORMASK0_G (1<<1) # define R300_COLORMASK0_R (1<<2) # define R300_COLORMASK0_A (1<<3) /* gap */ #define R300_RB3D_COLOROFFSET0 0x4E28 # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ /* gap */ /* Bit 16: Larger tiles // Bit 17: 4x2 tiles // Bit 18: Extremely weird tile like, but some pixels duplicated? */ #define R300_RB3D_COLORPITCH0 0x4E38 # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ # define R300_COLOR_FORMAT_RGB565 (2 << 22) # define R300_COLOR_FORMAT_ARGB8888 (3 << 22) #define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ /* gap */ /* Guess by Vladimir. // Set to 0A before 3D operations, set to 02 afterwards. */ #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C # define R300_RB3D_DSTCACHE_02 0x00000002 # define R300_RB3D_DSTCACHE_0A 0x0000000A /* gap */ /* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */ /* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */ #define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 # define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */ # define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */ # define R300_RB3D_Z_TEST 0x00000012 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 # define R300_RB3D_Z_WRITE_ONLY 0x00000006 # define R300_RB3D_Z_TEST 0x00000012 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 # define R300_RB3D_Z_WRITE_ONLY 0x00000006 # define R300_RB3D_STENCIL_ENABLE 0x00000001 #define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04 /* functions */ # define R300_ZS_NEVER 0 # define R300_ZS_LESS 1 # define R300_ZS_LEQUAL 2 # define R300_ZS_EQUAL 3 # define R300_ZS_GEQUAL 4 # define R300_ZS_GREATER 5 # define R300_ZS_NOTEQUAL 6 # define R300_ZS_ALWAYS 7 # define R300_ZS_MASK 7 /* operations */ # define R300_ZS_KEEP 0 # define R300_ZS_ZERO 1 # define R300_ZS_REPLACE 2 # define R300_ZS_INCR 3 # define R300_ZS_DECR 4 # define R300_ZS_INVERT 5 # define R300_ZS_INCR_WRAP 6 # define R300_ZS_DECR_WRAP 7 /* front and back refer to operations done for front and back faces, i.e. separate stencil function support */ # define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 # define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 # define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 # define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 # define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 # define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 # define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 # define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 # define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 #define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 # define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 # define R300_RB3D_ZS2_STENCIL_MASK 0xFF # define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 # define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 /* gap */ #define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 # define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) # define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) /* gap */ #define R300_RB3D_DEPTHOFFSET 0x4F20 #define R300_RB3D_DEPTHPITCH 0x4F24 # define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ # define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ # define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ # define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ /* BEGIN: Vertex program instruction set // Every instruction is four dwords long: // DWORD 0: output and opcode // DWORD 1: first argument // DWORD 2: second argument // DWORD 3: third argument // // Notes: // - ABS r, a is implemented as MAX r, a, -a // - MOV is implemented as ADD to zero // - XPD is implemented as MUL + MAD // - FLR is implemented as FRC + ADD // - apparently, fglrx tries to schedule instructions so that there is at least // one instruction between the write to a temporary and the first read // from said temporary; however, violations of this scheduling are allowed // - register indices seem to be unrelated with OpenGL aliasing to conventional state // - only one attribute and one parameter can be loaded at a time; however, the // same attribute/parameter can be used for more than one argument // - the second software argument for POW is the third hardware argument (no idea why) // - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 // // There is some magic surrounding LIT: // The single argument is replicated across all three inputs, but swizzled: // First argument: xyzy // Second argument: xyzx // Third argument: xyzw // Whenever the result is used later in the fragment program, fglrx forces x and w // to be 1.0 in the input selection; I don't know whether this is strictly necessary */ #define R300_VPI_OUT_OP_DOT (1 << 0) #define R300_VPI_OUT_OP_MUL (2 << 0) #define R300_VPI_OUT_OP_ADD (3 << 0) #define R300_VPI_OUT_OP_MAD (4 << 0) #define R300_VPI_OUT_OP_DST (5 << 0) #define R300_VPI_OUT_OP_FRC (6 << 0) #define R300_VPI_OUT_OP_MAX (7 << 0) #define R300_VPI_OUT_OP_MIN (8 << 0) #define R300_VPI_OUT_OP_SGE (9 << 0) #define R300_VPI_OUT_OP_SLT (10 << 0) #define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ #define R300_VPI_OUT_OP_EXP (65 << 0) #define R300_VPI_OUT_OP_LOG (66 << 0) #define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */ #define R300_VPI_OUT_OP_LIT (68 << 0) #define R300_VPI_OUT_OP_POW (69 << 0) #define R300_VPI_OUT_OP_RCP (70 << 0) #define R300_VPI_OUT_OP_RSQ (72 << 0) #define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ #define R300_VPI_OUT_OP_EX2 (75 << 0) #define R300_VPI_OUT_OP_LG2 (76 << 0) #define R300_VPI_OUT_OP_MAD_2 (128 << 0) #define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */ #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) #define R300_VPI_OUT_REG_INDEX_SHIFT 13 #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */ #define R300_VPI_OUT_WRITE_X (1 << 20) #define R300_VPI_OUT_WRITE_Y (1 << 21) #define R300_VPI_OUT_WRITE_Z (1 << 22) #define R300_VPI_OUT_WRITE_W (1 << 23) #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0) #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) #define R300_VPI_IN_REG_CLASS_NONE (9 << 0) #define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */ #define R300_VPI_IN_REG_INDEX_SHIFT 5 #define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */ /* The R300 can select components from the input register arbitrarily. // Use the following constants, shifted by the component shift you // want to select */ #define R300_VPI_IN_SELECT_X 0 #define R300_VPI_IN_SELECT_Y 1 #define R300_VPI_IN_SELECT_Z 2 #define R300_VPI_IN_SELECT_W 3 #define R300_VPI_IN_SELECT_ZERO 4 #define R300_VPI_IN_SELECT_ONE 5 #define R300_VPI_IN_SELECT_MASK 7 #define R300_VPI_IN_X_SHIFT 13 #define R300_VPI_IN_Y_SHIFT 16 #define R300_VPI_IN_Z_SHIFT 19 #define R300_VPI_IN_W_SHIFT 22 #define R300_VPI_IN_NEG_X (1 << 25) #define R300_VPI_IN_NEG_Y (1 << 26) #define R300_VPI_IN_NEG_Z (1 << 27) #define R300_VPI_IN_NEG_W (1 << 28) /* END */ //BEGIN: Packet 3 commands // A primitive emission dword. #define R300_PRIM_TYPE_NONE (0 << 0) #define R300_PRIM_TYPE_POINT (1 << 0) #define R300_PRIM_TYPE_LINE (2 << 0) #define R300_PRIM_TYPE_LINE_STRIP (3 << 0) #define R300_PRIM_TYPE_TRI_LIST (4 << 0) #define R300_PRIM_TYPE_TRI_FAN (5 << 0) #define R300_PRIM_TYPE_TRI_STRIP (6 << 0) #define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) #define R300_PRIM_TYPE_RECT_LIST (8 << 0) #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) #define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200) #define R300_PRIM_TYPE_LINE_LOOP (12 << 0) #define R300_PRIM_TYPE_QUADS (13 << 0) #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) #define R300_PRIM_TYPE_POLYGON (15 << 0) #define R300_PRIM_TYPE_MASK 0xF #define R300_PRIM_WALK_IND (1 << 4) #define R300_PRIM_WALK_LIST (2 << 4) #define R300_PRIM_WALK_RING (3 << 4) #define R300_PRIM_WALK_MASK (3 << 4) #define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200) #define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS #define R300_PRIM_NUM_VERTICES_SHIFT 16 // Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. // Two parameter dwords: // 0. The first parameter appears to be always 0 // 1. The second parameter is a standard primitive emission dword. #define R300_PACKET3_3D_DRAW_VBUF 0x00002800 // Specify the full set of vertex arrays as (address, stride). // The first parameter is the number of vertex arrays specified. // The rest of the command is a variable length list of blocks, where // each block is three dwords long and specifies two arrays. // The first dword of a block is split into two words, the lower significant // word refers to the first array, the more significant word to the second // array in the block. // The low byte of each word contains the size of an array entry in dwords, // the high byte contains the stride of the array. // The second dword of a block contains the pointer to the first array, // the third dword of a block contains the pointer to the second array. // Note that if the total number of arrays is odd, the third dword of // the last block is omitted. #define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 #define R300_PACKET3_INDX_BUFFER 0x00003300 # define R300_EB_UNK1_SHIFT 24 # define R300_EB_UNK1 (0x80<<24) # define R300_EB_UNK2 0x0810 #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 //END #endif /* _R300_REG_H */