linux - renesas/drm.git - libdrm, cloned from git://anongit.freedesktop.org/mesa/drm

summary refs log tree commit diff

path: root/linux

Mode	Name	Size
-rw-r--r--	Config.in	599	log plain
-rw-r--r--	Makefile.kernel	1258	log plain
-rw-r--r--	Makefile.linux	8644	log plain
-rw-r--r--	README.drm	1850	log plain
-rw-r--r--	ati_pcigart.h	5217	log plain
-rw-r--r--	drm.h	18742	log plain
-rw-r--r--	drmP.h	30919	log plain
-rw-r--r--	drm_agpsupport.h	11254	log plain
-rw-r--r--	drm_auth.h	4497	log plain
-rw-r--r--	drm_bufs.h	29431	log plain
-rw-r--r--	drm_context.h	19726	log plain
-rw-r--r--	drm_dma.h	14632	log plain
-rw-r--r--	drm_drawable.h	1930	log plain
-rw-r--r--	drm_drv.h	28261	log plain
-rw-r--r--	drm_fops.h	6009	log plain
-rw-r--r--	drm_init.h	3733	log plain
-rw-r--r--	drm_ioctl.h	6621	log plain
-rw-r--r--	drm_lists.h	5850	log plain
-rw-r--r--	drm_lock.h	6699	log plain
-rw-r--r--	drm_memory.h	11840	log plain
-rw-r--r--	drm_proc.h	17839	log plain
-rw-r--r--	drm_scatter.h	6120	log plain
-rw-r--r--	drm_stub.h	4632	log plain
-rw-r--r--	drm_vm.h	14030	log plain
-rw-r--r--	gamma.h	3042	log plain
-rw-r--r--	gamma_dma.c	15107	log plain
-rw-r--r--	gamma_drv.c	3016	log plain
-rw-r--r--	gamma_drv.h	3791	log plain
-rw-r--r--	i810.h	3813	log plain
-rw-r--r--	i810_dma.c	33562	log plain
-rw-r--r--	i810_drm.h	6588	log plain
-rw-r--r--	i810_drv.c	3673	log plain
-rw-r--r--	i810_drv.h	6639	log plain
-rw-r--r--	mga.h	2200	log plain
-rw-r--r--	mga_dma.c	21196	log plain
-rw-r--r--	mga_drm.h	8927	log plain
-rw-r--r--	mga_drv.c	3622	log plain
-rw-r--r--	mga_drv.h	18427	log plain
-rw-r--r--	mga_state.c	28270	log plain
-rw-r--r--	mga_ucode.h	173314	log plain
-rw-r--r--	mga_warp.c	6865	log plain
-rw-r--r--	picker.c	552	log plain
-rw-r--r--	r128.h	2533	log plain
-rw-r--r--	r128_cce.c	28777	log plain
-rw-r--r--	r128_drm.h	7589	log plain
-rw-r--r--	r128_drv.c	4301	log plain
-rw-r--r--	r128_drv.h	17259	log plain
-rw-r--r--	r128_state.c	39569	log plain
-rw-r--r--	radeon.h	2551	log plain
-rw-r--r--	radeon_cp.c	38837	log plain
-rw-r--r--	radeon_drm.h	9052	log plain
-rw-r--r--	radeon_drv.c	4128	log plain
-rw-r--r--	radeon_drv.h	24816	log plain
-rw-r--r--	radeon_state.c	39274	log plain
-rw-r--r--	sis.h	1959	log plain
-rw-r--r--	sis_drm.h	833	log plain
-rw-r--r--	sis_drv.c	2825	log plain
-rw-r--r--	sis_drv.h	1830	log plain
-rw-r--r--	sis_ds.c	9333	log plain
-rw-r--r--	sis_ds.h	5034	log plain
-rw-r--r--	sis_mm.c	7247	log plain
-rw-r--r--	tdfx.h	1598	log plain
-rw-r--r--	tdfx_drv.c	3594	log plain

span> ((from == STATE_GRAPHIC) && ((to == STATE_LOGOUT) || (to == STATE_REBOOT) || (to == STATE_SHUTDOWN))) { DRM_INFO("Leaving graphical mode (probably X shutting down)\n"); } else { DRM_ERROR("Invalid state change.\n"); return -EINVAL; } return 0; } int xgi_state_change_ioctl(struct drm_device * dev, void * data, struct drm_file * filp) { struct xgi_state_info *const state = (struct xgi_state_info *) data; struct xgi_info *info = dev->dev_private; return xgi_state_change(info, state->_toState, state->_fromState); } void xgi_cmdlist_reset(struct xgi_info * info) { info->cmdring.last_ptr = NULL; info->cmdring.ring_offset = 0; } void xgi_cmdlist_cleanup(struct xgi_info * info) { if (info->cmdring.ring_hw_base != 0) { /* If command lists have been issued, terminate the command * list chain with a flush command. */ if (info->cmdring.last_ptr != NULL) { xgi_emit_flush(info, false); xgi_emit_nop(info); } xgi_waitfor_pci_idle(info); (void) memset(&info->cmdring, 0, sizeof(info->cmdring)); } } static void triggerHWCommandList(struct xgi_info * info) { static unsigned int s_triggerID = 1; dwWriteReg(info->mmio_map, BASE_3D_ENG + M2REG_PCI_TRIGGER_REGISTER_ADDRESS, 0x05000000 + (0x0ffff & s_triggerID++)); } /** * Emit a flush to the CRTL command stream. * @info XGI info structure * * This function assumes info->cmdring.ptr is non-NULL. */ void xgi_emit_flush(struct xgi_info * info, bool stop) { const u32 flush_command[8] = { ((0x10 << 24) | (BEGIN_BEGIN_IDENTIFICATION_MASK & info->next_sequence)), BEGIN_LINK_ENABLE_MASK | (0x00004), 0x00000000, 0x00000000, /* Flush the 2D engine with the default 32 clock delay. */ M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK, M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK, M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK, M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK, }; const unsigned int flush_size = sizeof(flush_command); u32 *batch_addr; u32 hw_addr; unsigned int i; /* check buf is large enough to contain a new flush batch */ if ((info->cmdring.ring_offset + flush_size) >= info->cmdring.size) { info->cmdring.ring_offset = 0; } hw_addr = info->cmdring.ring_hw_base + info->cmdring.ring_offset; batch_addr = info->cmdring.ptr + (info->cmdring.ring_offset / 4); for (i = 0; i < (flush_size / 4); i++) { batch_addr[i] = cpu_to_le32(flush_command[i]); } if (stop) { *batch_addr |= cpu_to_le32(BEGIN_STOP_STORE_CURRENT_POINTER_MASK); } info->cmdring.last_ptr[1] = cpu_to_le32(BEGIN_LINK_ENABLE_MASK | (flush_size / 4)); info->cmdring.last_ptr[2] = cpu_to_le32(hw_addr >> 4); info->cmdring.last_ptr[3] = 0; DRM_WRITEMEMORYBARRIER(); info->cmdring.last_ptr[0] = cpu_to_le32((get_batch_command(BTYPE_CTRL) << 24) | (BEGIN_VALID_MASK)); triggerHWCommandList(info); info->cmdring.ring_offset += flush_size; info->cmdring.last_ptr = batch_addr; } /** * Emit an empty command to the CRTL command stream. * @info XGI info structure * * This function assumes info->cmdring.ptr is non-NULL. In addition, since * this function emits a command that does not have linkage information, * it sets info->cmdring.ptr to NULL. */ void xgi_emit_nop(struct xgi_info * info) { info->cmdring.last_ptr[1] = cpu_to_le32(BEGIN_LINK_ENABLE_MASK | (BEGIN_BEGIN_IDENTIFICATION_MASK & info->next_sequence)); info->cmdring.last_ptr[2] = 0; info->cmdring.last_ptr[3] = 0; DRM_WRITEMEMORYBARRIER(); info->cmdring.last_ptr[0] = cpu_to_le32((get_batch_command(BTYPE_CTRL) << 24) | (BEGIN_VALID_MASK)); triggerHWCommandList(info); info->cmdring.last_ptr = NULL; } void xgi_emit_irq(struct xgi_info * info) { if (info->cmdring.last_ptr == NULL) return; xgi_emit_flush(info, true); }