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-rw-r--r--.gitignore16logplain
-rw-r--r--Config.in594logplain
-rw-r--r--Doxyfile47630logplain
-rw-r--r--Kconfig3353logplain
-rw-r--r--Makefile9318logplain
-rw-r--r--Makefile.kernel2826logplain
-rw-r--r--README.drm1091logplain
-rw-r--r--ati_pcigart.c5452logplain
l---------drm.h20logplain
-rw-r--r--drmP.h43853logplain
-rw-r--r--drm_agpsupport.c17635logplain
-rw-r--r--drm_auth.c5521logplain
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-rw-r--r--drm_drawable.c5288logplain
-rw-r--r--drm_drv.c20724logplain
-rw-r--r--drm_fence.c21714logplain
-rw-r--r--drm_fops.c13787logplain
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l---------drm_internal.h29logplain
-rw-r--r--drm_ioc32.c32308logplain
-rw-r--r--drm_ioctl.c9024logplain
-rw-r--r--drm_irq.c20650logplain
-rw-r--r--drm_lock.c11032logplain
-rw-r--r--drm_memory.c9378logplain
-rw-r--r--drm_memory.h1936logplain
-rw-r--r--drm_memory_debug.c10415logplain
-rw-r--r--drm_memory_debug.h10169logplain
-rw-r--r--drm_mm.c7405logplain
-rw-r--r--drm_object.c8199logplain
-rw-r--r--drm_objects.h27305logplain
-rw-r--r--drm_os_linux.h4906logplain
-rw-r--r--drm_pci.c4988logplain
-rw-r--r--drm_proc.c18425logplain
-rw-r--r--drm_regman.c5396logplain
l---------drm_sarea.h26logplain
-rw-r--r--drm_scatter.c5956logplain
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-rw-r--r--drm_stub.c9189logplain
-rw-r--r--drm_sysfs.c5480logplain
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-rw-r--r--drm_vm_nopage_compat.c7498logplain
-rw-r--r--ffb_context.c18711logplain
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-rw-r--r--i810_dma.c34121logplain
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-rw-r--r--i915_buffer.c8247logplain
-rw-r--r--i915_compat.c5350logplain
l---------i915_dma.c25logplain
l---------i915_drm.h25logplain
-rw-r--r--i915_drv.c5476logplain
l---------i915_drv.h25logplain
-rw-r--r--i915_execbuf.c23345logplain
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l---------i915_suspend.c29logplain
-rw-r--r--imagine_drv.c2523logplain
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l---------mach64_dma.c27logplain
l---------mach64_drm.h27logplain
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l---------mach64_drv.h27logplain
l---------mach64_irq.c27logplain
l---------mach64_state.c29logplain
l---------mga_dma.c24logplain
l---------mga_drm.h24logplain
-rw-r--r--mga_drv.c4754logplain
l---------mga_drv.h24logplain
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l---------mga_irq.c24logplain
l---------mga_state.c26logplain
l---------mga_ucode.h26logplain
l---------mga_warp.c25logplain
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l---------nouveau_dma.c28logplain
l---------nouveau_dma.h28logplain
l---------nouveau_drm.h28logplain
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l---------nv04_fb.c24logplain
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l---------nv04_mc.c24logplain
l---------nv04_timer.c27logplain
l---------nv10_fb.c24logplain
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l---------r128_cce.c25logplain
l---------r128_drm.h25logplain
-rw-r--r--r128_drv.c3551logplain
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l---------radeon_drm.h27logplain
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l---------sis_drm.h24logplain
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l---------sis_drv.h24logplain
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l---------via_video.c26logplain
-rw-r--r--xgi_cmdlist.c9302logplain
-rw-r--r--xgi_cmdlist.h2186logplain
l---------xgi_drm.h24logplain
-rw-r--r--xgi_drv.c11577logplain
-rw-r--r--xgi_drv.h4103logplain
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-rw-r--r--xgi_fence.c4790logplain
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-rw-r--r--xgi_pcie.c3840logplain
-rw-r--r--xgi_regs.h5944logplain
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-01 19:40:23 +0000
">(&dev_priv->idle_count) == 0) { r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); } else { atomic_set(&dev_priv->idle_count, 0); } } #endif /* ================================================================ * CCE command dispatch functions */ static void r128_print_dirty(const char *msg, unsigned int flags) { DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", msg, flags, (flags & R128_UPLOAD_CORE) ? "core, " : "", (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", (flags & R128_UPLOAD_SETUP) ? "setup, " : "", (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", (flags & R128_UPLOAD_MASKS) ? "masks, " : "", (flags & R128_UPLOAD_WINDOW) ? "window, " : "", (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : ""); } static void r128_cce_dispatch_clear(struct drm_device * dev, drm_r128_clear_t * clear) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; struct drm_clip_rect *pbox = sarea_priv->boxes; unsigned int flags = clear->flags; int i; RING_LOCALS; DRM_DEBUG("\n"); if (dev_priv->page_flipping && dev_priv->current_page == 1) { unsigned int tmp = flags; flags &= ~(R128_FRONT | R128_BACK); if (tmp & R128_FRONT) flags |= R128_BACK; if (tmp & R128_BACK) flags |= R128_FRONT; } for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2, flags); if (flags & (R128_FRONT | R128_BACK)) { BEGIN_RING(2); OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); OUT_RING(clear->color_mask); ADVANCE_RING(); } if (flags & R128_FRONT) { BEGIN_RING(6); OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->color_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS); OUT_RING(dev_priv->front_pitch_offset_c); OUT_RING(clear->clear_color); OUT_RING((x << 16) | y); OUT_RING((w << 16) | h); ADVANCE_RING(); } if (flags & R128_BACK) { BEGIN_RING(6); OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->color_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS); OUT_RING(dev_priv->back_pitch_offset_c); OUT_RING(clear->clear_color); OUT_RING((x << 16) | y); OUT_RING((w << 16) | h); ADVANCE_RING(); } if (flags & R128_DEPTH) { BEGIN_RING(6); OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); OUT_RING(dev_priv->depth_pitch_offset_c); OUT_RING(clear->clear_depth); OUT_RING((x << 16) | y); OUT_RING((w << 16) | h); ADVANCE_RING(); } } } static void r128_cce_dispatch_swap(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; struct drm_clip_rect *pbox = sarea_priv->boxes; int i; RING_LOCALS; DRM_DEBUG("\n"); #if R128_PERFORMANCE_BOXES /* Do some trivial performance monitoring... */ r128_cce_performance_boxes(dev_priv); #endif for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; BEGIN_RING(7); OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_NONE | (dev_priv->color_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_S | R128_DP_SRC_SOURCE_MEMORY | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); /* Make this work even if front & back are flipped: */ if (dev_priv->current_page == 0) { OUT_RING(dev_priv->back_pitch_offset_c); OUT_RING(dev_priv->front_pitch_offset_c); } else { OUT_RING(dev_priv->front_pitch_offset_c); OUT_RING(dev_priv->back_pitch_offset_c); } OUT_RING((x << 16) | y); OUT_RING((x << 16) | y); OUT_RING((w << 16) | h); ADVANCE_RING(); } /* Increment the frame counter. The client-side 3D driver must * throttle the framerate by waiting for this value before * performing the swapbuffer ioctl. */ dev_priv->sarea_priv->last_frame++; BEGIN_RING(2); OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); OUT_RING(dev_priv->sarea_priv->last_frame); ADVANCE_RING(); } static void r128_cce_dispatch_flip(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; RING_LOCALS; DRM_DEBUG("page=%d pfCurrentPage=%d\n", dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); #if R128_PERFORMANCE_BOXES /* Do some trivial performance monitoring... */ r128_cce_performance_boxes(dev_priv); #endif BEGIN_RING(4); R128_WAIT_UNTIL_PAGE_FLIPPED(); OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0)); if (dev_priv->current_page == 0) { OUT_RING(dev_priv->back_offset); } else { OUT_RING(dev_priv->front_offset); } ADVANCE_RING(); /* Increment the frame counter. The client-side 3D driver must * throttle the framerate by waiting for this value before * performing the swapbuffer ioctl. */ dev_priv->sarea_priv->last_frame++; dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = 1 - dev_priv->current_page; BEGIN_RING(2); OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); OUT_RING(dev_priv->sarea_priv->last_frame); ADVANCE_RING(); } static void r128_cce_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int format = sarea_priv->vc_format; int offset = buf->bus_address; int size = buf->used; int prim = buf_priv->prim; int i = 0; RING_LOCALS; DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox); if (0) r128_print_dirty("dispatch_vertex", sarea_priv->dirty); if (buf->used) { buf_priv->dispatched = 1; if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { r128_emit_state(dev_priv); } do { /* Emit the next set of up to three cliprects */ if (i < sarea_priv->nbox) { r128_emit_clip_rects(dev_priv, &sarea_priv->boxes[i], sarea_priv->nbox - i); } /* Emit the vertex buffer rendering commands */ BEGIN_RING(5); OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3)); OUT_RING(offset); OUT_RING(size); OUT_RING(format); OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | (size << R128_CCE_VC_CNTL_NUM_SHIFT)); ADVANCE_RING(); i += 3; } while (i < sarea_priv->nbox); } if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ BEGIN_RING(2); OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); OUT_RING(buf_priv->age); ADVANCE_RING(); buf->pending = 1; buf->used = 0; /* FIXME: Check dispatched field */ buf_priv->dispatched = 0; } dev_priv->sarea_priv->last_dispatch++; sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; sarea_priv->nbox = 0; } static void r128_cce_dispatch_indirect(struct drm_device * dev, struct drm_buf * buf, int start, int end) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; RING_LOCALS; DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); if (start != end) { int offset = buf->bus_address + start; int dwords = (end - start + 3) / sizeof(u32); /* Indirect buffer data must be an even number of * dwords, so if we've been given an odd number we must * pad the data with a Type-2 CCE packet. */ if (dwords & 1) { u32 *data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset + start); data[dwords++] = cpu_to_le32(R128_CCE_PACKET2); } buf_priv->dispatched = 1; /* Fire off the indirect buffer */ BEGIN_RING(3); OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1)); OUT_RING(offset); OUT_RING(dwords); ADVANCE_RING(); } if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the indirect buffer age */ BEGIN_RING(2); OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); OUT_RING(buf_priv->age); ADVANCE_RING(); buf->pending = 1; buf->used = 0; /* FIXME: Check dispatched field */ buf_priv->dispatched = 0; } dev_priv->sarea_priv->last_dispatch++; } static void r128_cce_dispatch_indices(struct drm_device * dev, struct drm_buf * buf, int start, int end, int count) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int format = sarea_priv->vc_format; int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset; int prim = buf_priv->prim; u32 *data; int dwords; int i = 0; RING_LOCALS; DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count); if (0) r128_print_dirty("dispatch_indices", sarea_priv->dirty); if (start != end) { buf_priv->dispatched = 1; if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { r128_emit_state(dev_priv); } dwords = (end - start + 3) / sizeof(u32); data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset + start); data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, dwords - 2)); data[1] = cpu_to_le32(offset); data[2] = cpu_to_le32(R128_MAX_VB_VERTS); data[3] = cpu_to_le32(format); data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | (count << 16))); if (count & 0x1) { #ifdef __LITTLE_ENDIAN data[dwords - 1] &= 0x0000ffff; #else data[dwords - 1] &= 0xffff0000; #endif } do { /* Emit the next set of up to three cliprects */ if (i < sarea_priv->nbox) { r128_emit_clip_rects(dev_priv, &sarea_priv->boxes[i], sarea_priv->nbox - i); } r128_cce_dispatch_indirect(dev, buf, start, end); i += 3; } while (i < sarea_priv->nbox); } if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ BEGIN_RING(2); OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); OUT_RING(buf_priv->age); ADVANCE_RING(); buf->pending = 1; /* FIXME: Check dispatched field */ buf_priv->dispatched = 0; } dev_priv->sarea_priv->last_dispatch++; sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; sarea_priv->nbox = 0; } static int r128_cce_dispatch_blit(struct drm_device * dev, struct drm_file *file_priv, drm_r128_blit_t * blit) { drm_r128_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; u32 *data; int dword_shift, dwords; RING_LOCALS; DRM_DEBUG("\n"); /* The compiler won't optimize away a division by a variable, * even if the only legal values are powers of two. Thus, we'll * use a shift instead. */ switch (blit->format) { case R128_DATATYPE_ARGB8888: dword_shift = 0; break; case R128_DATATYPE_ARGB1555: case R128_DATATYPE_RGB565: case R128_DATATYPE_ARGB4444: case R128_DATATYPE_YVYU422: case R128_DATATYPE_VYUY422: dword_shift = 1; break; case R128_DATATYPE_CI8: case R128_DATATYPE_RGB8: dword_shift = 2; break; default: DRM_ERROR("invalid blit format %d\n", blit->format); return -EINVAL; } /* Flush the pixel cache, and mark the contents as Read Invalid. * This ensures no pixel data gets mixed up with the texture * data from the host data blit, otherwise part of the texture * image may be corrupted. */ BEGIN_RING(2); OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI); ADVANCE_RING(); /* Dispatch the indirect buffer. */ buf = dma->buflist[blit->idx]; buf_priv = buf->dev_private; if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", blit->idx); return -EINVAL; } buf_priv->discard = 1; dwords = (blit->width * blit->height) >> dword_shift; data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6)); data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_NONE | (blit->format << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_S | R128_DP_SRC_SOURCE_HOST_DATA | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS)); data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5)); data[3] = cpu_to_le32(0xffffffff); data[4] = cpu_to_le32(0xffffffff); data[5] = cpu_to_le32((blit->y << 16) | blit->x); data[6] = cpu_to_le32((blit->height << 16) | blit->width); data[7] = cpu_to_le32(dwords); buf->used = (dwords + 8) * sizeof(u32); r128_cce_dispatch_indirect(dev, buf, 0, buf->used); /* Flush the pixel cache after the blit completes. This ensures * the texture data is written out to memory before rendering * continues. */ BEGIN_RING(2); OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); OUT_RING(R128_PC_FLUSH_GUI); ADVANCE_RING(); return 0; } /* ================================================================ * Tiled depth buffer management * * FIXME: These should all set the destination write mask for when we * have hardware stencil support. */ static int r128_cce_dispatch_write_span(struct drm_device * dev, drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, x, y; u32 *buffer; u8 *mask; int i, buffer_size, mask_size; RING_LOCALS; DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) return -EMSGSIZE; if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { return -EFAULT; } if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { return -EFAULT; } buffer_size = depth->n * sizeof(u32); buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); if (buffer == NULL) return -ENOMEM; if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { drm_free(buffer, buffer_size, DRM_MEM_BUFS); return -EFAULT; } mask_size = depth->n * sizeof(u8); if (depth->mask) { mask = drm_alloc(mask_size, DRM_MEM_BUFS); if (mask == NULL) { drm_free(buffer, buffer_size, DRM_MEM_BUFS); return -ENOMEM; } if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { drm_free(buffer, buffer_size, DRM_MEM_BUFS); drm_free(mask, mask_size, DRM_MEM_BUFS); return -EFAULT; } for (i = 0; i < count; i++, x++) { if (mask[i]) { BEGIN_RING(6); OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); OUT_RING(dev_priv->depth_pitch_offset_c); OUT_RING(buffer[i]); OUT_RING((x << 16) | y); OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } drm_free(mask, mask_size, DRM_MEM_BUFS); } else { for (i = 0; i < count; i++, x++) { BEGIN_RING(6); OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); OUT_RING(dev_priv->depth_pitch_offset_c); OUT_RING(buffer[i]); OUT_RING((x << 16) | y); OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } drm_free(buffer, buffer_size, DRM_MEM_BUFS); return 0; } static int r128_cce_dispatch_write_pixels(struct drm_device * dev, drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; u32 *buffer; u8 *mask; int i, xbuf_size, ybuf_size, buffer_size, mask_size; RING_LOCALS; DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) return -EMSGSIZE; xbuf_size = count * sizeof(*x); ybuf_size = count * sizeof(*y); x = drm_alloc(xbuf_size, DRM_MEM_BUFS); if (x == NULL) { return -ENOMEM; } y = drm_alloc(ybuf_size, DRM_MEM_BUFS); if (y == NULL) { drm_free(x, xbuf_size, DRM_MEM_BUFS); return -ENOMEM; } if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); return -EFAULT; } if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); return -EFAULT; } buffer_size = depth->n * sizeof(u32); buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); if (buffer == NULL) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); return -ENOMEM; } if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); drm_free(buffer, buffer_size, DRM_MEM_BUFS); return -EFAULT; } if (depth->mask) { mask_size = depth->n * sizeof(u8); mask = drm_alloc(mask_size, DRM_MEM_BUFS); if (mask == NULL) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); drm_free(buffer, buffer_size, DRM_MEM_BUFS); return -ENOMEM; } if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); drm_free(buffer, buffer_size, DRM_MEM_BUFS); drm_free(mask, mask_size, DRM_MEM_BUFS); return -EFAULT; } for (i = 0; i < count; i++) { if (mask[i]) { BEGIN_RING(6); OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); OUT_RING(dev_priv->depth_pitch_offset_c); OUT_RING(buffer[i]); OUT_RING((x[i] << 16) | y[i]); OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } drm_free(mask, mask_size, DRM_MEM_BUFS); } else { for (i = 0; i < count; i++) { BEGIN_RING(6); OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); OUT_RING(dev_priv->depth_pitch_offset_c); OUT_RING(buffer[i]); OUT_RING((x[i] << 16) | y[i]); OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); drm_free(buffer, buffer_size, DRM_MEM_BUFS); return 0; } static int r128_cce_dispatch_read_span(struct drm_device * dev, drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, x, y; RING_LOCALS; DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) return -EMSGSIZE; if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { return -EFAULT; } if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { return -EFAULT; } BEGIN_RING(7); OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_NONE | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_S | R128_DP_SRC_SOURCE_MEMORY | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); OUT_RING(dev_priv->depth_pitch_offset_c); OUT_RING(dev_priv->span_pitch_offset_c); OUT_RING((x << 16) | y); OUT_RING((0 << 16) | 0); OUT_RING((count << 16) | 1); ADVANCE_RING(); return 0; } static int r128_cce_dispatch_read_pixels(struct drm_device * dev, drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; int i, xbuf_size, ybuf_size; RING_LOCALS; DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) return -EMSGSIZE; if (count > dev_priv->depth_pitch) { count = dev_priv->depth_pitch; } xbuf_size = count * sizeof(*x); ybuf_size = count * sizeof(*y); x = drm_alloc(xbuf_size, DRM_MEM_BUFS); if (x == NULL) { return -ENOMEM; } y = drm_alloc(ybuf_size, DRM_MEM_BUFS); if (y == NULL) { drm_free(x, xbuf_size, DRM_MEM_BUFS); return -ENOMEM; } if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); return -EFAULT; } if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); return -EFAULT; } for (i = 0; i < count; i++) { BEGIN_RING(7); OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_NONE | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_S | R128_DP_SRC_SOURCE_MEMORY | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); OUT_RING(dev_priv->depth_pitch_offset_c); OUT_RING(dev_priv->span_pitch_offset_c); OUT_RING((x[i] << 16) | y[i]); OUT_RING((i << 16) | 0); OUT_RING((1 << 16) | 1); ADVANCE_RING(); } drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); return 0; } /* ================================================================ * Polygon stipple */ static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple) { drm_r128_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; DRM_DEBUG("\n"); BEGIN_RING(33); OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31)); for (i = 0; i < 32; i++) { OUT_RING(stipple[i]); } ADVANCE_RING(); } /* ================================================================ * IOCTL functions */ static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_clear_t *clear = data; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); RING_SPACE_TEST_WITH_RETURN(dev_priv); if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; r128_cce_dispatch_clear(dev, clear); COMMIT_RING(); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; return 0; } static int r128_do_init_pageflip(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET); dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL); R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset); R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL); dev_priv->page_flipping = 1; dev_priv->current_page = 0; dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; return 0; } static int r128_do_cleanup_pageflip(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); if (dev_priv->current_page != 0) { r128_cce_dispatch_flip(dev); COMMIT_RING(); } dev_priv->page_flipping = 0; return 0; } /* Swapping and flipping are different operations, need different ioctls. * They can & should be intermixed to support multiple 3d windows. */ static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); RING_SPACE_TEST_WITH_RETURN(dev_priv); if (!dev_priv->page_flipping) r128_do_init_pageflip(dev); r128_cce_dispatch_flip(dev); COMMIT_RING(); return 0; } static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); RING_SPACE_TEST_WITH_RETURN(dev_priv); if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; r128_cce_dispatch_swap(dev); dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS); COMMIT_RING(); return 0; } static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_vertex_t *vertex = data; LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("called with no initialization\n"); return -EINVAL; } DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", vertex->idx, dma->buf_count - 1); return -EINVAL; } if (vertex->prim < 0 || vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { DRM_ERROR("buffer prim %d\n", vertex->prim); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[vertex->idx]; buf_priv = buf->dev_private; if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", vertex->idx); return -EINVAL; } buf->used = vertex->count; buf_priv->prim = vertex->prim; buf_priv->discard = vertex->discard; r128_cce_dispatch_vertex(dev, buf); COMMIT_RING(); return 0; } static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_indices_t *elts = data; int count; LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("called with no initialization\n"); return -EINVAL; } DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, elts->idx, elts->start, elts->end, elts->discard); if (elts->idx < 0 || elts->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", elts->idx, dma->buf_count - 1); return -EINVAL; } if (elts->prim < 0 || elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { DRM_ERROR("buffer prim %d\n", elts->prim); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[elts->idx]; buf_priv = buf->dev_private; if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", elts->idx); return -EINVAL; } count = (elts->end - elts->start) / sizeof(u16); elts->start -= R128_INDEX_PRIM_OFFSET; if (elts->start & 0x7) { DRM_ERROR("misaligned buffer 0x%x\n", elts->start); return -EINVAL; } if (elts->start < buf->used) { DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used); return -EINVAL; } buf->used = elts->end; buf_priv->prim = elts->prim; buf_priv->discard = elts->discard; r128_cce_dispatch_indices(dev, buf, elts->start, elts->end, count); COMMIT_RING(); return 0; } static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_device_dma *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_blit_t *blit = data; int ret; LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx); if (blit->idx < 0 || blit->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", blit->idx, dma->buf_count - 1); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); ret = r128_cce_dispatch_blit(dev, file_priv, blit); COMMIT_RING(); return ret; } static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_depth_t *depth = data; int ret; LOCK_TEST_WITH_RETURN(dev, file_priv); RING_SPACE_TEST_WITH_RETURN(dev_priv); ret = -EINVAL; switch (depth->func) { case R128_WRITE_SPAN: ret = r128_cce_dispatch_write_span(dev, depth); break; case R128_WRITE_PIXELS: ret = r128_cce_dispatch_write_pixels(dev, depth); break; case R128_READ_SPAN: ret = r128_cce_dispatch_read_span(dev, depth); break; case R128_READ_PIXELS: ret = r128_cce_dispatch_read_pixels(dev, depth); break; } COMMIT_RING(); return ret; } static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_stipple_t *stipple = data; u32 mask[32]; LOCK_TEST_WITH_RETURN(dev, file_priv); if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) return -EFAULT; RING_SPACE_TEST_WITH_RETURN(dev_priv); r128_cce_dispatch_stipple(dev, mask); COMMIT_RING(); return 0; } static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_indirect_t *indirect = data; #if 0 RING_LOCALS; #endif LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("called with no initialization\n"); return -EINVAL; } DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", indirect->idx, indirect->start, indirect->end, indirect->discard); if (indirect->idx < 0 || indirect->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", indirect->idx, dma->buf_count - 1); return -EINVAL; } buf = dma->buflist[indirect->idx]; buf_priv = buf->dev_private; if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", indirect->idx); return -EINVAL; } if (indirect->start < buf->used) { DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", indirect->start, buf->used); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); buf->used = indirect->end; buf_priv->discard = indirect->discard; #if 0 /* Wait for the 3D stream to idle before the indirect buffer * containing 2D acceleration commands is processed. */ BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); #endif /* Dispatch the indirect buffer full of commands from the * X server. This is insecure and is thus only available to * privileged clients. */ r128_cce_dispatch_indirect(dev, buf, indirect->start, indirect->end); COMMIT_RING(); return 0; } static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_getparam_t *param = data; int value; if (!dev_priv) { DRM_ERROR("called with no initialization\n"); return -EINVAL; } DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); switch (param->param) { case R128_PARAM_IRQ_NR: value = dev->irq; break; default: return -EINVAL; } if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } return 0; } void r128_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) { if (dev->dev_private) { drm_r128_private_t *dev_priv = dev->dev_private; if (dev_priv->page_flipping) { r128_do_cleanup_pageflip(dev); } } } void r128_driver_lastclose(struct drm_device * dev) { r128_do_cleanup_cce(dev); } struct drm_ioctl_desc r128_ioctls[] = { DRM_IOCTL_DEF(DRM_R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_R128_CCE_IDLE, r128_cce_idle, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_RESET, r128_engine_reset, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_FULLSCREEN, r128_fullscreen, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_SWAP, r128_cce_swap, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_FLIP, r128_cce_flip, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_CLEAR, r128_cce_clear, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_VERTEX, r128_cce_vertex, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_INDICES, r128_cce_indices, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_BLIT, r128_cce_blit, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_DEPTH, r128_cce_depth, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_STIPPLE, r128_cce_stipple, DRM_AUTH), DRM_IOCTL_DEF(DRM_R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_R128_GETPARAM, r128_getparam, DRM_AUTH), }; int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-01 19:40:23 +0000