/* mach64_irq.c -- IRQ handling for ATI Mach64 -*- linux-c -*- * Created: Tue Feb 25, 2003 by Leif Delgass, based on radeon_irq.c/r128_irq.c */ /*- * Copyright (C) The Weather Channel, Inc. 2002. * Copyright 2003 Leif Delgass * All Rights Reserved. * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Keith Whitwell * Eric Anholt * Leif Delgass */ #include "drmP.h" #include "drm.h" #include "mach64_drm.h" #include "mach64_drv.h" irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS) { drm_device_t *dev = (drm_device_t *) arg; drm_mach64_private_t *dev_priv = (drm_mach64_private_t *) dev->dev_private; int status; status = MACH64_READ(MACH64_CRTC_INT_CNTL); /* VBLANK interrupt */ if (status & MACH64_CRTC_VBLANK_INT) { /* Mask off all interrupt ack bits before setting the ack bit, since * there may be other handlers outside the DRM. * * NOTE: On mach64, you need to keep the enable bits set when doing * the ack, despite what the docs say about not acking and enabling * in a single write. */ MACH64_WRITE(MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_INT_ACKS) | MACH64_CRTC_VBLANK_INT); atomic_inc(&dev->vbl_received); DRM_WAKEUP(&dev->vbl_queue); drm_vbl_send_signals(dev); return IRQ_HANDLED; } return IRQ_NONE; } int mach64_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; /* Assume that the user has missed the current sequence number * by about a day rather than she wants to wait for years * using vertical blanks... */ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, (((cur_vblank = atomic_read(&dev->vbl_received)) - *sequence) <= (1 << 23))); *sequence = cur_vblank; return ret; } /* drm_dma.h hooks */ void mach64_driver_irq_preinstall(drm_device_t * dev) { drm_mach64_private_t *dev_priv = (drm_mach64_private_t *) dev->dev_private; u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL); DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status); /* Disable and clear VBLANK interrupt */ MACH64_WRITE(MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN) | MACH64_CRTC_VBLANK_INT); } void mach64_driver_irq_postinstall(drm_device_t * dev) { drm_mach64_private_t *dev_priv = (drm_mach64_private_t *) dev->dev_private; /* Turn on VBLANK interrupt */ MACH64_WRITE(MACH64_CRTC_INT_CNTL, MACH64_READ(MACH64_CRTC_INT_CNTL) | MACH64_CRTC_VBLANK_INT_EN); DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n", MACH64_READ(MACH64_CRTC_INT_CNTL)); } void mach64_driver_irq_uninstall(drm_device_t * dev) { drm_mach64_private_t *dev_priv = (drm_mach64_private_t *) dev->dev_private; if (!dev_priv) return; /* Disable and clear VBLANK interrupt */ MACH64_WRITE(MACH64_CRTC_INT_CNTL, (MACH64_READ(MACH64_CRTC_INT_CNTL) & ~MACH64_CRTC_VBLANK_INT_EN) | MACH64_CRTC_VBLANK_INT); DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n", MACH64_READ(MACH64_CRTC_INT_CNTL)); } id='n45' href='#n45'>45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 
/*
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_drv.h"

#include "atom.h"

#include "drm_crtc_helper.h"

int radeon_suspend(struct drm_device *dev, pm_message_t state)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb;
	int i;

	if (!dev || !dev_priv) {
		return -ENODEV;
	}

	if (state.event == PM_EVENT_PRETHAW)
		return 0;

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

	/* unpin the front buffers */
	list_for_each_entry(fb, &dev->mode_config.fb_kernel_list, filp_head) {
		struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);

		if (!radeon_fb)
			continue;

		if (!radeon_fb->obj)
			continue;
		
		radeon_gem_object_unpin(radeon_fb->obj);
	}

	if (!(dev_priv->flags & RADEON_IS_IGP))
		drm_bo_evict_mm(dev, DRM_BO_MEM_VRAM, 0);

	dev_priv->pmregs.crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
	for (i = 0; i < 8; i++)
		dev_priv->pmregs.bios_scratch[i] = RADEON_READ(RADEON_BIOS_0_SCRATCH + (i * 4));

	radeon_modeset_cp_suspend(dev);

        /* Disable *all* interrupts */
	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
		RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);

	if (dev_priv->flags & RADEON_IS_PCIE) {
		memcpy_fromio(dev_priv->mm.pcie_table_backup, dev_priv->mm.pcie_table.kmap.virtual, RADEON_PCIGART_TABLE_SIZE);
	}

	pci_save_state(dev->pdev);

	if (state.event == PM_EVENT_SUSPEND) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
	}
	return 0;
}

int radeon_resume(struct drm_device *dev)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb;
	int i;

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

	pci_set_power_state(dev->pdev, PCI_D0);
	pci_restore_state(dev->pdev);
	if (pci_enable_device(dev->pdev))
		return -1;

	/* Turn on bus mastering -todo fix properly */
	radeon_enable_bm(dev_priv);

	DRM_ERROR("\n");
	/* on atom cards re init the whole card 
	   and set the modes again */

	if (dev_priv->is_atom_bios) {
		struct atom_context *ctx = dev_priv->mode_info.atom_context;
		atom_asic_init(ctx);
	} else {
		radeon_combios_asic_init(dev);
	}

	pci_set_master(dev->pdev);

	for (i = 0; i < 8; i++)
		RADEON_WRITE(RADEON_BIOS_0_SCRATCH + (i * 4), dev_priv->pmregs.bios_scratch[i]);

	/* VGA render mayhaps */
	if (dev_priv->chip_family >= CHIP_RS600) {
		uint32_t tmp;

		RADEON_WRITE(AVIVO_D1VGA_CONTROL, 0);
		RADEON_WRITE(AVIVO_D2VGA_CONTROL, 0);
		tmp = RADEON_READ(0x300);
		tmp &= ~(3 << 16);
		RADEON_WRITE(0x300, tmp);
		RADEON_WRITE(0x308, (1 << 8));
		RADEON_WRITE(0x310, dev_priv->fb_location);
		RADEON_WRITE(0x594, 0);
	}

	RADEON_WRITE(RADEON_CRTC_EXT_CNTL, dev_priv->pmregs.crtc_ext_cntl);

	radeon_static_clocks_init(dev);
	
	radeon_init_memory_map(dev);

	if (dev_priv->flags & RADEON_IS_PCIE) {
		memcpy_toio(dev_priv->mm.pcie_table.kmap.virtual, dev_priv->mm.pcie_table_backup, RADEON_PCIGART_TABLE_SIZE);
	}

	if (dev_priv->mm.ring.kmap.virtual)
		memset(dev_priv->mm.ring.kmap.virtual, 0, RADEON_DEFAULT_RING_SIZE);

	if (dev_priv->mm.ring_read.kmap.virtual)
		memset(dev_priv->mm.ring_read.kmap.virtual, 0, PAGE_SIZE);

	radeon_modeset_cp_resume(dev);

	/* reset swi reg */
	RADEON_WRITE(RADEON_LAST_SWI_REG, dev_priv->counter);

	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
		RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
	RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);

	/* reset the context for userspace */
	if (dev->primary->master) {
		struct drm_radeon_master_private *master_priv = dev->primary->master->driver_priv;
		if (master_priv->sarea_priv)
			master_priv->sarea_priv->ctx_owner = 0;
	}

	/* pin the front buffers */
	list_for_each_entry(fb, &dev->mode_config.fb_kernel_list, filp_head) {
		
		struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);

		if (!radeon_fb)
			continue;

		if (!radeon_fb->obj)
			continue;
		
		radeon_gem_object_pin(radeon_fb->obj,
				      PAGE_SIZE, RADEON_GEM_DOMAIN_VRAM);
	}
	/* blat the mode back in */
	drm_helper_resume_force_mode(dev);

	return 0;
}

bool radeon_set_pcie_lanes(struct drm_device *dev, int lanes)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	uint32_t link_width_cntl, mask;

	/* FIXME wait for idle */


	switch (lanes) {
	case 0:
		mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
		break;
	case 1:
		mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
		break;
	case 2:
		mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
		break;
	case 4:
		mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
		break;
	case 8:
		mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
		break;
	case 12:
		mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
		break;
	case 16:
	default:
		mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
		break;
	}

	link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);

	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
	    (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
		return true;

	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
			     RADEON_PCIE_LC_RECONFIG_NOW |
			     RADEON_PCIE_LC_RECONFIG_LATER |
			     RADEON_PCIE_LC_SHORT_RECONFIG_EN);
	link_width_cntl |= mask;
	RADEON_WRITE_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
	RADEON_WRITE_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW);

	/* wait for lane set to complete */
	link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
	while (link_width_cntl == 0xffffffff)
		link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);

	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
	    (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
		return true;
	else
		return false;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-17 03:49:19 +0000