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path: root/linux-core/nouveau_bo.c
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/*
 * Copyright 2007 Dave Airlied
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
/*
 * Authors: Dave Airlied <airlied@linux.ie>
 *	    Ben Skeggs   <darktama@iinet.net.au>
 *	    Jeremy Kolb  <jkolb@brandeis.edu>
 */

#include "drmP.h"
#include "nouveau_drm.h"
#include "nouveau_drv.h"
#include "nouveau_dma.h"

static struct drm_ttm_backend *
nouveau_bo_create_ttm_backend_entry(struct drm_device * dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	switch (dev_priv->gart_info.type) {
	case NOUVEAU_GART_AGP:
		return drm_agp_init_ttm(dev);
	case NOUVEAU_GART_SGDMA:
		return nouveau_sgdma_init_ttm(dev);
	default:
		DRM_ERROR("Unknown GART type %d\n", dev_priv->gart_info.type);
		break;
	}

	return NULL;
}

static int
nouveau_bo_fence_type(struct drm_buffer_object *bo,
		      uint32_t *fclass, uint32_t *type)
{
	/* When we get called, *fclass is set to the requested fence class */

	if (bo->mem.proposed_flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE))
		*type = 3;
	else
		*type = 1;
	return 0;

}

static int
nouveau_bo_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags)
{
	/* We'll do this from user space. */
	return 0;
}

static int
nouveau_bo_init_mem_type(struct drm_device *dev, uint32_t type,
			 struct drm_mem_type_manager *man)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	switch (type) {
	case DRM_BO_MEM_LOCAL:
		man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
			     _DRM_FLAG_MEMTYPE_CACHED;
		man->drm_bus_maptype = 0;
		break;
	case DRM_BO_MEM_VRAM:
		man->flags = _DRM_FLAG_MEMTYPE_FIXED |
			     _DRM_FLAG_MEMTYPE_MAPPABLE |
			     _DRM_FLAG_NEEDS_IOREMAP;
		man->io_addr = NULL;
		man->drm_bus_maptype = _DRM_FRAME_BUFFER;
		man->io_offset = drm_get_resource_start(dev, 1);
		man->io_size = drm_get_resource_len(dev, 1);
		if (man->io_size > nouveau_mem_fb_amount(dev))
			man->io_size = nouveau_mem_fb_amount(dev);
		break;
	case DRM_BO_MEM_PRIV0:
		/* Unmappable VRAM */
		man->flags = _DRM_FLAG_MEMTYPE_CMA;
		man->drm_bus_maptype = 0;
		break;
	case DRM_BO_MEM_TT:
		switch (dev_priv->gart_info.type) {
		case NOUVEAU_GART_AGP:
			man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
				     _DRM_FLAG_MEMTYPE_CSELECT |
				     _DRM_FLAG_NEEDS_IOREMAP;
			man->drm_bus_maptype = _DRM_AGP;
			break;
		case NOUVEAU_GART_SGDMA:
			man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
				     _DRM_FLAG_MEMTYPE_CSELECT |
				     _DRM_FLAG_MEMTYPE_CMA;
			man->drm_bus_maptype = _DRM_SCATTER_GATHER;
			break;
		default:
			DRM_ERROR("Unknown GART type: %d\n",
				  dev_priv->gart_info.type);
			return -EINVAL;
		}

		man->io_offset  = dev_priv->gart_info.aper_base;
		man->io_size    = dev_priv->gart_info.aper_size;
		man->io_addr   = NULL;
		break;
	default:
		DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
		return -EINVAL;
	}
	return 0;
}

static uint64_t
nouveau_bo_evict_flags(struct drm_buffer_object *bo)
{
	switch (bo->mem.mem_type) {
	case DRM_BO_MEM_LOCAL:
	case DRM_BO_MEM_TT:
		return DRM_BO_FLAG_MEM_LOCAL;
	default:
		return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_CACHED;
	}
	return 0;
}


/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
 * DRM_BO_MEM_{VRAM,PRIV0,TT} directly.
 */
static int
nouveau_bo_move_m2mf(struct drm_buffer_object *bo, int evict, int no_wait,
		     struct drm_bo_mem_reg *new_mem)
{
	struct drm_device *dev = bo->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_drm_channel *dchan = &dev_priv->channel;
	struct drm_bo_mem_reg *old_mem = &bo->mem;
	uint32_t srch, dsth, page_count;

	/* Can happen during init/takedown */
	if (!dchan->chan)
		return -EINVAL;

	srch = old_mem->mem_type == DRM_BO_MEM_TT ? NvDmaTT : NvDmaFB;
	dsth = new_mem->mem_type == DRM_BO_MEM_TT ? NvDmaTT : NvDmaFB;
	if (srch != dchan->m2mf_dma_source || dsth != dchan->m2mf_dma_destin) {
		dchan->m2mf_dma_source = srch;
		dchan->m2mf_dma_destin = dsth;

		BEGIN_RING(NvSubM2MF,
			   NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_SOURCE, 2);
		OUT_RING  (dchan->m2mf_dma_source);
		OUT_RING  (dchan->m2mf_dma_destin);
	}

	page_count = new_mem->num_pages;
	while (page_count) {
		int line_count = (page_count > 2047) ? 2047 : page_count;

		BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
		OUT_RING  (old_mem->mm_node->start << PAGE_SHIFT);
		OUT_RING  (new_mem->mm_node->start << PAGE_SHIFT);
		OUT_RING  (PAGE_SIZE); /* src_pitch */
		OUT_RING  (PAGE_SIZE); /* dst_pitch */
		OUT_RING  (PAGE_SIZE); /* line_length */
		OUT_RING  (line_count);
		OUT_RING  ((1<<8)|(1<<0));
		OUT_RING  (0);
		BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
		OUT_RING  (0);

		page_count -= line_count;
	}

	return drm_bo_move_accel_cleanup(bo, evict, no_wait, dchan->chan->id,
					 DRM_FENCE_TYPE_EXE, 0, new_mem);
}

/* Flip pages into the GART and move if we can. */
static int
nouveau_bo_move_flipd(struct drm_buffer_object *bo, int evict, int no_wait,
		      struct drm_bo_mem_reg *new_mem)
{
        struct drm_device *dev = bo->dev;
        struct drm_bo_mem_reg tmp_mem;
        int ret;

        tmp_mem = *new_mem;
        tmp_mem.mm_node = NULL;
        tmp_mem.proposed_flags = (DRM_BO_FLAG_MEM_TT |
				  DRM_BO_FLAG_CACHED |
				  DRM_BO_FLAG_FORCE_CACHING);

        ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
        if (ret)
                return ret;

        ret = drm_ttm_bind(bo->ttm, &tmp_mem);
        if (ret)
                goto out_cleanup;

        ret = nouveau_bo_move_m2mf(bo, 1, no_wait, &tmp_mem);
        if (ret)
                goto out_cleanup;

        ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem);

out_cleanup:
        if (tmp_mem.mm_node) {
                mutex_lock(&dev->struct_mutex);
                if (tmp_mem.mm_node != bo->pinned_node)
                        drm_memrange_put_block(tmp_mem.mm_node);
                tmp_mem.mm_node = NULL;
                mutex_unlock(&dev->struct_mutex);
        }

        return ret;
}

static int
nouveau_bo_move(struct drm_buffer_object *bo, int evict, int no_wait,
		struct drm_bo_mem_reg *new_mem)
{
	struct drm_bo_mem_reg *old_mem = &bo->mem;

	if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
		if (old_mem->mem_type == DRM_BO_MEM_LOCAL)
			return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
		if (nouveau_bo_move_flipd(bo, evict, no_wait, new_mem))
			return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
	}
	else
	if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
		if (1 /*nouveau_bo_move_flips(bo, evict, no_wait, new_mem)*/)
			return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
	}
	else {
		if (nouveau_bo_move_m2mf(bo, evict, no_wait, new_mem))
			return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
	}

	return 0;
}

static void
nouveau_bo_flush_ttm(struct drm_ttm *ttm)
{
}

static uint32_t nouveau_mem_prios[]  = {
	DRM_BO_MEM_PRIV0,
	DRM_BO_MEM_VRAM,
	DRM_BO_MEM_TT,
	DRM_BO_MEM_LOCAL
};
static uint32_t nouveau_busy_prios[] = {
	DRM_BO_MEM_TT,
	DRM_BO_MEM_PRIV0,
	DRM_BO_MEM_VRAM,
	DRM_BO_MEM_LOCAL
};

struct drm_bo_driver nouveau_bo_driver = {
	.mem_type_prio = nouveau_mem_prios,
	.mem_busy_prio = nouveau_busy_prios,
	.num_mem_type_prio = sizeof(nouveau_mem_prios)/sizeof(uint32_t),
	.num_mem_busy_prio = sizeof(nouveau_busy_prios)/sizeof(uint32_t),
	.create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
	.fence_type = nouveau_bo_fence_type,
	.invalidate_caches = nouveau_bo_invalidate_caches,
	.init_mem_type = nouveau_bo_init_mem_type,
	.evict_flags = nouveau_bo_evict_flags,
	.move = nouveau_bo_move,
	.ttm_cache_flush= nouveau_bo_flush_ttm,
	.command_stream_barrier = NULL
};
a">for (p = (*heap)->next; p != *heap;) { struct mem_block *q = p; p = p->next; drm_free(q, sizeof(*q), DRM_MEM_DRIVER); } drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER); *heap = NULL; } void nouveau_mem_close(struct drm_device *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; nouveau_mem_takedown(&dev_priv->agp_heap); nouveau_mem_takedown(&dev_priv->fb_heap); } /* returns the amount of FB ram in bytes */ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) { drm_nouveau_private_t *dev_priv=dev->dev_private; switch(dev_priv->card_type) { case NV_03: switch(NV_READ(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT) { case NV03_BOOT_0_RAM_AMOUNT_8MB: case NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM: return 8*1024*1024; case NV03_BOOT_0_RAM_AMOUNT_4MB: return 4*1024*1024; case NV03_BOOT_0_RAM_AMOUNT_2MB: return 2*1024*1024; } break; case NV_04: case NV_05: if (NV_READ(NV03_BOOT_0) & 0x00000100) { return (((NV_READ(NV03_BOOT_0) >> 12) & 0xf)*2+2)*1024*1024; } else switch(NV_READ(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT) { case NV04_BOOT_0_RAM_AMOUNT_32MB: return 32*1024*1024; case NV04_BOOT_0_RAM_AMOUNT_16MB: return 16*1024*1024; case NV04_BOOT_0_RAM_AMOUNT_8MB: return 8*1024*1024; case NV04_BOOT_0_RAM_AMOUNT_4MB: return 4*1024*1024; } break; case NV_10: case NV_20: case NV_30: case NV_40: case NV_44: case NV_50: default: // XXX won't work on BSD because of pci_read_config_dword if (dev_priv->flags&NV_NFORCE) { uint32_t mem; pci_read_config_dword(dev->pdev, 0x7C, &mem); return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; } else if(dev_priv->flags&NV_NFORCE2) { uint32_t mem; pci_read_config_dword(dev->pdev, 0x84, &mem); return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; } else { uint64_t mem; mem=(NV_READ(NV04_FIFO_DATA)&NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >> NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT; return mem*1024*1024; } break; } DRM_ERROR("Unable to detect video ram size. Please report your setup to " DRIVER_EMAIL "\n"); return 0; } int nouveau_mem_init(struct drm_device *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t fb_size; dev_priv->agp_phys=0; dev_priv->fb_phys=0; /* init AGP */ dev_priv->agp_heap=NULL; if (drm_device_is_agp(dev)) { int err; drm_agp_info_t info; drm_agp_mode_t mode; drm_agp_buffer_t agp_req; drm_agp_binding_t bind_req; err = drm_agp_acquire(dev); if (err) { DRM_ERROR("Unable to acquire AGP: %d\n", err); goto no_agp; } err = drm_agp_info(dev, &info); if (err) { DRM_ERROR("Unable to get AGP info: %d\n", err); goto no_agp; } /* see agp.h for the AGPSTAT_* modes available */ mode.mode = info.mode; err = drm_agp_enable(dev, mode); if (err) { DRM_ERROR("Unable to enable AGP: %d\n", err); goto no_agp; } agp_req.size = info.aperture_size; agp_req.type = 0; err = drm_agp_alloc(dev, &agp_req); if (err) { DRM_ERROR("Unable to alloc AGP: %d\n", err); goto no_agp; } bind_req.handle = agp_req.handle; bind_req.offset = 0; err = drm_agp_bind(dev, &bind_req); if (err) { DRM_ERROR("Unable to bind AGP: %d\n", err); goto no_agp; } if (init_heap(&dev_priv->agp_heap, info.aperture_base, info.aperture_size)) goto no_agp; dev_priv->agp_phys=info.aperture_base; } no_agp: /* Init FB */ dev_priv->fb_phys=drm_get_resource_start(dev,1); fb_size = nouveau_mem_fb_amount(dev); /* On at least NV40, RAMIN is actually at the end of vram. * We don't want to allocate this... */ if (dev_priv->card_type >= NV_40) fb_size -= dev_priv->ramin_size; DRM_DEBUG("Available VRAM: %dKiB\n", fb_size>>10); if (fb_size>256*1024*1024) { /* On cards with > 256Mb, you can't map everything. * So we create a second FB heap for that type of memory */ if (init_heap(&dev_priv->fb_heap, drm_get_resource_start(dev,1), 256*1024*1024)) return DRM_ERR(ENOMEM); if (init_heap(&dev_priv->fb_nomap_heap, drm_get_resource_start(dev,1)+256*1024*1024, fb_size-256*1024*1024)) return DRM_ERR(ENOMEM); } else { if (init_heap(&dev_priv->fb_heap, drm_get_resource_start(dev,1), fb_size)) return DRM_ERR(ENOMEM); dev_priv->fb_nomap_heap=NULL; } return 0; } struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size, int flags, DRMFILE filp) { struct mem_block *block; int type; drm_nouveau_private_t *dev_priv = dev->dev_private; /* * Init memory if needed */ if (meminit_ok==0) { nouveau_mem_init(dev); meminit_ok=1; } /* * Make things easier on ourselves: all allocations are page-aligned. * We need that to map allocated regions into the user space */ if (alignment < PAGE_SHIFT) alignment = PAGE_SHIFT; /* * Warn about 0 sized allocations, but let it go through. It'll return 1 page */ if (size == 0) DRM_INFO("warning : 0 byte allocation\n"); /* * Keep alloc size a multiple of the page size to keep drm_addmap() happy */ if (size & (~PAGE_MASK)) size = ((size/PAGE_SIZE) + 1) * PAGE_SIZE; if (flags&NOUVEAU_MEM_AGP) { type=NOUVEAU_MEM_AGP; block = alloc_block(dev_priv->agp_heap, size, alignment, filp); if (block) goto alloc_ok; } if (flags&(NOUVEAU_MEM_FB|NOUVEAU_MEM_FB_ACCEPTABLE)) { type=NOUVEAU_MEM_FB; if (!(flags&NOUVEAU_MEM_MAPPED)) { block = alloc_block(dev_priv->fb_nomap_heap, size, alignment, filp); if (block) goto alloc_ok; } block = alloc_block(dev_priv->fb_heap, size, alignment, filp); if (block) goto alloc_ok; } if (flags&NOUVEAU_MEM_AGP_ACCEPTABLE) { type=NOUVEAU_MEM_AGP; block = alloc_block(dev_priv->agp_heap, size, alignment, filp); if (block) goto alloc_ok; } return NULL; alloc_ok: block->flags=type; if (flags&NOUVEAU_MEM_MAPPED) { int ret; block->flags|=NOUVEAU_MEM_MAPPED; if (type == NOUVEAU_MEM_AGP) ret = drm_addmap(dev, block->start - dev->agp->base, block->size, _DRM_AGP, 0, &block->map); else ret = drm_addmap(dev, block->start, block->size, _DRM_FRAME_BUFFER, 0, &block->map); if (ret) { free_block(block); return NULL; } } DRM_INFO("allocated 0x%llx\n", block->start); return block; } void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) { DRM_INFO("freeing 0x%llx\n", block->start); if (meminit_ok==0) { DRM_ERROR("%s called without init\n", __FUNCTION__); return; } if (block->flags&NOUVEAU_MEM_MAPPED) drm_rmmap(dev, block->map); free_block(block); } int nouveau_instmem_init(struct drm_device *dev, uint32_t offset) { drm_nouveau_private_t *dev_priv = dev->dev_private; int ret; if (dev_priv->card_type >= NV_40) /* We'll want more instance memory than this on some NV4x cards. * There's a 16MB aperture to play with that maps onto the end * of vram. For now, only reserve a small piece until we know * more about what each chipset requires. */ dev_priv->ramin_size = (1*1024* 1024); else { /*XXX: what *are* the limits on <NV40 cards?, and does RAMIN * exist in vram on those cards as well? */ dev_priv->ramin_size = (512*1024); } DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_size>>10); /* Create a heap to manage RAMIN allocations, we don't allocate * the space that was reserved for RAMHT/FC/RO. */ ret = init_heap(&dev_priv->ramin_heap, offset, dev_priv->ramin_size - offset); if (ret) { dev_priv->ramin_heap = NULL; DRM_ERROR("Failed to init RAMIN heap\n"); } return ret; } struct mem_block *nouveau_instmem_alloc(struct drm_device *dev, uint32_t size, uint32_t align) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct mem_block *block; if (!dev_priv->ramin_heap) { DRM_ERROR("instmem alloc called without init\n"); return NULL; } block = alloc_block(dev_priv->ramin_heap, size, align, (DRMFILE)-2); if (block) { block->flags = NOUVEAU_MEM_INSTANCE; DRM_DEBUG("instance(size=%d, align=%d) alloc'd at 0x%08x\n", size, (1<<align), (uint32_t)block->start); } return block; } void nouveau_instmem_free(struct drm_device *dev, struct mem_block *block) { if (dev && block) { free_block(block); } } uint32_t nouveau_instmem_r32(drm_nouveau_private_t *dev_priv, struct mem_block *mem, int index) { uint32_t ofs = (uint32_t)mem->start + (index<<2); if (dev_priv->ramin) { #if defined(__powerpc__) return in_be32((void __iomem *)(dev_priv->ramin)->handle + ofs); #else return DRM_READ32(dev_priv->ramin, ofs); #endif } else { return NV_READ(NV_RAMIN+ofs); } } void nouveau_instmem_w32(drm_nouveau_private_t *dev_priv, struct mem_block *mem, int index, uint32_t val) { uint32_t ofs = (uint32_t)mem->start + (index<<2);