/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Rickard E. (Rik) Faith * Kevin E. Martin * Gareth Hughes * Michel Dänzer */ #ifndef __R128_DRV_H__ #define __R128_DRV_H__ #define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ #define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ typedef struct drm_r128_freelist { unsigned int age; drm_buf_t *buf; struct drm_r128_freelist *next; struct drm_r128_freelist *prev; } drm_r128_freelist_t; typedef struct drm_r128_ring_buffer { u32 *start; u32 *end; int size; int size_l2qw; volatile u32 *head; u32 tail; u32 tail_mask; int space; int high_mark; drm_local_map_t *ring_rptr; } drm_r128_ring_buffer_t; typedef struct drm_r128_private { drm_r128_ring_buffer_t ring; drm_r128_sarea_t *sarea_priv; int cce_mode; int cce_fifo_size; int cce_running; drm_r128_freelist_t *head; drm_r128_freelist_t *tail; int usec_timeout; int is_pci; unsigned long phys_pci_gart; dma_addr_t bus_pci_gart; unsigned long cce_buffers_offset; atomic_t idle_count; int page_flipping; int current_page; u32 crtc_offset; u32 crtc_offset_cntl; u32 color_fmt; unsigned int front_offset; unsigned int front_pitch; unsigned int back_offset; unsigned int back_pitch; u32 depth_fmt; unsigned int depth_offset; unsigned int depth_pitch; unsigned int span_offset; u32 front_pitch_offset_c; u32 back_pitch_offset_c; u32 depth_pitch_offset_c; u32 span_pitch_offset_c; drm_local_map_t *sarea; drm_local_map_t *fb; drm_local_map_t *mmio; drm_local_map_t *cce_ring; drm_local_map_t *ring_rptr; drm_local_map_t *buffers; drm_local_map_t *agp_textures; } drm_r128_private_t; typedef struct drm_r128_buf_priv { u32 age; int prim; int discard; int dispatched; drm_r128_freelist_t *list_entry; } drm_r128_buf_priv_t; /* r128_cce.c */ extern int r128_cce_init( DRM_IOCTL_ARGS ); extern int r128_cce_start( DRM_IOCTL_ARGS ); extern int r128_cce_stop( DRM_IOCTL_ARGS ); extern int r128_cce_reset( DRM_IOCTL_ARGS ); extern int r128_cce_idle( DRM_IOCTL_ARGS ); extern int r128_engine_reset( DRM_IOCTL_ARGS ); extern int r128_fullscreen( DRM_IOCTL_ARGS ); extern int r128_cce_buffers( DRM_IOCTL_ARGS ); extern int r128_getparam( DRM_IOCTL_ARGS ); extern void r128_freelist_reset( drm_device_t *dev ); extern drm_buf_t *r128_freelist_get( drm_device_t *dev ); extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); static __inline__ void r128_update_ring_snapshot( drm_r128_ring_buffer_t *ring ) { ring->space = (GET_RING_HEAD( ring ) - ring->tail) * sizeof(u32); if ( ring->space <= 0 ) ring->space += ring->size; } extern int r128_do_cce_idle( drm_r128_private_t *dev_priv ); extern int r128_do_cleanup_cce( drm_device_t *dev ); extern int r128_do_cleanup_pageflip( drm_device_t *dev ); /* r128_state.c */ extern int r128_cce_clear( DRM_IOCTL_ARGS ); extern int r128_cce_swap( DRM_IOCTL_ARGS ); extern int r128_cce_vertex( DRM_IOCTL_ARGS ); extern int r128_cce_indices( DRM_IOCTL_ARGS ); extern int r128_cce_blit( DRM_IOCTL_ARGS ); extern int r128_cce_depth( DRM_IOCTL_ARGS ); extern int r128_cce_stipple( DRM_IOCTL_ARGS ); extern int r128_cce_indirect( DRM_IOCTL_ARGS ); /* Register definitions, register access macros and drmAddMap constants * for Rage 128 kernel driver. */ #define R128_AUX_SC_CNTL 0x1660 # define R128_AUX1_SC_EN (1 << 0) # define R128_AUX1_SC_MODE_OR (0 << 1) # define R128_AUX1_SC_MODE_NAND (1 << 1) # define R128_AUX2_SC_EN (1 << 2) # define R128_AUX2_SC_MODE_OR (0 << 3) # define R128_AUX2_SC_MODE_NAND (1 << 3) # define R128_AUX3_SC_EN (1 << 4) # define R128_AUX3_SC_MODE_OR (0 << 5) # define R128_AUX3_SC_MODE_NAND (1 << 5) #define R128_AUX1_SC_LEFT 0x1664 #define R128_AUX1_SC_RIGHT 0x1668 #define R128_AUX1_SC_TOP 0x166c #define R128_AUX1_SC_BOTTOM 0x1670 #define R128_AUX2_SC_LEFT 0x1674 #define R128_AUX2_SC_RIGHT 0x1678 #define R128_AUX2_SC_TOP 0x167c #define R128_AUX2_SC_BOTTOM 0x1680 #define R128_AUX3_SC_LEFT 0x1684 #define R128_AUX3_SC_RIGHT 0x1688 #define R128_AUX3_SC_TOP 0x168c #define R128_AUX3_SC_BOTTOM 0x1690 #define R128_BRUSH_DATA0 0x1480 #define R128_BUS_CNTL 0x0030 # define R128_BUS_MASTER_DIS (1 << 6) #define R128_CLOCK_CNTL_INDEX 0x0008 #define R128_CLOCK_CNTL_DATA 0x000c # define R128_PLL_WR_EN (1 << 7) #define R128_CONSTANT_COLOR_C 0x1d34 #define R128_CRTC_OFFSET 0x0224 #define R128_CRTC_OFFSET_CNTL 0x0228 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) #define R128_DP_GUI_MASTER_CNTL 0x146c # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) # define R128_GMC_BRUSH_NONE (15 << 4) # define R128_GMC_DST_16BPP (4 << 8) # define R128_GMC_DST_24BPP (5 << 8) # define R128_GMC_DST_32BPP (6 << 8) # define R128_GMC_DST_DATATYPE_SHIFT 8 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) # define R128_GMC_AUX_CLIP_DIS (1 << 29) # define R128_GMC_WR_MSK_DIS (1 << 30) # define R128_ROP3_S 0x00cc0000 # define R128_ROP3_P 0x00f00000 #define R128_DP_WRITE_MASK 0x16cc #define R128_DST_PITCH_OFFSET_C 0x1c80 # define R128_DST_TILE (1 << 31) #define R128_GEN_INT_CNTL 0x0040 # define R128_CRTC_VBLANK_INT_EN (1 << 0) #define R128_GEN_INT_STATUS 0x0044 # define R128_CRTC_VBLANK_INT (1 << 0) # define R128_CRTC_VBLANK_INT_AK (1 << 0) #define R128_GEN_RESET_CNTL 0x00f0 # define R128_SOFT_RESET_GUI (1 << 0) #define R128_GUI_SCRATCH_REG0 0x15e0 #define R128_GUI_SCRATCH_REG1 0x15e4 #define R128_GUI_SCRATCH_REG2 0x15e8 #define R128_GUI_SCRATCH_REG3 0x15ec #define R128_GUI_SCRATCH_REG4 0x15f0 #define R128_GUI_SCRATCH_REG5 0x15f4 #define R128_GUI_STAT 0x1740 # define R128_GUI_FIFOCNT_MASK 0x0fff # define R128_GUI_ACTIVE (1 << 31) #define R128_MCLK_CNTL 0x000f # define R128_FORCE_GCP (1 << 16) # define R128_FORCE_PIPE3D_CP (1 << 17) # define R128_FORCE_RCP (1 << 18) #define R128_PC_GUI_CTLSTAT 0x1748 #define R128_PC_NGUI_CTLSTAT 0x0184 # define R128_PC_FLUSH_GUI (3 << 0) # define R128_PC_RI_GUI (1 << 2) # define R128_PC_FLUSH_ALL 0x00ff # define R128_PC_BUSY (1 << 31) #define R128_PCI_GART_PAGE 0x017c #define R128_PRIM_TEX_CNTL_C 0x1cb0 #define R128_SCALE_3D_CNTL 0x1a00 #define R128_SEC_TEX_CNTL_C 0x1d00 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c #define R128_SETUP_CNTL 0x1bc4 #define R128_STEN_REF_MASK_C 0x1d40 #define R128_TEX_CNTL_C 0x1c9c # define R128_TEX_CACHE_FLUSH (1 << 23) #define R128_WAIT_UNTIL 0x1720 # define R128_EVENT_CRTC_OFFSET (1 << 0) #define R128_WINDOW_XY_OFFSET 0x1bcc /* CCE registers */ #define R128_PM4_BUFFER_OFFSET 0x0700 #define R128_PM4_BUFFER_CNTL 0x0704 # define R128_PM4_MASK (15 << 28) # define R128_PM4_NONPM4 (0 << 28) # define R128_PM4_192PIO (1 << 28) # define R128_PM4_192BM (2 << 28) # define R128_PM4_128PIO_64INDBM (3 << 28) # define R128_PM4_128BM_64INDBM (4 << 28) # define R128_PM4_64PIO_128INDBM (5 << 28) # define R128_PM4_64BM_128INDBM (6 << 28) # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) #define R128_PM4_BUFFER_WM_CNTL 0x0708 # define R128_WMA_SHIFT 0 # define R128_WMB_SHIFT 8 # define R128_WMC_SHIFT 16 # define R128_WB_WM_SHIFT 24 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c #define R128_PM4_BUFFER_DL_RPTR 0x0710 #define R128_PM4_BUFFER_DL_WPTR 0x0714 # define R128_PM4_BUFFER_DL_DONE (1 << 31) #define R128_PM4_VC_FPU_SETUP 0x071c #define R128_PM4_IW_INDOFF 0x0738 #define R128_PM4_IW_INDSIZE 0x073c #define R128_PM4_STAT 0x07b8 # define R128_PM4_FIFOCNT_MASK 0x0fff # define R128_PM4_BUSY (1 << 16) # define R128_PM4_GUI_ACTIVE (1 << 31) #define R128_PM4_MICROCODE_ADDR 0x07d4 #define R128_PM4_MICROCODE_RADDR 0x07d8 #define R128_PM4_MICROCODE_DATAH 0x07dc #define R128_PM4_MICROCODE_DATAL 0x07e0 #define R128_PM4_BUFFER_ADDR 0x07f0 #define R128_PM4_MICRO_CNTL 0x07fc # define R128_PM4_MICRO_FREERUN (1 << 30) #define R128_PM4_FIFO_DATA_EVEN 0x1000 #define R128_PM4_FIFO_DATA_ODD 0x1004 /* CCE command packets */ #define R128_CCE_PACKET0 0x00000000 #define R128_CCE_PACKET1 0x40000000 #define R128_CCE_PACKET2 0x80000000 #define R128_CCE_PACKET3 0xC0000000 # define R128_CNTL_HOSTDATA_BLT 0x00009400 # define R128_CNTL_PAINT_MULTI 0x00009A00 # define R128_CNTL_BITBLT_MULTI 0x00009B00 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 #define R128_CCE_PACKET_MASK 0xC0000000 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 #define R128_CCE_PACKET0_REG_MASK 0x000007ff #define R128_CCE_PACKET1_REG0_MASK 0x000007ff #define R128_CCE_PACKET1_REG1_MASK 0x003ff800 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 #define R128_CCE_VC_CNTL_NUM_SHIFT 16 #define R128_DATATYPE_CI8 2 #define R128_DATATYPE_ARGB1555 3 #define R128_DATATYPE_RGB565 4 #define R128_DATATYPE_RGB888 5 #define R128_DATATYPE_ARGB8888 6 #define R128_DATATYPE_RGB332 7 #define R128_DATATYPE_RGB8 9 #define R128_DATATYPE_ARGB4444 15 /* Constants */ #define R128_AGP_OFFSET 0x02000000 #define R128_WATERMARK_L 16 #define R128_WATERMARK_M 8 #define R128_WATERMARK_N 8 #define R128_WATERMARK_K 128 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 #define R128_MAX_VB_AGE 0x7fffffff #define R128_MAX_VB_VERTS (0xffff) #define R128_RING_HIGH_MARK 128 #define R128_PERFORMANCE_BOXES 0 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define R128_WRITE_PLL(addr,val) \ do { \ R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ ((addr) & 0x1f) | R128_PLL_WR_EN); \ R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ } while (0) extern int R128_READ_PLL(drm_device_t *dev, int addr); #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ ((n) /* $Id$ * ffb_drv.h: Creator/Creator3D direct rendering driver. * * Copyright (C) 2000 David S. Miller (davem@redhat.com) */ /* Auxilliary clips. */ typedef struct { volatile unsigned int min; volatile unsigned int max; } ffb_auxclip, *ffb_auxclipPtr; /* FFB register set. */ typedef struct _ffb_fbc { /* Next vertex registers, on the right we list which drawops * use said register and the logical name the register has in * that context. */ /* DESCRIPTION DRAWOP(NAME) */ /*0x00*/unsigned int pad1[3]; /* Reserved */ /*0x0c*/volatile unsigned int alpha; /* ALPHA Transparency */ /*0x10*/volatile unsigned int red; /* RED */ /*0x14*/volatile unsigned int green; /* GREEN */ /*0x18*/volatile unsigned int blue; /* BLUE */ /*0x1c*/volatile unsigned int z; /* DEPTH */ /*0x20*/volatile unsigned int y; /* Y triangle(DOYF) */ /* aadot(DYF) */ /* ddline(DYF) */ /* aaline(DYF) */ /*0x24*/volatile unsigned int x; /* X triangle(DOXF) */ /* aadot(DXF) */ /* ddline(DXF) */ /* aaline(DXF) */ /*0x28*/unsigned int pad2[2]; /* Reserved */ /*0x30*/volatile unsigned int ryf; /* Y (alias to DOYF) ddline(RYF) */ /* aaline(RYF) */ /* triangle(RYF) */ /*0x34*/volatile unsigned int rxf; /* X ddline(RXF) */ /* aaline(RXF) */ /* triangle(RXF) */ /*0x38*/unsigned int pad3[2]; /* Reserved */ /*0x40*/volatile unsigned int dmyf; /* Y (alias to DOYF) triangle(DMYF) */ /*0x44*/volatile unsigned int dmxf; /* X triangle(DMXF) */ /*0x48*/unsigned int pad4[2]; /* Reserved */ /*0x50*/volatile unsigned int ebyi; /* Y (alias to RYI) polygon(EBYI) */ /*0x54*/volatile unsigned int ebxi; /* X polygon(EBXI) */ /*0x58*/unsigned int pad5[2]; /* Reserved */ /*0x60*/volatile unsigned int by; /* Y brline(RYI) */ /* fastfill(OP) */ /* polygon(YI) */ /* rectangle(YI) */ /* bcopy(SRCY) */ /* vscroll(SRCY) */ /*0x64*/volatile unsigned int bx; /* X brline(RXI) */ /* polygon(XI) */ /* rectangle(XI) */ /* bcopy(SRCX) */ /* vscroll(SRCX) */ /* fastfill(GO) */ /*0x68*/volatile unsigned int dy; /* destination Y fastfill(DSTY) */ /* bcopy(DSRY) */ /* vscroll(DSRY) */ /*0x6c*/volatile unsigned int dx; /* destination X fastfill(DSTX) */ /* bcopy(DSTX) */ /* vscroll(DSTX) */ /*0x70*/volatile unsigned int bh; /* Y (alias to RYI) brline(DYI) */ /* dot(DYI) */ /* polygon(ETYI) */ /* Height fastfill(H) */ /* bcopy(H) */ /* vscroll(H) */ /* Y count fastfill(NY) */ /*0x74*/volatile unsigned int bw; /* X dot(DXI) */ /* brline(DXI) */ /* polygon(ETXI) */ /* fastfill(W) */ /* bcopy(W) */ /* vscroll(W) */ /* fastfill(NX) */ /*0x78*/unsigned int pad6[2]; /* Reserved */ /*0x80*/unsigned int pad7[32]; /* Reserved */ /* Setup Unit's vertex state register */ /*100*/ volatile unsigned int suvtx; /*104*/ unsigned int pad8[63]; /* Reserved */ /* Frame Buffer Control Registers */ /*200*/ volatile unsigned int ppc; /* Pixel Processor Control */ /*204*/ volatile unsigned int wid; /* Current WID */ /*208*/ volatile unsigned int fg; /* FG data */ /*20c*/ volatile unsigned int bg; /* BG data */ /*210*/ volatile unsigned int consty; /* Constant Y */ /*214*/ volatile unsigned int constz; /* Constant Z */ /*218*/ volatile unsigned int xclip; /* X Clip */ /*21c*/ volatile unsigned int dcss; /* Depth Cue Scale Slope */ /*220*/ volatile unsigned int vclipmin; /* Viewclip XY Min Bounds */ /*224*/ volatile unsigned int vclipmax; /* Viewclip XY Max Bounds */ /*228*/ volatile unsigned int vclipzmin; /* Viewclip Z Min Bounds */ /*22c*/ volatile unsigned int vclipzmax; /* Viewclip Z Max Bounds */ /*230*/ volatile unsigned int dcsf; /* Depth Cue Scale Front Bound */ /*234*/ volatile unsigned int dcsb; /* Depth Cue Scale Back Bound */ /*238*/ volatile unsigned int dczf; /* Depth Cue Z Front */ /*23c*/ volatile unsigned int dczb; /* Depth Cue Z Back */ /*240*/ unsigned int pad9; /* Reserved */ /*244*/ volatile unsigned int blendc; /* Alpha Blend Control */ /*248*/ volatile unsigned int blendc1; /* Alpha Blend Color 1 */ /*24c*/ volatile unsigned int blendc2; /* Alpha Blend Color 2 */ /*250*/ volatile unsigned int fbramitc; /* FB RAM Interleave Test Control */ /*254*/ volatile unsigned int fbc; /* Frame Buffer Control */ /*258*/ volatile unsigned int rop; /* Raster OPeration */ /*25c*/ volatile unsigned int cmp; /* Frame Buffer Compare */ /*260*/ volatile unsigned int matchab; /* Buffer AB Match Mask */ /*264*/ volatile unsigned int matchc; /* Buffer C(YZ) Match Mask */ /*268*/ volatile unsigned int magnab; /* Buffer AB Magnitude Mask */ /*26c*/ volatile unsigned int magnc; /* Buffer C(YZ) Magnitude Mask */ /*270*/ volatile unsigned int fbcfg0; /* Frame Buffer Config 0 */ /*274*/ volatile unsigned int fbcfg1; /* Frame Buffer Config 1 */ /*278*/ volatile unsigned int fbcfg2; /* Frame Buffer Config 2 */ /*27c*/ volatile unsigned int fbcfg3; /* Frame Buffer Config 3 */ /*280*/ volatile unsigned int ppcfg; /* Pixel Processor Config */ /*284*/ volatile unsigned int pick; /* Picking Control */ /*288*/ volatile unsigned int fillmode; /* FillMode */ /*28c*/ volatile unsigned int fbramwac; /* FB RAM Write Address Control */ /*290*/ volatile unsigned int pmask; /* RGB PlaneMask */ /*294*/ volatile unsigned int xpmask; /* X PlaneMask */ /*298*/ volatile unsigned int ypmask; /* Y PlaneMask */ /*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */ /*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */ /* New 3dRAM III support regs */ /*2c0*/ volatile unsigned int rawblend2; /*2c4*/ volatile unsigned int rawpreblend; /*2c8*/ volatile unsigned int rawstencil; /*2cc*/ volatile unsigned int rawstencilctl; /*2d0*/ volatile unsigned int threedram1; /*2d4*/ volatile unsigned int threedram2; /*2d8*/ volatile unsigned int passin; /*2dc*/ volatile unsigned int rawclrdepth; /*2e0*/ volatile unsigned int rawpmask; /*2e4*/ volatile unsigned int rawcsrc; /*2e8*/ volatile unsigned int rawmatch; /*2ec*/ volatile unsigned int rawmagn; /*2f0*/ volatile unsigned int rawropblend; /*2f4*/ volatile unsigned int rawcmp; /*2f8*/ volatile unsigned int rawwac; /*2fc*/ volatile unsigned int fbramid; /*300*/ volatile unsigned int drawop; /* Draw OPeration */ /*304*/ unsigned int pad10[2]; /* Reserved */ /*30c*/ volatile unsigned int lpat; /* Line Pattern control */ /*310*/ unsigned int pad11; /* Reserved */ /*314*/ volatile unsigned int fontxy; /* XY Font coordinate */ /*318*/ volatile unsigned int fontw; /* Font Width */ /*31c*/ volatile unsigned int fontinc; /* Font Increment */ /*320*/ volatile unsigned int font; /* Font bits */ /*324*/ unsigned int pad12[3]; /* Reserved */ /*330*/ volatile unsigned int blend2; /*334*/ volatile unsigned int preblend; /*338*/ volatile unsigned int stencil; /*33c*/ volatile unsigned int stencilctl; /*340*/ unsigned int pad13[4]; /* Reserved */ /*350*/ volatile unsigned int dcss1; /* Depth Cue Scale Slope 1 */ /*354*/ volatile unsigned int dcss2; /* Depth Cue Scale Slope 2 */ /*358*/ volatile unsigned int dcss3; /* Depth Cue Scale Slope 3 */ /*35c*/ volatile unsigned int widpmask; /*360*/ volatile unsigned int dcs2; /*364*/ volatile unsigned int dcs3; /*368*/ volatile unsigned int dcs4; /*36c*/ unsigned int pad14; /* Reserved */ /*370*/ volatile unsigned int dcd2; /*374*/ volatile unsigned int dcd3; /*378*/ volatile unsigned int dcd4; /*37c*/ unsigned int pad15; /* Reserved */ /*380*/ volatile unsigned int pattern[32]; /* area Pattern */ /*400*/ unsigned int pad16[8]; /* Reserved */ /*420*/ volatile unsigned int reset; /* chip RESET */ /*424*/ unsigned int pad17[247]; /* Reserved */ /*800*/ volatile unsigned int devid; /* Device ID */ /*804*/ unsigned int pad18[63]; /* Reserved */ /*900*/ volatile unsigned int ucsr; /* User Control & Status Register */ /*904*/ unsigned int pad19[31]; /* Reserved */ /*980*/ volatile unsigned int mer; /* Mode Enable Register */ /*984*/ unsigned int pad20[1439]; /* Reserved */ } ffb_fbc, *ffb_fbcPtr; struct ffb_hw_context { int is_2d_only; unsigned int ppc; unsigned int wid; unsigned int fg; unsigned int bg; unsigned int consty; unsigned int constz; unsigned int xclip; unsigned int dcss; unsigned int vclipmin; unsigned int vclipmax; unsigned int vclipzmin; unsigned int vclipzmax; unsigned int dcsf; unsigned int dcsb; unsigned int dczf; unsigned int dczb; unsigned int blendc; unsigned int blendc1; unsigned int blendc2; unsigned int fbc; unsigned int rop; unsigned int cmp; unsigned int matchab; unsigned int matchc; unsigned int magnab; unsigned int magnc; unsigned int pmask; unsigned int xpmask; unsigned int ypmask; unsigned int zpmask; unsigned int auxclip0min; unsigned int auxclip0max; unsigned int auxclip1min; unsigned int auxclip1max; unsigned int auxclip2min; unsigned int auxclip2max; unsigned int auxclip3min; unsigned int auxclip3max; unsigned int drawop; unsigned int lpat; unsigned int fontxy; unsigned int fontw; unsigned int fontinc; unsigned int area_pattern[32]; unsigned int ucsr; unsigned int stencil; unsigned int stencilctl; unsigned int dcss1; unsigned int dcss2; unsigned int dcss3; unsigned int dcs2; unsigned int dcs3; unsigned int dcs4; unsigned int dcd2; unsigned int dcd3; unsigned int dcd4; unsigned int mer; }; #define FFB_MAX_CTXS 32 enum ffb_chip_type { ffb1_prototype = 0, /* Early pre-FCS FFB */ ffb1_standard, /* First FCS FFB, 100Mhz UPA, 66MHz gclk */ ffb1_speedsort, /* Second FCS FFB, 100Mhz UPA, 75MHz gclk */ ffb2_prototype, /* Early pre-FCS vertical FFB2 */ ffb2_vertical, /* First FCS FFB2/vertical, 100Mhz UPA, 100MHZ gclk, 75(SingleBuffer)/83(DoubleBuffer) MHz fclk */ ffb2_vertical_plus, /* Second FCS FFB2/vertical, same timings */ ffb2_horizontal, /* First FCS FFB2/horizontal, same timings as FFB2/vert */ ffb2_horizontal_plus, /* Second FCS FFB2/horizontal, same timings */ afb_m3, /* FCS Elite3D, 3 float chips */ afb_m6 /* FCS Elite3D, 6 float chips */ }; typedef struct ffb_dev_priv { /* Misc software state. */ int prom_node; enum ffb_chip_type ffb_type; u64 card_phys_base; struct miscdevice miscdev; /* Controller registers. */ ffb_fbcPtr regs; /* Context table. */ struct ffb_hw_context *hw_state[FFB_MAX_CTXS]; } ffb_dev_priv_t; extern unsigned long ffb_get_unmapped_area(struct file *filp, unsigned long hint, unsigned long len, unsigned long pgoff, unsigned long flags); extern unsigned long ffb_driver_get_map_ofs(drm_map_t *map) extern unsigned long ffb_driver_get_reg_ofs(struct drm_device *dev)
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