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path: root/linux-core/drm_fops.c
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/**
 * \file drm_fops.c
 * File operations for DRM
 *
 * \author Rickard E. (Rik) Faith <faith@valinux.com>
 * \author Daryll Strauss <daryll@valinux.com>
 * \author Gareth Hughes <gareth@valinux.com>
 */

/*
 * Created: Mon Jan  4 08:58:31 1999 by faith@valinux.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "drm_sarea.h"
#include <linux/poll.h>

static int drm_open_helper(struct inode *inode, struct file *filp,
			   struct drm_device * dev);

static int drm_setup(struct drm_device * dev)
{
	int i;
	int ret;

	if (dev->driver->firstopen) {
		ret = dev->driver->firstopen(dev);
		if (ret != 0)
			return ret;
	}

	atomic_set(&dev->ioctl_count, 0);
	atomic_set(&dev->vma_count, 0);
	dev->buf_use = 0;
	atomic_set(&dev->buf_alloc, 0);

	if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) {
		i = drm_dma_setup(dev);
		if (i < 0)
			return i;
	}

	for (i = 0; i < ARRAY_SIZE(dev->counts); i++)
		atomic_set(&dev->counts[i], 0);

	dev->sigdata.lock = NULL;

	dev->queue_count = 0;
	dev->queue_reserved = 0;
	dev->queue_slots = 0;
	dev->queuelist = NULL;
	dev->context_flag = 0;
	dev->interrupt_flag = 0;
	dev->dma_flag = 0;
	dev->last_context = 0;
	dev->last_switch = 0;
	dev->last_checked = 0;
	init_waitqueue_head(&dev->context_wait);
	dev->if_version = 0;

	dev->ctx_start = 0;
	dev->lck_start = 0;

	dev->buf_async = NULL;
	init_waitqueue_head(&dev->buf_readers);
	init_waitqueue_head(&dev->buf_writers);

	DRM_DEBUG("\n");

	/*
	 * The kernel's context could be created here, but is now created
	 * in drm_dma_enqueue.  This is more resource-efficient for
	 * hardware that does not do DMA, but may mean that
	 * drm_select_queue fails between the time the interrupt is
	 * initialized and the time the queues are initialized.
	 */

	return 0;
}

/**
 * Open file.
 *
 * \param inode device inode
 * \param filp file pointer.
 * \return zero on success or a negative number on failure.
 *
 * Searches the DRM device with the same minor number, calls open_helper(), and
 * increments the device open count. If the open count was previous at zero,
 * i.e., it's the first that the device is open, then calls setup().
 */
int drm_open(struct inode *inode, struct file *filp)
{
	struct drm_device *dev = NULL;
	int minor_id = iminor(inode);
	struct drm_minor *minor;
	int retcode = 0;

	minor = idr_find(&drm_minors_idr, minor_id);
	if (!minor)
		return -ENODEV;

	if (!(dev = minor->dev))
		return -ENODEV;

	retcode = drm_open_helper(inode, filp, dev);
	if (!retcode) {
		atomic_inc(&dev->counts[_DRM_STAT_OPENS]);
		spin_lock(&dev->count_lock);
		if (!dev->open_count++) {
			spin_unlock(&dev->count_lock);
			retcode = drm_setup(dev);
			goto out;
		}
		spin_unlock(&dev->count_lock);
	}

out:
	mutex_lock(&dev->struct_mutex);
	BUG_ON((dev->dev_mapping != NULL) &&
	       (dev->dev_mapping != inode->i_mapping));
	if (dev->dev_mapping == NULL)
		dev->dev_mapping = inode->i_mapping;
	mutex_unlock(&dev->struct_mutex);

	return retcode;
}
EXPORT_SYMBOL(drm_open);

/**
 * File \c open operation.
 *
 * \param inode device inode.
 * \param filp file pointer.
 *
 * Puts the dev->fops corresponding to the device minor number into
 * \p filp, call the \c open method, and restore the file operations.
 */
int drm_stub_open(struct inode *inode, struct file *filp)
{
	struct drm_device *dev = NULL;
	struct drm_minor *minor;
	int minor_id = iminor(inode);
	int err = -ENODEV;
	const struct file_operations *old_fops;

	DRM_DEBUG("\n");

	minor = idr_find(&drm_minors_idr, minor_id);
	if (!minor)
		return -ENODEV;
	
	if (!(dev = minor->dev))
		return -ENODEV;

	old_fops = filp->f_op;
	filp->f_op = fops_get(&dev->driver->fops);
	if (filp->f_op->open && (err = filp->f_op->open(inode, filp))) {
		fops_put(filp->f_op);
		filp->f_op = fops_get(old_fops);
	}
	fops_put(old_fops);

	return err;
}

/**
 * Check whether DRI will run on this CPU.
 *
 * \return non-zero if the DRI will run on this CPU, or zero otherwise.
 */
static int drm_cpu_valid(void)
{
#if defined(__i386__)
	if (boot_cpu_data.x86 == 3)
		return 0;	/* No cmpxchg on a 386 */
#endif
#if defined(__sparc__) && !defined(__sparc_v9__)
	return 0;		/* No cmpxchg before v9 sparc. */
#endif
	return 1;
}

/**
 * Called whenever a process opens /dev/drm.
 *
 * \param inode device inode.
 * \param filp file pointer.
 * \param dev device.
 * \return zero on success or a negative number on failure.
 *
 * Creates and initializes a drm_file structure for the file private data in \p
 * filp and add it into the double linked list in \p dev.
 */
static int drm_open_helper(struct inode *inode, struct file *filp,
			   struct drm_device * dev)
{
	int minor_id = iminor(inode);
	struct drm_file *priv;
	int ret;
	int i, j;

	if (filp->f_flags & O_EXCL)
		return -EBUSY;	/* No exclusive opens */
	if (!drm_cpu_valid())
		return -EINVAL;

	DRM_DEBUG("pid = %d, minor = %d\n", current->pid, minor_id);

	priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES);
	if (!priv)
		return -ENOMEM;

	memset(priv, 0, sizeof(*priv));
	filp->private_data = priv;
	priv->filp = filp;
	priv->uid = current->euid;
	priv->pid = current->pid;
	priv->minor = idr_find(&drm_minors_idr, minor_id);
	priv->ioctl_count = 0;
	/* for compatibility root is always authenticated */
	priv->authenticated = capable(CAP_SYS_ADMIN);
	priv->lock_count = 0;

	INIT_LIST_HEAD(&priv->lhead);
	INIT_LIST_HEAD(&priv->refd_objects);
	INIT_LIST_HEAD(&priv->fbs);

	for (i = 0; i < _DRM_NO_REF_TYPES; ++i) {
		ret = drm_ht_create(&priv->refd_object_hash[i],
				    DRM_FILE_HASH_ORDER);
		if (ret)
			break;
	}

	if (ret) {
		for (j = 0; j < i; ++j)
			drm_ht_remove(&priv->refd_object_hash[j]);
		goto out_free;
	}

	if (dev->driver->open) {
		ret = dev->driver->open(dev, priv);
		if (ret < 0)
			goto out_free;
	}


	/* if there is no current master make this fd it */
	mutex_lock(&dev->struct_mutex);
	if (!priv->minor->master) {
		priv->minor->master = drm_get_master(priv->minor);
		if (!priv->minor->master) {
			ret = -ENOMEM;
			goto out_free;
		}

		priv->is_master = 1;
		priv->master = priv->minor->master;

		mutex_unlock(&dev->struct_mutex);
		if (dev->driver->master_create) {
			ret = dev->driver->master_create(dev, priv->master);
			if (ret) {
				drm_put_master(priv->minor->master);
				priv->minor->master = priv->master = NULL;
				mutex_unlock(&dev->struct_mutex);
				goto out_free;
			}
		}
	} else {
		priv->master = priv->minor->master;
		mutex_unlock(&dev->struct_mutex);
	}

	mutex_lock(&dev->struct_mutex);
	list_add(&priv->lhead, &dev->filelist);
	mutex_unlock(&dev->struct_mutex);

#ifdef __alpha__
	/*
	 * Default the hose
	 */
	if (!dev->hose) {
		struct pci_dev *pci_dev;
		pci_dev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, NULL);
		if (pci_dev) {
			dev->hose = pci_dev->sysdata;
			pci_dev_put(pci_dev);
		}
		if (!dev->hose) {
			struct pci_bus *b = pci_bus_b(pci_root_buses.next);
			if (b)
				dev->hose = b->sysdata;
		}
	}
#endif

	return 0;
      out_free:
	drm_free(priv, sizeof(*priv), DRM_MEM_FILES);
	filp->private_data = NULL;
	return ret;
}

/** No-op. */
int drm_fasync(int fd, struct file *filp, int on)
{
	struct drm_file *priv = filp->private_data;
	struct drm_device *dev = priv->minor->dev;
	int retcode;

	DRM_DEBUG("fd = %d, device = 0x%lx\n", fd,
		  (long)old_encode_dev(priv->minor->device));
	retcode = fasync_helper(fd, filp, on, &dev->buf_async);
	if (retcode < 0)
		return retcode;
	return 0;
}
EXPORT_SYMBOL(drm_fasync);

static void drm_object_release(struct file *filp)
{
	struct drm_file *priv = filp->private_data;
	struct list_head *head;
	struct drm_ref_object *ref_object;
	int i;

	/*
	 * Free leftover ref objects created by me. Note that we cannot use
	 * list_for_each() here, as the struct_mutex may be temporarily
	 * released by the remove_() functions, and thus the lists may be
	 * altered.
	 * Also, a drm_remove_ref_object() will not remove it
	 * from the list unless its refcount is 1.
	 */

	head = &priv->refd_objects;
	while (head->next != head) {
		ref_object = list_entry(head->next, struct drm_ref_object, list);
		drm_remove_ref_object(priv, ref_object);
		head = &priv->refd_objects;
	}

	for (i = 0; i < _DRM_NO_REF_TYPES; ++i)
		drm_ht_remove(&priv->refd_object_hash[i]);
}

/**
 * Release file.
 *
 * \param inode device inode
 * \param file_priv DRM file private.
 * \return zero on success or a negative number on failure.
 *
 * If the hardware lock is held then free it, and take it again for the kernel
 * context since it's necessary to reclaim buffers. Unlink the file private
 * data from its list and free it. Decreases the open count and if it reaches
 * zero calls drm_lastclose().
 */
int drm_release(struct inode *inode, struct file *filp)
{
	struct drm_file *file_priv = filp->private_data;
	struct drm_device *dev = file_priv->minor->dev;
	int retcode = 0;

	lock_kernel();

	DRM_DEBUG("open_count = %d\n", dev->open_count);

	if (dev->driver->preclose)
		dev->driver->preclose(dev, file_priv);

	/* ========================================================
	 * Begin inline drm_release
	 */

	DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n",
		  current->pid, (long)old_encode_dev(file_priv->minor->device),
		  dev->open_count);

	if (dev->driver->reclaim_buffers_locked && file_priv->master->lock.hw_lock) {
		if (drm_i_have_hw_lock(dev, file_priv)) {
			dev->driver->reclaim_buffers_locked(dev, file_priv);
		} else {
			unsigned long _end=jiffies + 3*DRM_HZ;
			int locked = 0;

			drm_idlelock_take(&file_priv->master->lock);

			/*
			 * Wait for a while.
			 */

			do{
				spin_lock(&file_priv->master->lock.spinlock);
				locked = file_priv->master->lock.idle_has_lock;
				spin_unlock(&file_priv->master->lock.spinlock);
				if (locked)
					break;
				schedule();
			} while (!time_after_eq(jiffies, _end));

			if (!locked) {
				DRM_ERROR("reclaim_buffers_locked() deadlock. Please rework this\n"
					  "\tdriver to use reclaim_buffers_idlelocked() instead.\n"
					  "\tI will go on reclaiming the buffers anyway.\n");
			}

			dev->driver->reclaim_buffers_locked(dev, file_priv);
			drm_idlelock_release(&file_priv->master->lock);
		}
	}

	if (dev->driver->reclaim_buffers_idlelocked && file_priv->master->lock.hw_lock) {

		drm_idlelock_take(&file_priv->master->lock);
		dev->driver->reclaim_buffers_idlelocked(dev, file_priv);
		drm_idlelock_release(&file_priv->master->lock);

	}

	if (drm_i_have_hw_lock(dev, file_priv)) {
		DRM_DEBUG("File %p released, freeing lock for context %d\n",
			  filp, _DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));

		drm_lock_free(&file_priv->master->lock,
			      _DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));
	}


	if (drm_core_check_feature(dev, DRIVER_HAVE_DMA) &&
	    !dev->driver->reclaim_buffers_locked) {
		dev->driver->reclaim_buffers(dev, file_priv);
	}

	drm_fasync(-1, filp, 0);

	mutex_lock(&dev->ctxlist_mutex);

	if (!list_empty(&dev->ctxlist)) {
		struct drm_ctx_list *pos, *n;

		list_for_each_entry_safe(pos, n, &dev->ctxlist, head) {
			if (pos->tag == file_priv &&
			    pos->handle != DRM_KERNEL_CONTEXT) {
				if (dev->driver->context_dtor)
					dev->driver->context_dtor(dev,
								  pos->handle);

				drm_ctxbitmap_free(dev, pos->handle);

				list_del(&pos->head);
				drm_free(pos, sizeof(*pos), DRM_MEM_CTXLIST);
				--dev->ctx_count;
			}
		}
	}
	mutex_unlock(&dev->ctxlist_mutex);

	if (drm_core_check_feature(dev, DRIVER_MODESET))
		drm_fb_release(filp);

	file_priv->master = NULL;

	if (file_priv->is_master) {
	       drm_put_master(file_priv->minor->master);
	       file_priv->minor->master = NULL;
	}

	mutex_lock(&dev->struct_mutex);
	drm_object_release(filp);
	if (file_priv->remove_auth_on_close == 1) {
		struct drm_file *temp;

		list_for_each_entry(temp, &dev->filelist, lhead)
			temp->authenticated = 0;
	}
	list_del(&file_priv->lhead);


	mutex_unlock(&dev->struct_mutex);

	if (dev->driver->postclose)
		dev->driver->postclose(dev, file_priv);
	drm_free(file_priv, sizeof(*file_priv), DRM_MEM_FILES);

	/* ========================================================
	 * End inline drm_release
	 */

	atomic_inc(&dev->counts[_DRM_STAT_CLOSES]);
	spin_lock(&dev->count_lock);
	if (!--dev->open_count) {
		if (atomic_read(&dev->ioctl_count)) {
			DRM_ERROR("Device busy: %d\n",
				  atomic_read(&dev->ioctl_count));
			spin_unlock(&dev->count_lock);
			unlock_kernel();
			return -EBUSY;
		}
		spin_unlock(&dev->count_lock);
		unlock_kernel();
		return drm_lastclose(dev);
	}
	spin_unlock(&dev->count_lock);

	unlock_kernel();

	return retcode;
}
EXPORT_SYMBOL(drm_release);

/** No-op. */
/* This is to deal with older X servers that believe 0 means data is
 * available which is not the correct return for a poll function.
 * This cannot be fixed until the Xserver is fixed. Xserver will need
 * to set a newer interface version to avoid breaking older Xservers.
 * Without fixing the Xserver you get: "WaitForSomething(): select: errno=22"
 * http://freedesktop.org/bugzilla/show_bug.cgi?id=1505 if you try
 * to return the correct response.
 */
unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait)
{
	/* return (POLLIN | POLLOUT | POLLRDNORM | POLLWRNORM); */
	return 0;
}
EXPORT_SYMBOL(drm_poll);
( tex->tex_border_color ); ADVANCE_RING(); } static inline void r128_emit_tex1( drm_r128_private_t *dev_priv ) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; int i; RING_LOCALS; DRM_DEBUG( " %s\n", __FUNCTION__ ); BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS ); OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS ) ); OUT_RING( tex->tex_cntl ); OUT_RING( tex->tex_combine_cntl ); for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { OUT_RING( tex->tex_offset[i] ); } OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); OUT_RING( tex->tex_border_color ); ADVANCE_RING(); } static inline void r128_emit_state( drm_r128_private_t *dev_priv ) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); if ( dirty & R128_UPLOAD_CORE ) { r128_emit_core( dev_priv ); sarea_priv->dirty &= ~R128_UPLOAD_CORE; } if ( dirty & R128_UPLOAD_CONTEXT ) { r128_emit_context( dev_priv ); sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; } if ( dirty & R128_UPLOAD_SETUP ) { r128_emit_setup( dev_priv ); sarea_priv->dirty &= ~R128_UPLOAD_SETUP; } if ( dirty & R128_UPLOAD_MASKS ) { r128_emit_masks( dev_priv ); sarea_priv->dirty &= ~R128_UPLOAD_MASKS; } if ( dirty & R128_UPLOAD_WINDOW ) { r128_emit_window( dev_priv ); sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; } if ( dirty & R128_UPLOAD_TEX0 ) { r128_emit_tex0( dev_priv ); sarea_priv->dirty &= ~R128_UPLOAD_TEX0; } if ( dirty & R128_UPLOAD_TEX1 ) { r128_emit_tex1( dev_priv ); sarea_priv->dirty &= ~R128_UPLOAD_TEX1; } /* Turn off the texture cache flushing */ sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; } #if R128_PERFORMANCE_BOXES /* ================================================================ * Performance monitoring functions */ static void r128_clear_box( drm_r128_private_t *dev_priv, int x, int y, int w, int h, int r, int g, int b ) { u32 pitch, offset; u32 fb_bpp, color; RING_LOCALS; switch ( dev_priv->fb_bpp ) { case 16: fb_bpp = R128_GMC_DST_16BPP; color = (((r & 0xf8) << 8) | ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); break; case 24: fb_bpp = R128_GMC_DST_24BPP; color = ((r << 16) | (g << 8) | b); break; case 32: fb_bpp = R128_GMC_DST_32BPP; color = (((0xff) << 24) | (r << 16) | (g << 8) | b); break; default: return; } offset = dev_priv->back_offset; pitch = dev_priv->back_pitch >> 3; BEGIN_RING( 6 ); OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | fb_bpp | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS ); OUT_RING( (pitch << 21) | (offset >> 5) ); OUT_RING( color ); OUT_RING( (x << 16) | y ); OUT_RING( (w << 16) | h ); ADVANCE_RING(); } static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) { if ( atomic_read( &dev_priv->idle_count ) == 0 ) { r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); } else { atomic_set( &dev_priv->idle_count, 0 ); } } #endif /* ================================================================ * CCE command dispatch functions */ static void r128_print_dirty( const char *msg, unsigned int flags ) { DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", msg, flags, (flags & R128_UPLOAD_CORE) ? "core, " : "", (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", (flags & R128_UPLOAD_SETUP) ? "setup, " : "", (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", (flags & R128_UPLOAD_MASKS) ? "masks, " : "", (flags & R128_UPLOAD_WINDOW) ? "window, " : "", (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); } static void r128_cce_dispatch_clear( drm_device_t *dev, drm_r128_clear_t *clear ) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; unsigned int flags = clear->flags; int i; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); r128_update_ring_snapshot( dev_priv ); if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { unsigned int tmp = flags; flags &= ~(R128_FRONT | R128_BACK); if ( tmp & R128_FRONT ) flags |= R128_BACK; if ( tmp & R128_BACK ) flags |= R128_FRONT; } for ( i = 0 ; i < nbox ; i++ ) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2, flags ); if ( flags & (R128_FRONT | R128_BACK) ) { BEGIN_RING( 2 ); OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); OUT_RING( clear->color_mask ); ADVANCE_RING(); } if ( flags & R128_FRONT ) { BEGIN_RING( 6 ); OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->color_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS ); OUT_RING( dev_priv->front_pitch_offset_c ); OUT_RING( clear->clear_color ); OUT_RING( (x << 16) | y ); OUT_RING( (w << 16) | h ); ADVANCE_RING(); } if ( flags & R128_BACK ) { BEGIN_RING( 6 ); OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->color_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS ); OUT_RING( dev_priv->back_pitch_offset_c ); OUT_RING( clear->clear_color ); OUT_RING( (x << 16) | y ); OUT_RING( (w << 16) | h ); ADVANCE_RING(); } if ( flags & R128_DEPTH ) { BEGIN_RING( 6 ); OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS ); OUT_RING( dev_priv->depth_pitch_offset_c ); OUT_RING( clear->clear_depth ); OUT_RING( (x << 16) | y ); OUT_RING( (w << 16) | h ); ADVANCE_RING(); } } } static void r128_cce_dispatch_swap( drm_device_t *dev ) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int i; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); r128_update_ring_snapshot( dev_priv ); #if R128_PERFORMANCE_BOXES /* Do some trivial performance monitoring... */ r128_cce_performance_boxes( dev_priv ); #endif for ( i = 0 ; i < nbox ; i++ ) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; BEGIN_RING( 7 ); OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_NONE | (dev_priv->color_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_S | R128_DP_SRC_SOURCE_MEMORY | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS ); OUT_RING( dev_priv->back_pitch_offset_c ); OUT_RING( dev_priv->front_pitch_offset_c ); OUT_RING( (x << 16) | y ); OUT_RING( (x << 16) | y ); OUT_RING( (w << 16) | h ); ADVANCE_RING(); } /* Increment the frame counter. The client-side 3D driver must * throttle the framerate by waiting for this value before * performing the swapbuffer ioctl. */ dev_priv->sarea_priv->last_frame++; BEGIN_RING( 2 ); OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); OUT_RING( dev_priv->sarea_priv->last_frame ); ADVANCE_RING(); } static void r128_cce_dispatch_flip( drm_device_t *dev ) { drm_r128_private_t *dev_priv = dev->dev_private; RING_LOCALS; DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page ); r128_update_ring_snapshot( dev_priv ); #if R128_PERFORMANCE_BOXES /* Do some trivial performance monitoring... */ r128_cce_performance_boxes( dev_priv ); #endif BEGIN_RING( 4 ); R128_WAIT_UNTIL_PAGE_FLIPPED(); OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) ); if ( dev_priv->current_page == 0 ) { OUT_RING( dev_priv->back_offset ); dev_priv->current_page = 1; } else { OUT_RING( dev_priv->front_offset ); dev_priv->current_page = 0; } ADVANCE_RING(); /* Increment the frame counter. The client-side 3D driver must * throttle the framerate by waiting for this value before * performing the swapbuffer ioctl. */ dev_priv->sarea_priv->last_frame++; BEGIN_RING( 2 ); OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); OUT_RING( dev_priv->sarea_priv->last_frame ); ADVANCE_RING(); } static void r128_cce_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int format = sarea_priv->vc_format; int offset = buf->bus_address; int size = buf->used; int prim = buf_priv->prim; int i = 0; RING_LOCALS; DRM_DEBUG( "%s: buf=%d nbox=%d\n", __FUNCTION__, buf->idx, sarea_priv->nbox ); r128_update_ring_snapshot( dev_priv ); if ( 0 ) r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); if ( buf->used ) { buf_priv->dispatched = 1; if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { r128_emit_state( dev_priv ); } do { /* Emit the next set of up to three cliprects */ if ( i < sarea_priv->nbox ) { r128_emit_clip_rects( dev_priv, &sarea_priv->boxes[i], sarea_priv->nbox - i ); } /* Emit the vertex buffer rendering commands */ BEGIN_RING( 5 ); OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); OUT_RING( offset ); OUT_RING( size ); OUT_RING( format ); OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); ADVANCE_RING(); i += 3; } while ( i < sarea_priv->nbox ); } if ( buf_priv->discard ) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ BEGIN_RING( 2 ); OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); OUT_RING( buf_priv->age ); ADVANCE_RING(); buf->pending = 1; buf->used = 0; /* FIXME: Check dispatched field */ buf_priv->dispatched = 0; } dev_priv->sarea_priv->last_dispatch++; sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; sarea_priv->nbox = 0; } static void r128_cce_dispatch_indirect( drm_device_t *dev, drm_buf_t *buf, int start, int end ) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; RING_LOCALS; DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end ); r128_update_ring_snapshot( dev_priv ); if ( start != end ) { int offset = buf->bus_address + start; int dwords = (end - start + 3) / sizeof(u32); /* Indirect buffer data must be an even number of * dwords, so if we've been given an odd number we must * pad the data with a Type-2 CCE packet. */ if ( dwords & 1 ) { u32 *data = (u32 *) ((char *)dev_priv->buffers->handle + buf->offset + start); data[dwords++] = R128_CCE_PACKET2; } buf_priv->dispatched = 1; /* Fire off the indirect buffer */ BEGIN_RING( 3 ); OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); OUT_RING( offset ); OUT_RING( dwords ); ADVANCE_RING(); } if ( buf_priv->discard ) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the indirect buffer age */ BEGIN_RING( 2 ); OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); OUT_RING( buf_priv->age ); ADVANCE_RING(); buf->pending = 1; buf->used = 0; /* FIXME: Check dispatched field */ buf_priv->dispatched = 0; } dev_priv->sarea_priv->last_dispatch++; } static void r128_cce_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, int start, int end, int count ) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int format = sarea_priv->vc_format; int offset = dev_priv->buffers->offset - dev->agp->base; int prim = buf_priv->prim; u32 *data; int dwords; int i = 0; RING_LOCALS; DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); r128_update_ring_snapshot( dev_priv ); if ( 0 ) r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); if ( start != end ) { buf_priv->dispatched = 1; if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { r128_emit_state( dev_priv ); } dwords = (end - start + 3) / sizeof(u32); data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset + start); data[0] = CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); data[1] = offset; data[2] = R128_MAX_VB_VERTS; data[3] = format; data[4] = (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | (count << 16)); if ( count & 0x1 ) { data[dwords-1] &= 0x0000ffff; } do { /* Emit the next set of up to three cliprects */ if ( i < sarea_priv->nbox ) { r128_emit_clip_rects( dev_priv, &sarea_priv->boxes[i], sarea_priv->nbox - i ); } r128_cce_dispatch_indirect( dev, buf, start, end ); i += 3; } while ( i < sarea_priv->nbox ); } if ( buf_priv->discard ) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ BEGIN_RING( 2 ); OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); OUT_RING( buf_priv->age ); ADVANCE_RING(); buf->pending = 1; /* FIXME: Check dispatched field */ buf_priv->dispatched = 0; } dev_priv->sarea_priv->last_dispatch++; sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; sarea_priv->nbox = 0; } static int r128_cce_dispatch_blit( drm_device_t *dev, drm_r128_blit_t *blit ) { drm_r128_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_r128_buf_priv_t *buf_priv; u32 *data; int dword_shift, dwords; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); r128_update_ring_snapshot( dev_priv ); /* The compiler won't optimize away a division by a variable, * even if the only legal values are powers of two. Thus, we'll * use a shift instead. */ switch ( blit->format ) { case R128_DATATYPE_ARGB8888: dword_shift = 0; break; case R128_DATATYPE_ARGB1555: case R128_DATATYPE_RGB565: case R128_DATATYPE_ARGB4444: dword_shift = 1; break; case R128_DATATYPE_CI8: case R128_DATATYPE_RGB8: dword_shift = 2; break; default: DRM_ERROR( "invalid blit format %d\n", blit->format ); return -EINVAL; } /* Flush the pixel cache, and mark the contents as Read Invalid. * This ensures no pixel data gets mixed up with the texture * data from the host data blit, otherwise part of the texture * image may be corrupted. */ BEGIN_RING( 2 ); OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); ADVANCE_RING(); /* Dispatch the indirect buffer. */ buf = dma->buflist[blit->idx]; buf_priv = buf->dev_private; if ( buf->pid != current->pid ) { DRM_ERROR( "process %d using buffer owned by %d\n", current->pid, buf->pid ); return -EINVAL; } if ( buf->pending ) { DRM_ERROR( "sending pending buffer %d\n", blit->idx ); return -EINVAL; } buf_priv->discard = 1; dwords = (blit->width * blit->height) >> dword_shift; data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset); data[0] = CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ); data[1] = (R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_NONE | (blit->format << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_S | R128_DP_SRC_SOURCE_HOST_DATA | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); data[2] = (blit->pitch << 21) | (blit->offset >> 5); data[3] = 0xffffffff; data[4] = 0xffffffff; data[5] = (blit->y << 16) | blit->x; data[6] = (blit->height << 16) | blit->width; data[7] = dwords; buf->used = (dwords + 8) * sizeof(u32); r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); /* Flush the pixel cache after the blit completes. This ensures * the texture data is written out to memory before rendering * continues. */ BEGIN_RING( 2 ); OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); OUT_RING( R128_PC_FLUSH_GUI ); ADVANCE_RING(); return 0; } /* ================================================================ * Tiled depth buffer management * * FIXME: These should all set the destination write mask for when we * have hardware stencil support. */ static int r128_cce_dispatch_write_span( drm_device_t *dev, drm_r128_depth_t *depth ) { drm_r128_private_t *dev_priv = dev->dev_private; int count, x, y; u32 *buffer; u8 *mask; int i; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); r128_update_ring_snapshot( dev_priv ); count = depth->n; if ( copy_from_user( &x, depth->x, sizeof(x) ) ) { return -EFAULT; } if ( copy_from_user( &y, depth->y, sizeof(y) ) ) { return -EFAULT; } buffer = kmalloc( depth->n * sizeof(u32), 0 ); if ( buffer == NULL ) return -ENOMEM; if ( copy_from_user( buffer, depth->buffer, depth->n * sizeof(u32) ) ) { kfree( buffer ); return -EFAULT; } if ( depth->mask ) { mask = kmalloc( depth->n * sizeof(u8), 0 ); if ( mask == NULL ) { kfree( buffer ); return -ENOMEM; } if ( copy_from_user( mask, depth->mask, depth->n * sizeof(u8) ) ) { kfree( buffer ); kfree( mask ); return -EFAULT; } for ( i = 0 ; i < count ; i++, x++ ) { if ( mask[i] ) { BEGIN_RING( 6 ); OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS ); OUT_RING( dev_priv->depth_pitch_offset_c ); OUT_RING( buffer[i] ); OUT_RING( (x << 16) | y ); OUT_RING( (1 << 16) | 1 ); ADVANCE_RING(); } } kfree( mask ); } else { for ( i = 0 ; i < count ; i++, x++ ) { BEGIN_RING( 6 ); OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS ); OUT_RING( dev_priv->depth_pitch_offset_c ); OUT_RING( buffer[i] ); OUT_RING( (x << 16) | y ); OUT_RING( (1 << 16) | 1 ); ADVANCE_RING(); } } kfree( buffer ); return 0; } static int r128_cce_dispatch_write_pixels( drm_device_t *dev, drm_r128_depth_t *depth ) { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; u32 *buffer; u8 *mask; int i; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); r128_update_ring_snapshot( dev_priv ); count = depth->n; x = kmalloc( count * sizeof(*x), 0 ); if ( x == NULL ) { return -ENOMEM; } y = kmalloc( count * sizeof(*y), 0 ); if ( y == NULL ) { kfree( x ); return -ENOMEM; } if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) { kfree( x ); kfree( y ); return -EFAULT; } if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) { kfree( x ); kfree( y ); return -EFAULT; } buffer = kmalloc( depth->n * sizeof(u32), 0 ); if ( buffer == NULL ) { kfree( x ); kfree( y ); return -ENOMEM; } if ( copy_from_user( buffer, depth->buffer, depth->n * sizeof(u32) ) ) { kfree( x ); kfree( y ); kfree( buffer ); return -EFAULT; } if ( depth->mask ) { mask = kmalloc( depth->n * sizeof(u8), 0 ); if ( mask == NULL ) { kfree( x ); kfree( y ); kfree( buffer ); return -ENOMEM; } if ( copy_from_user( mask, depth->mask, depth->n * sizeof(u8) ) ) { kfree( x ); kfree( y ); kfree( buffer ); kfree( mask ); return -EFAULT; } for ( i = 0 ; i < count ; i++ ) { if ( mask[i] ) { BEGIN_RING( 6 ); OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS ); OUT_RING( dev_priv->depth_pitch_offset_c ); OUT_RING( buffer[i] ); OUT_RING( (x[i] << 16) | y[i] ); OUT_RING( (1 << 16) | 1 ); ADVANCE_RING(); } } kfree( mask ); } else { for ( i = 0 ; i < count ; i++ ) { BEGIN_RING( 6 ); OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_SOLID_COLOR | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_P | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS ); OUT_RING( dev_priv->depth_pitch_offset_c ); OUT_RING( buffer[i] ); OUT_RING( (x[i] << 16) | y[i] ); OUT_RING( (1 << 16) | 1 ); ADVANCE_RING(); } } kfree( x ); kfree( y ); kfree( buffer ); return 0; } static int r128_cce_dispatch_read_span( drm_device_t *dev, drm_r128_depth_t *depth ) { drm_r128_private_t *dev_priv = dev->dev_private; int count, x, y; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); r128_update_ring_snapshot( dev_priv ); count = depth->n; if ( copy_from_user( &x, depth->x, sizeof(x) ) ) { return -EFAULT; } if ( copy_from_user( &y, depth->y, sizeof(y) ) ) { return -EFAULT; } BEGIN_RING( 7 ); OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_NONE | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_S | R128_DP_SRC_SOURCE_MEMORY | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS ); OUT_RING( dev_priv->depth_pitch_offset_c ); OUT_RING( dev_priv->span_pitch_offset_c ); OUT_RING( (x << 16) | y ); OUT_RING( (0 << 16) | 0 ); OUT_RING( (count << 16) | 1 ); ADVANCE_RING(); return 0; } static int r128_cce_dispatch_read_pixels( drm_device_t *dev, drm_r128_depth_t *depth ) { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; int i; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); r128_update_ring_snapshot( dev_priv ); count = depth->n; if ( count > dev_priv->depth_pitch ) { count = dev_priv->depth_pitch; } x = kmalloc( count * sizeof(*x), 0 ); if ( x == NULL ) { return -ENOMEM; } y = kmalloc( count * sizeof(*y), 0 ); if ( y == NULL ) { kfree( x ); return -ENOMEM; } if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) { kfree( x ); kfree( y ); return -EFAULT; } if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) { kfree( x ); kfree( y ); return -EFAULT; } for ( i = 0 ; i < count ; i++ ) { BEGIN_RING( 7 ); OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | R128_GMC_DST_PITCH_OFFSET_CNTL | R128_GMC_BRUSH_NONE | (dev_priv->depth_fmt << 8) | R128_GMC_SRC_DATATYPE_COLOR | R128_ROP3_S | R128_DP_SRC_SOURCE_MEMORY | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS ); OUT_RING( dev_priv->depth_pitch_offset_c ); OUT_RING( dev_priv->span_pitch_offset_c ); OUT_RING( (x[i] << 16) | y[i] ); OUT_RING( (i << 16) | 0 ); OUT_RING( (1 << 16) | 1 ); ADVANCE_RING(); } kfree( x ); kfree( y ); return 0; } /* ================================================================ * Polygon stipple */ static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) { drm_r128_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); r128_update_ring_snapshot( dev_priv ); BEGIN_RING( 33 ); OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); for ( i = 0 ; i < 32 ; i++ ) { OUT_RING( stipple[i] ); } ADVANCE_RING(); } /* ================================================================ * IOCTL functions */ int r128_cce_clear( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_clear_t clear; DRM_DEBUG( "%s\n", __FUNCTION__ ); LOCK_TEST_WITH_RETURN( dev ); if ( copy_from_user( &clear, (drm_r128_clear_t *) arg, sizeof(clear) ) ) return -EFAULT; RING_SPACE_TEST_WITH_RETURN( dev_priv ); if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; r128_cce_dispatch_clear( dev, &clear ); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; return 0; } int r128_cce_swap( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; DRM_DEBUG( "%s\n", __FUNCTION__ ); LOCK_TEST_WITH_RETURN( dev ); RING_SPACE_TEST_WITH_RETURN( dev_priv ); if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; if ( !dev_priv->page_flipping ) { r128_cce_dispatch_swap( dev ); dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS); } else { r128_cce_dispatch_flip( dev ); } return 0; } int r128_cce_vertex( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_r128_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_vertex_t vertex; LOCK_TEST_WITH_RETURN( dev ); if ( !dev_priv || dev_priv->is_pci ) { DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ ); return -EINVAL; } if ( copy_from_user( &vertex, (drm_r128_vertex_t *)arg, sizeof(vertex) ) ) return -EFAULT; DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n", __FUNCTION__, current->pid, vertex.idx, vertex.count, vertex.discard ); if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { DRM_ERROR( "buffer index %d (of %d max)\n", vertex.idx, dma->buf_count - 1 ); return -EINVAL; } if ( vertex.prim < 0 || vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { DRM_ERROR( "buffer prim %d\n", vertex.prim ); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN( dev_priv ); VB_AGE_TEST_WITH_RETURN( dev_priv ); buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; if ( buf->pid != current->pid ) { DRM_ERROR( "process %d using buffer owned by %d\n", current->pid, buf->pid ); return -EINVAL; } if ( buf->pending ) { DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); return -EINVAL; } buf->used = vertex.count; buf_priv->prim = vertex.prim; buf_priv->discard = vertex.discard; r128_cce_dispatch_vertex( dev, buf ); return 0; } int r128_cce_indices( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_r128_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_indices_t elts; int count; LOCK_TEST_WITH_RETURN( dev ); if ( !dev_priv || dev_priv->is_pci ) { DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ ); return -EINVAL; } if ( copy_from_user( &elts, (drm_r128_indices_t *)arg, sizeof(elts) ) ) return -EFAULT; DRM_DEBUG( "%s: pid=%d buf=%d s=%d e=%d d=%d\n", __FUNCTION__, current->pid, elts.idx, elts.start, elts.end, elts.discard ); if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { DRM_ERROR( "buffer index %d (of %d max)\n", elts.idx, dma->buf_count - 1 ); return -EINVAL; } if ( elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { DRM_ERROR( "buffer prim %d\n", elts.prim ); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN( dev_priv ); VB_AGE_TEST_WITH_RETURN( dev_priv ); buf = dma->buflist[elts.idx]; buf_priv = buf->dev_private; if ( buf->pid != current->pid ) { DRM_ERROR( "process %d using buffer owned by %d\n", current->pid, buf->pid ); return -EINVAL; } if ( buf->pending ) { DRM_ERROR( "sending pending buffer %d\n", elts.idx ); return -EINVAL; } count = (elts.end - elts.start) / sizeof(u16); elts.start -= R128_INDEX_PRIM_OFFSET; if ( elts.start & 0x7 ) { DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); return -EINVAL; } if ( elts.start < buf->used ) { DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); return -EINVAL; } buf->used = elts.end; buf_priv->prim = elts.prim; buf_priv->discard = elts.discard; r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); return 0; } int r128_cce_blit( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_blit_t blit; LOCK_TEST_WITH_RETURN( dev ); if ( copy_from_user( &blit, (drm_r128_blit_t *)arg, sizeof(blit) ) ) return -EFAULT; DRM_DEBUG( "%s: pid=%d index=%d\n", __FUNCTION__, current->pid, blit.idx ); if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { DRM_ERROR( "buffer index %d (of %d max)\n", blit.idx, dma->buf_count - 1 ); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN( dev_priv ); VB_AGE_TEST_WITH_RETURN( dev_priv ); return r128_cce_dispatch_blit( dev, &blit ); } int r128_cce_depth( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_depth_t depth; LOCK_TEST_WITH_RETURN( dev ); if ( copy_from_user( &depth, (drm_r128_depth_t *)arg, sizeof(depth) ) ) return -EFAULT; RING_SPACE_TEST_WITH_RETURN( dev_priv ); switch ( depth.func ) { case R128_WRITE_SPAN: return r128_cce_dispatch_write_span( dev, &depth ); case R128_WRITE_PIXELS: return r128_cce_dispatch_write_pixels( dev, &depth ); case R128_READ_SPAN: return r128_cce_dispatch_read_span( dev, &depth ); case R128_READ_PIXELS: return r128_cce_dispatch_read_pixels( dev, &depth ); } return -EINVAL; } int r128_cce_stipple( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_stipple_t stipple; u32 mask[32]; LOCK_TEST_WITH_RETURN( dev ); if ( copy_from_user( &stipple, (drm_r128_stipple_t *)arg, sizeof(stipple) ) ) return -EFAULT; if ( copy_from_user( &mask, stipple.mask, 32 * sizeof(u32) ) ) return -EFAULT; RING_SPACE_TEST_WITH_RETURN( dev_priv ); r128_cce_dispatch_stipple( dev, mask ); return 0; } int r128_cce_indirect( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; LOCK_TEST_WITH_RETURN( dev ); /* Indirect buffer firing is not supported at this time. */ return -EINVAL; }