summaryrefslogtreecommitdiff
path: root/linux-core/drm_drv.c
blob: 0d446a127fe7985c2aab095ad0a259ffdcc1279e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
/**
 * \file drm_drv.c
 * Generic driver template
 *
 * \author Rickard E. (Rik) Faith <faith@valinux.com>
 * \author Gareth Hughes <gareth@valinux.com>
 *
 * To use this template, you must at least define the following (samples
 * given for the MGA driver):
 *
 * \code
 * #define DRIVER_AUTHOR	"VA Linux Systems, Inc."
 *
 * #define DRIVER_NAME		"mga"
 * #define DRIVER_DESC		"Matrox G200/G400"
 * #define DRIVER_DATE		"20001127"
 *
 * #define drm_x		mga_##x
 * \endcode
 */

/*
 * Created: Thu Nov 23 03:10:50 2000 by gareth@valinux.com
 *
 * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#include "drmP.h"
#include "drm_core.h"

static void drm_cleanup(drm_device_t * dev);
int drm_fb_loaded = 0;

static int drm_version(struct inode *inode, struct file *filp,
		unsigned int cmd, unsigned long arg);

/** Ioctl table */
static drm_ioctl_desc_t drm_ioctls[] = {
	[DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = {drm_version, 0},
	[DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = {drm_getunique, 0},
	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = {drm_getmagic, 0},
	[DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = {drm_irq_by_busid, DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_GET_MAP)] = {drm_getmap, 0},
	[DRM_IOCTL_NR(DRM_IOCTL_GET_CLIENT)] = {drm_getclient, 0},
	[DRM_IOCTL_NR(DRM_IOCTL_GET_STATS)] = {drm_getstats, 0},
	[DRM_IOCTL_NR(DRM_IOCTL_SET_VERSION)] = {drm_setversion, DRM_MASTER|DRM_ROOT_ONLY},

	[DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = {drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = {drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = {drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = {drm_authmagic, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},

	[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = {drm_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_RM_MAP)] = {drm_rmmap_ioctl, DRM_AUTH},

	[DRM_IOCTL_NR(DRM_IOCTL_SET_SAREA_CTX)] = {drm_setsareactx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX)] = {drm_getsareactx, DRM_AUTH},

	[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = {drm_addctx, DRM_AUTH|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = {drm_rmctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = {drm_modctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = {drm_getctx, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = {drm_switchctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = {drm_newctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = {drm_resctx, DRM_AUTH},

	[DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = {drm_adddraw, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = {drm_rmdraw, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},

	[DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = {drm_lock, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = {drm_unlock, DRM_AUTH},

	[DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = {drm_noop, DRM_AUTH},

	[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = {drm_addbufs, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = {drm_markbufs, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = {drm_infobufs, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = {drm_mapbufs, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = {drm_freebufs, DRM_AUTH},
	/* The DRM_IOCTL_DMA ioctl should be defined by the driver. */
	[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = {NULL, DRM_AUTH},

	[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = {drm_control, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},

#if __OS_HAS_AGP
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = {drm_agp_acquire_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = {drm_agp_release_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = {drm_agp_enable_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info_ioctl, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = {drm_agp_alloc_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = {drm_agp_free_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = {drm_agp_bind_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = {drm_agp_unbind_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
#endif

	[DRM_IOCTL_NR(DRM_IOCTL_SG_ALLOC)] = {drm_sg_alloc_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
	[DRM_IOCTL_NR(DRM_IOCTL_SG_FREE)] = {drm_sg_free, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},

	[DRM_IOCTL_NR(DRM_IOCTL_WAIT_VBLANK)] = {drm_wait_vblank, 0},
	[DRM_IOCTL_NR(DRM_IOCTL_FENCE)] = {drm_fence_ioctl, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_IOCTL_BUFOBJ)] = {drm_bo_ioctl, DRM_AUTH},
	[DRM_IOCTL_NR(DRM_IOCTL_MM_INIT)] = {drm_mm_init_ioctl, 
					     DRM_AUTH },

	[DRM_IOCTL_NR(DRM_IOCTL_UPDATE_DRAW)] = {drm_update_drawable_info, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
};

#define DRM_CORE_IOCTL_COUNT	ARRAY_SIZE( drm_ioctls )


/**
 * Take down the DRM device.
 *
 * \param dev DRM device structure.
 *
 * Frees every resource in \p dev.
 *
 * \sa drm_device
 */
int drm_lastclose(drm_device_t * dev)
{
	drm_magic_entry_t *pt, *next;
	drm_map_list_t *r_list, *list_t;
	drm_vma_entry_t *vma, *vma_temp;
	int i;

	DRM_DEBUG("\n");

	/*
	 * We can't do much about this function failing.
	 */

	drm_bo_driver_finish(dev);

	if (dev->driver->lastclose)
		dev->driver->lastclose(dev);
	DRM_DEBUG("driver lastclose completed\n");

	if (dev->unique) {
		drm_free(dev->unique, strlen(dev->unique) + 1, DRM_MEM_DRIVER);
		dev->unique=NULL;
		dev->unique_len=0;
	}

	if (dev->irq_enabled)
		drm_irq_uninstall(dev);

	/* Free drawable information memory */
	mutex_lock(&dev->struct_mutex);

	drm_drawable_free_all(dev);
	del_timer(&dev->timer);

	if (dev->unique) {
		drm_free(dev->unique, strlen(dev->unique) + 1, DRM_MEM_DRIVER);
		dev->unique = NULL;
		dev->unique_len = 0;
	}

	if (dev->magicfree.next) {
		list_for_each_entry_safe(pt, next, &dev->magicfree, head) {
			list_del(&pt->head);
			drm_ht_remove_item(&dev->magiclist, &pt->hash_item);
			drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
		}
		drm_ht_remove(&dev->magiclist);
	}


	/* Clear AGP information */
	if (drm_core_has_AGP(dev) && dev->agp) {
		drm_agp_mem_t *entry, *tempe;

		/* Remove AGP resources, but leave dev->agp
		   intact until drv_cleanup is called. */
		list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
			if (entry->bound)
				drm_unbind_agp(entry->memory);
			drm_free_agp(entry->memory, entry->pages);
			drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
		}
		INIT_LIST_HEAD(&dev->agp->memory);

		if (dev->agp->acquired)
			drm_agp_release(dev);

		dev->agp->acquired = 0;
		dev->agp->enabled = 0;
	}
	if (drm_core_check_feature(dev, DRIVER_SG) && dev->sg) {
		drm_sg_cleanup(dev->sg);
		dev->sg = NULL;
	}

	/* Clear vma list (only built for debugging) */
	list_for_each_entry_safe(vma, vma_temp, &dev->vmalist, head) {
		list_del(&vma->head);
		drm_ctl_free(vma, sizeof(*vma), DRM_MEM_VMAS);
	}
	
	list_for_each_entry_safe(r_list, list_t, &dev->maplist, head) {
		drm_rmmap_locked(dev, r_list->map);
		r_list = NULL;
	}

	if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && dev->queuelist) {
		for (i = 0; i < dev->queue_count; i++) {

			if (dev->queuelist[i]) {
				drm_free(dev->queuelist[i],
					 sizeof(*dev->queuelist[0]),
					 DRM_MEM_QUEUES);
				dev->queuelist[i] = NULL;
			}
		}
		drm_free(dev->queuelist,
			 dev->queue_slots * sizeof(*dev->queuelist),
			 DRM_MEM_QUEUES);
		dev->queuelist = NULL;
	}
	dev->queue_count = 0;

	if (drm_core_check_feature(dev, DRIVER_HAVE_DMA))
		drm_dma_takedown(dev);

	if (dev->lock.hw_lock) {
		dev->sigdata.lock = dev->lock.hw_lock = NULL;	/* SHM removed */
		dev->lock.filp = NULL;
		wake_up_interruptible(&dev->lock.lock_queue);
	}
	dev->dev_mapping = NULL;
	mutex_unlock(&dev->struct_mutex);

	DRM_DEBUG("lastclose completed\n");
	return 0;
}

void drm_cleanup_pci(struct pci_dev *pdev)
{
	drm_device_t *dev = pci_get_drvdata(pdev);

	pci_set_drvdata(pdev, NULL);
	pci_release_regions(pdev);
	if (dev)
		drm_cleanup(dev);
}
EXPORT_SYMBOL(drm_cleanup_pci);

/**
 * Module initialization. Called via init_module at module load time, or via
 * linux/init/main.c (this is not currently supported).
 *
 * \return zero on success or a negative number on failure.
 *
 * Initializes an array of drm_device structures, and attempts to
 * initialize all available devices, using consecutive minors, registering the
 * stubs and initializing the AGP device.
 *
 * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and
 * after the initialization for driver customization.
 */
int drm_init(struct drm_driver *driver,
		       struct pci_device_id *pciidlist)
{
	struct pci_dev *pdev;
	struct pci_device_id *pid;
	int rc, i;

	DRM_DEBUG("\n");

	for (i = 0; (pciidlist[i].vendor != 0) && !drm_fb_loaded; i++) {
		pid = &pciidlist[i];

		pdev = NULL;
		/* pass back in pdev to account for multiple identical cards */
		while ((pdev =
			pci_get_subsys(pid->vendor, pid->device, pid->subvendor,
				       pid->subdevice, pdev))) {
			/* is there already a driver loaded, or (short circuit saves work) */
			/* does something like VesaFB have control of the memory region? */
			if (pci_dev_driver(pdev)
			    || pci_request_regions(pdev, "DRM scan")) {
				/* go into stealth mode */
				drm_fb_loaded = 1;
				pci_dev_put(pdev);
				break;
			}
			/* no fbdev or vesadev, put things back and wait for normal probe */
			pci_release_regions(pdev);
		}
	}

	if (!drm_fb_loaded)
		return pci_register_driver(&driver->pci_driver);
	else {
		for (i = 0; pciidlist[i].vendor != 0; i++) {
			pid = &pciidlist[i];

			pdev = NULL;
			/* pass back in pdev to account for multiple identical cards */
			while ((pdev =
				pci_get_subsys(pid->vendor, pid->device,
					       pid->subvendor, pid->subdevice,
					       pdev))) {
				/* stealth mode requires a manual probe */
				pci_dev_get(pdev);
				if ((rc = drm_get_dev(pdev, &pciidlist[i], driver))) {
					pci_dev_put(pdev);
					return rc;
				}
			}
		}
		DRM_INFO("Used old pci detect: framebuffer loaded\n");
	}
	return 0;
}
EXPORT_SYMBOL(drm_init);

/**
 * Called via cleanup_module() at module unload time.
 *
 * Cleans up all DRM device, calling drm_lastclose().
 *
 * \sa drm_init
 */
static void drm_cleanup(drm_device_t * dev)
{

	DRM_DEBUG("\n");
	if (!dev) {
		DRM_ERROR("cleanup called no dev\n");
		return;
	}

	drm_lastclose(dev);
	drm_fence_manager_takedown(dev);

	drm_ht_remove(&dev->map_hash);
	drm_mm_takedown(&dev->offset_manager);
	drm_ht_remove(&dev->object_hash);

	if (!drm_fb_loaded)
		pci_disable_device(dev->pdev);

	drm_ctxbitmap_cleanup(dev);

	if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) && dev->agp
	    && dev->agp->agp_mtrr >= 0) {
		int retval;
		retval = mtrr_del(dev->agp->agp_mtrr,
				  dev->agp->agp_info.aper_base,
				  dev->agp->agp_info.aper_size * 1024 * 1024);
		DRM_DEBUG("mtrr_del=%d\n", retval);
	}

	if (drm_core_has_AGP(dev) && dev->agp) {
		drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS);
		dev->agp = NULL;
	}
	if (dev->driver->unload)
		dev->driver->unload(dev);

	drm_put_head(&dev->primary);
	if (drm_put_dev(dev))
		DRM_ERROR("Cannot unload module\n");
}

void drm_exit(struct drm_driver *driver)
{
	int i;
	drm_device_t *dev = NULL;
	drm_head_t *head;

	DRM_DEBUG("\n");
	if (drm_fb_loaded) {
		for (i = 0; i < drm_cards_limit; i++) {
			head = drm_heads[i];
			if (!head)
				continue;
			if (!head->dev)
				continue;
			if (head->dev->driver != driver)
				continue;
			dev = head->dev;
			if (dev) {
				/* release the pci driver */
				if (dev->pdev)
					pci_dev_put(dev->pdev);
				drm_cleanup(dev);
			}
		}
	} else
		pci_unregister_driver(&driver->pci_driver);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15))
	free_nopage_retry();
#endif
	DRM_INFO("Module unloaded\n");
}
EXPORT_SYMBOL(drm_exit);

/** File operations structure */
static const struct file_operations drm_stub_fops = {
	.owner = THIS_MODULE,
	.open = drm_stub_open
};

static int __init drm_core_init(void)
{
	int ret;
	struct sysinfo si;
	unsigned long avail_memctl_mem;
	unsigned long max_memctl_mem;

	si_meminfo(&si);
	
	/*
	 * AGP only allows low / DMA32 memory ATM.
	 */

	avail_memctl_mem = si.totalram - si.totalhigh;

	/* 
	 * Avoid overflows 
	 */

	max_memctl_mem = 1UL << (32 - PAGE_SHIFT);
	max_memctl_mem = (max_memctl_mem / si.mem_unit) * PAGE_SIZE; 

	if (avail_memctl_mem >= max_memctl_mem)
		avail_memctl_mem = max_memctl_mem;

	drm_init_memctl(avail_memctl_mem/2, avail_memctl_mem*3/4, si.mem_unit);

	ret = -ENOMEM;
	drm_cards_limit =
	    (drm_cards_limit < DRM_MAX_MINOR + 1 ? drm_cards_limit : DRM_MAX_MINOR + 1);
	drm_heads = drm_calloc(drm_cards_limit, sizeof(*drm_heads), DRM_MEM_STUB);
	if (!drm_heads)
		goto err_p1;

	if (register_chrdev(DRM_MAJOR, "drm", &drm_stub_fops))
		goto err_p1;

	drm_class = drm_sysfs_create(THIS_MODULE, "drm");
	if (IS_ERR(drm_class)) {
		printk(KERN_ERR "DRM: Error creating drm class.\n");
		ret = PTR_ERR(drm_class);
		goto err_p2;
	}

	drm_proc_root = proc_mkdir("dri", NULL);
	if (!drm_proc_root) {
		DRM_ERROR("Cannot create /proc/dri\n");
		ret = -1;
		goto err_p3;
	}

	drm_mem_init();

	DRM_INFO("Initialized %s %d.%d.%d %s\n",
		 CORE_NAME,
		 CORE_MAJOR, CORE_MINOR, CORE_PATCHLEVEL, CORE_DATE);
	return 0;
err_p3:
	drm_sysfs_destroy(drm_class);
err_p2:
	unregister_chrdev(DRM_MAJOR, "drm");
	drm_free(drm_heads, sizeof(*drm_heads) * drm_cards_limit, DRM_MEM_STUB);
err_p1:
	return ret;
}

static void __exit drm_core_exit(void)
{
	remove_proc_entry("dri", NULL);
	drm_sysfs_destroy(drm_class);

	unregister_chrdev(DRM_MAJOR, "drm");

	drm_free(drm_heads, sizeof(*drm_heads) * drm_cards_limit, DRM_MEM_STUB);
}

module_init(drm_core_init);
module_exit(drm_core_exit);

/**
 * Get version information
 *
 * \param inode device inode.
 * \param filp file pointer.
 * \param cmd command.
 * \param arg user argument, pointing to a drm_version structure.
 * \return zero on success or negative number on failure.
 *
 * Fills in the version information in \p arg.
 */
static int drm_version(struct inode *inode, struct file *filp,
		unsigned int cmd, unsigned long arg)
{
	drm_file_t *priv = filp->private_data;
	drm_device_t *dev = priv->head->dev;
	drm_version_t __user *argp = (void __user *)arg;
	drm_version_t version;
	int len;

	if (copy_from_user(&version, argp, sizeof(version)))
		return -EFAULT;

	version.version_major = dev->driver->major;
	version.version_minor = dev->driver->minor;
	version.version_patchlevel = dev->driver->patchlevel;
	DRM_COPY(version.name, dev->driver->name);
	DRM_COPY(version.date, dev->driver->date);
	DRM_COPY(version.desc, dev->driver->desc);

	if (copy_to_user(argp, &version, sizeof(version)))
		return -EFAULT;
	return 0;
}

/**
 * Called whenever a process performs an ioctl on /dev/drm.
 *
 * \param inode device inode.
 * \param filp file pointer.
 * \param cmd command.
 * \param arg user argument.
 * \return zero on success or negative number on failure.
 *
 * Looks up the ioctl function in the ::ioctls table, checking for root
 * previleges if so required, and dispatches to the respective function.
 */
int drm_ioctl(struct inode *inode, struct file *filp,
	      unsigned int cmd, unsigned long arg)
{
	drm_file_t *priv = filp->private_data;
	drm_device_t *dev = priv->head->dev;
	drm_ioctl_desc_t *ioctl;
	drm_ioctl_t *func;
	unsigned int nr = DRM_IOCTL_NR(cmd);
	int retcode = -EINVAL;

	atomic_inc(&dev->ioctl_count);
	atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]);
	++priv->ioctl_count;

	DRM_DEBUG("pid=%d, cmd=0x%02x, nr=0x%02x, dev 0x%lx, auth=%d\n",
		  current->pid, cmd, nr, (long)old_encode_dev(priv->head->device),
		  priv->authenticated);

	if ((nr >= DRM_CORE_IOCTL_COUNT) &&
	    ((nr < DRM_COMMAND_BASE) || (nr >= DRM_COMMAND_END)))
		goto err_i1;
	if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
		&& (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
		ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
	else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE))
		ioctl = &drm_ioctls[nr];
	else
		goto err_i1;

	func = ioctl->func;
	/* is there a local override? */
	if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
		func = dev->driver->dma_ioctl;

	if (!func) {
		DRM_DEBUG("no function\n");
		retcode = -EINVAL;
	} else if (((ioctl->flags & DRM_ROOT_ONLY) && !capable(CAP_SYS_ADMIN)) ||
		   ((ioctl->flags & DRM_AUTH) && !priv->authenticated) ||
		   ((ioctl->flags & DRM_MASTER) && !priv->master)) {
		retcode = -EACCES;
	} else {
		retcode = func(inode, filp, cmd, arg);
	}
err_i1:
	atomic_dec(&dev->ioctl_count);
	if (retcode)
		DRM_DEBUG("ret = %x\n", retcode);
	return retcode;
}
EXPORT_SYMBOL(drm_ioctl);

drm_local_map_t *drm_getsarea(struct drm_device *dev)
{
	drm_map_list_t *entry;

	list_for_each_entry(entry, &dev->maplist, head) {
		if (entry->map && entry->map->type == _DRM_SHM &&
		    (entry->map->flags & _DRM_CONTAINS_LOCK)) {
			return entry->map;
		}
	}
	return NULL;
}
EXPORT_SYMBOL(drm_getsarea);
0007678, 0x00000006}, {0x0003802b, 0x00000002}, {0x04002676, 0x00000002}, {0x00007677, 0x00000002}, {0x00007678, 0x00000006}, {0x0000002e, 0x00000018}, {0x0000002e, 0x00000018}, {0000000000, 0x00000006}, {0x0000002f, 0x00000018}, {0x0000002f, 0x00000018}, {0000000000, 0x00000006}, {0x01605000, 0x00000002}, {0x00065000, 0x00000002}, {0x00098000, 0x00000002}, {0x00061000, 0x00000002}, {0x64c0603d, 0x00000004}, {0x00080000, 0x00000016}, {0000000000, 0000000000}, {0x0400251d, 0x00000002}, {0x00007580, 0x00000002}, {0x00067581, 0x00000002}, {0x04002580, 0x00000002}, {0x00067581, 0x00000002}, {0x00000046, 0x00000004}, {0x00005000, 0000000000}, {0x00061000, 0x00000002}, {0x0000750e, 0x00000002}, {0x00019000, 0x00000002}, {0x00011055, 0x00000014}, {0x00000055, 0x00000012}, {0x0400250f, 0x00000002}, {0x0000504a, 0x00000004}, {0x00007565, 0x00000002}, {0x00007566, 0x00000002}, {0x00000051, 0x00000004}, {0x01e655b4, 0x00000002}, {0x4401b0dc, 0x00000002}, {0x01c110dc, 0x00000002}, {0x2666705d, 0x00000018}, {0x040c2565, 0x00000002}, {0x0000005d, 0x00000018}, {0x04002564, 0x00000002}, {0x00007566, 0x00000002}, {0x00000054, 0x00000004}, {0x00401060, 0x00000008}, {0x00101000, 0x00000002}, {0x000d80ff, 0x00000002}, {0x00800063, 0x00000008}, {0x000f9000, 0x00000002}, {0x000e00ff, 0x00000002}, {0000000000, 0x00000006}, {0x00000080, 0x00000018}, {0x00000054, 0x00000004}, {0x00007576, 0x00000002}, {0x00065000, 0x00000002}, {0x00009000, 0x00000002}, {0x00041000, 0x00000002}, {0x0c00350e, 0x00000002}, {0x00049000, 0x00000002}, {0x00051000, 0x00000002}, {0x01e785f8, 0x00000002}, {0x00200000, 0x00000002}, {0x00600073, 0x0000000c}, {0x00007563, 0x00000002}, {0x006075f0, 0x00000021}, {0x20007068, 0x00000004}, {0x00005068, 0x00000004}, {0x00007576, 0x00000002}, {0x00007577, 0x00000002}, {0x0000750e, 0x00000002}, {0x0000750f, 0x00000002}, {0x00a05000, 0x00000002}, {0x00600076, 0x0000000c}, {0x006075f0, 0x00000021}, {0x000075f8, 0x00000002}, {0x00000076, 0x00000004}, {0x000a750e, 0x00000002}, {0x0020750f, 0x00000002}, {0x00600079, 0x00000004}, {0x00007570, 0x00000002}, {0x00007571, 0x00000002}, {0x00007572, 0x00000006}, {0x00005000, 0x00000002}, {0x00a05000, 0x00000002}, {0x00007568, 0x00000002}, {0x00061000, 0x00000002}, {0x00000084, 0x0000000c}, {0x00058000, 0x00000002}, {0x0c607562, 0x00000002}, {0x00000086, 0x00000004}, {0x00600085, 0x00000004}, {0x400070dd, 0000000000}, {0x000380dd, 0x00000002}, {0x00000093, 0x0000001c}, {0x00065095, 0x00000018}, {0x040025bb, 0x00000002}, {0x00061096, 0x00000018}, {0x040075bc, 0000000000}, {0x000075bb, 0x00000002}, {0x000075bc, 0000000000}, {0x00090000, 0x00000006}, {0x00090000, 0x00000002}, {0x000d8002, 0x00000006}, {0x00005000, 0x00000002}, {0x00007821, 0x00000002}, {0x00007800, 0000000000}, {0x00007821, 0x00000002}, {0x00007800, 0000000000}, {0x01665000, 0x00000002}, {0x000a0000, 0x00000002}, {0x000671cc, 0x00000002}, {0x0286f1cd, 0x00000002}, {0x000000a3, 0x00000010}, {0x21007000, 0000000000}, {0x000000aa, 0x0000001c}, {0x00065000, 0x00000002}, {0x000a0000, 0x00000002}, {0x00061000, 0x00000002}, {0x000b0000, 0x00000002}, {0x38067000, 0x00000002}, {0x000a00a6, 0x00000004}, {0x20007000, 0000000000}, {0x01200000, 0x00000002}, {0x20077000, 0x00000002}, {0x01200000, 0x00000002}, {0x20007000, 0000000000}, {0x00061000, 0x00000002}, {0x0120751b, 0x00000002}, {0x8040750a, 0x00000002}, {0x8040750b, 0x00000002}, {0x00110000, 0x00000002}, {0x000380dd, 0x00000002}, {0x000000bd, 0x0000001c}, {0x00061096, 0x00000018}, {0x844075bd, 0x00000002}, {0x00061095, 0x00000018}, {0x840075bb, 0x00000002}, {0x00061096, 0x00000018}, {0x844075bc, 0x00000002}, {0x000000c0, 0x00000004}, {0x804075bd, 0x00000002}, {0x800075bb, 0x00000002}, {0x804075bc, 0x00000002}, {0x00108000, 0x00000002}, {0x01400000, 0x00000002}, {0x006000c4, 0x0000000c}, {0x20c07000, 0x00000020}, {0x000000c6, 0x00000012}, {0x00800000, 0x00000006}, {0x0080751d, 0x00000006}, {0x000025bb, 0x00000002}, {0x000040c0, 0x00000004}, {0x0000775c, 0x00000002}, {0x00a05000, 0x00000002}, {0x00661000, 0x00000002}, {0x0460275d, 0x00000020}, {0x00004000, 0000000000}, {0x00007999, 0x00000002}, {0x00a05000, 0x00000002}, {0x00661000, 0x00000002}, {0x0460299b, 0x00000020}, {0x00004000, 0000000000}, {0x01e00830, 0x00000002}, {0x21007000, 0000000000}, {0x00005000, 0x00000002}, {0x00038042, 0x00000002}, {0x040025e0, 0x00000002}, {0x000075e1, 0000000000}, {0x00000001, 0000000000}, {0x000380d9, 0x00000002}, {0x04007394, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, }; static const u32 radeon_cp_microcode[][2] = { {0x21007000, 0000000000}, {0x20007000, 0000000000}, {0x000000b4, 0x00000004}, {0x000000b8, 0x00000004}, {0x6f5b4d4c, 0000000000}, {0x4c4c427f, 0000000000}, {0x5b568a92, 0000000000}, {0x4ca09c6d, 0000000000}, {0xad4c4c4c, 0000000000}, {0x4ce1af3d, 0000000000}, {0xd8afafaf, 0000000000}, {0xd64c4cdc, 0000000000}, {0x4cd10d10, 0000000000}, {0x000f0000, 0x00000016}, {0x362f242d, 0000000000}, {0x00000012, 0x00000004}, {0x000f0000, 0x00000016}, {0x362f282d, 0000000000}, {0x000380e7, 0x00000002}, {0x04002c97, 0x00000002}, {0x000f0001, 0x00000016}, {0x333a3730, 0000000000}, {0x000077ef, 0x00000002}, {0x00061000, 0x00000002}, {0x00000021, 0x0000001a}, {0x00004000, 0x0000001e}, {0x00061000, 0x00000002}, {0x00000021, 0x0000001a}, {0x00004000, 0x0000001e}, {0x00061000, 0x00000002}, {0x00000021, 0x0000001a}, {0x00004000, 0x0000001e}, {0x00000017, 0x00000004}, {0x0003802b, 0x00000002}, {0x040067e0, 0x00000002}, {0x00000017, 0x00000004}, {0x000077e0, 0x00000002}, {0x00065000, 0x00000002}, {0x000037e1, 0x00000002}, {0x040067e1, 0x00000006}, {0x000077e0, 0x00000002}, {0x000077e1, 0x00000002}, {0x000077e1, 0x00000006}, {0xffffffff, 0000000000}, {0x10000000, 0000000000}, {0x0003802b, 0x00000002}, {0x040067e0, 0x00000006}, {0x00007675, 0x00000002}, {0x00007676, 0x00000002}, {0x00007677, 0x00000002}, {0x00007678, 0x00000006}, {0x0003802c, 0x00000002}, {0x04002676, 0x00000002}, {0x00007677, 0x00000002}, {0x00007678, 0x00000006}, {0x0000002f, 0x00000018}, {0x0000002f, 0x00000018}, {0000000000, 0x00000006}, {0x00000030, 0x00000018}, {0x00000030, 0x00000018}, {0000000000, 0x00000006}, {0x01605000, 0x00000002}, {0x00065000, 0x00000002}, {0x00098000, 0x00000002}, {0x00061000, 0x00000002}, {0x64c0603e, 0x00000004}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x00080000, 0x00000016}, {0000000000, 0000000000}, {0x0400251d, 0x00000002}, {0x00007580, 0x00000002}, {0x00067581, 0x00000002}, {0x04002580, 0x00000002}, {0x00067581, 0x00000002}, {0x00000049, 0x00000004}, {0x00005000, 0000000000}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x00061000, 0x00000002}, {0x0000750e, 0x00000002}, {0x00019000, 0x00000002}, {0x00011055, 0x00000014}, {0x00000055, 0x00000012}, {0x0400250f, 0x00000002}, {0x0000504f, 0x00000004}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x00007565, 0x00000002}, {0x00007566, 0x00000002}, {0x00000058, 0x00000004}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x01e655b4, 0x00000002}, {0x4401b0e4, 0x00000002}, {0x01c110e4, 0x00000002}, {0x26667066, 0x00000018}, {0x040c2565, 0x00000002}, {0x00000066, 0x00000018}, {0x04002564, 0x00000002}, {0x00007566, 0x00000002}, {0x0000005d, 0x00000004}, {0x00401069, 0x00000008}, {0x00101000, 0x00000002}, {0x000d80ff, 0x00000002}, {0x0080006c, 0x00000008}, {0x000f9000, 0x00000002}, {0x000e00ff, 0x00000002}, {0000000000, 0x00000006}, {0x0000008f, 0x00000018}, {0x0000005b, 0x00000004}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x00007576, 0x00000002}, {0x00065000, 0x00000002}, {0x00009000, 0x00000002}, {0x00041000, 0x00000002}, {0x0c00350e, 0x00000002}, {0x00049000, 0x00000002}, {0x00051000, 0x00000002}, {0x01e785f8, 0x00000002}, {0x00200000, 0x00000002}, {0x0060007e, 0x0000000c}, {0x00007563, 0x00000002}, {0x006075f0, 0x00000021}, {0x20007073, 0x00000004}, {0x00005073, 0x00000004}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x00007576, 0x00000002}, {0x00007577, 0x00000002}, {0x0000750e, 0x00000002}, {0x0000750f, 0x00000002}, {0x00a05000, 0x00000002}, {0x00600083, 0x0000000c}, {0x006075f0, 0x00000021}, {0x000075f8, 0x00000002}, {0x00000083, 0x00000004}, {0x000a750e, 0x00000002}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x0020750f, 0x00000002}, {0x00600086, 0x00000004}, {0x00007570, 0x00000002}, {0x00007571, 0x00000002}, {0x00007572, 0x00000006}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x00005000, 0x00000002}, {0x00a05000, 0x00000002}, {0x00007568, 0x00000002}, {0x00061000, 0x00000002}, {0x00000095, 0x0000000c}, {0x00058000, 0x00000002}, {0x0c607562, 0x00000002}, {0x00000097, 0x00000004}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x00600096, 0x00000004}, {0x400070e5, 0000000000}, {0x000380e6, 0x00000002}, {0x040025c5, 0x00000002}, {0x000380e5, 0x00000002}, {0x000000a8, 0x0000001c}, {0x000650aa, 0x00000018}, {0x040025bb, 0x00000002}, {0x000610ab, 0x00000018}, {0x040075bc, 0000000000}, {0x000075bb, 0x00000002}, {0x000075bc, 0000000000}, {0x00090000, 0x00000006}, {0x00090000, 0x00000002}, {0x000d8002, 0x00000006}, {0x00007832, 0x00000002}, {0x00005000, 0x00000002}, {0x000380e7, 0x00000002}, {0x04002c97, 0x00000002}, {0x00007820, 0x00000002}, {0x00007821, 0x00000002}, {0x00007800, 0000000000}, {0x01200000, 0x00000002}, {0x20077000, 0x00000002}, {0x01200000, 0x00000002}, {0x20007000, 0x00000002}, {0x00061000, 0x00000002}, {0x0120751b, 0x00000002}, {0x8040750a, 0x00000002}, {0x8040750b, 0x00000002}, {0x00110000, 0x00000002}, {0x000380e5, 0x00000002}, {0x000000c6, 0x0000001c}, {0x000610ab, 0x00000018}, {0x844075bd, 0x00000002}, {0x000610aa, 0x00000018}, {0x840075bb, 0x00000002}, {0x000610ab, 0x00000018}, {0x844075bc, 0x00000002}, {0x000000c9, 0x00000004}, {0x804075bd, 0x00000002}, {0x800075bb, 0x00000002}, {0x804075bc, 0x00000002}, {0x00108000, 0x00000002}, {0x01400000, 0x00000002}, {0x006000cd, 0x0000000c}, {0x20c07000, 0x00000020}, {0x000000cf, 0x00000012}, {0x00800000, 0x00000006}, {0x0080751d, 0x00000006}, {0000000000, 0000000000}, {0x0000775c, 0x00000002}, {0x00a05000, 0x00000002}, {0x00661000, 0x00000002}, {0x0460275d, 0x00000020}, {0x00004000, 0000000000}, {0x01e00830, 0x00000002}, {0x21007000, 0000000000}, {0x6464614d, 0000000000}, {0x69687420, 0000000000}, {0x00000073, 0000000000}, {0000000000, 0000000000}, {0x00005000, 0x00000002}, {0x000380d0, 0x00000002}, {0x040025e0, 0x00000002}, {0x000075e1, 0000000000}, {0x00000001, 0000000000}, {0x000380e0, 0x00000002}, {0x04002394, 0x00000002}, {0x00005000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0x00000008, 0000000000}, {0x00000004, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, {0000000000, 0000000000}, }; static const u32 R300_cp_microcode[][2] = { { 0x4200e000, 0000000000 }, { 0x4000e000, 0000000000 }, { 0x000000af, 0x00000008 }, { 0x000000b3, 0x00000008 }, { 0x6c5a504f, 0000000000 }, { 0x4f4f497a, 0000000000 }, { 0x5a578288, 0000000000 }, { 0x4f91906a, 0000000000 }, { 0x4f4f4f4f, 0000000000 }, { 0x4fe24f44, 0000000000 }, { 0x4f9c9c9c, 0000000000 }, { 0xdc4f4fde, 0000000000 }, { 0xa1cd4f4f, 0000000000 }, { 0xd29d9d9d, 0000000000 }, { 0x4f0f9fd7, 0000000000 }, { 0x000ca000, 0x00000004 }, { 0x000d0012, 0x00000038 }, { 0x0000e8b4, 0x00000004 }, { 0x000d0014, 0x00000038 }, { 0x0000e8b6, 0x00000004 }, { 0x000d0016, 0x00000038 }, { 0x0000e854, 0x00000004 }, { 0x000d0018, 0x00000038 }, { 0x0000e855, 0x00000004 }, { 0x000d001a, 0x00000038 }, { 0x0000e856, 0x00000004 }, { 0x000d001c, 0x00000038 }, { 0x0000e857, 0x00000004 }, { 0x000d001e, 0x00000038 }, { 0x0000e824, 0x00000004 }, { 0x000d0020, 0x00000038 }, { 0x0000e825, 0x00000004 }, { 0x000d0022, 0x00000038 }, { 0x0000e830, 0x00000004 }, { 0x000d0024, 0x00000038 }, { 0x0000f0c0, 0x00000004 }, { 0x000d0026, 0x00000038 }, { 0x0000f0c1, 0x00000004 }, { 0x000d0028, 0x00000038 }, { 0x0000f041, 0x00000004 }, { 0x000d002a, 0x00000038 }, { 0x0000f184, 0x00000004 }, { 0x000d002c, 0x00000038 }, { 0x0000f185, 0x00000004 }, { 0x000d002e, 0x00000038 }, { 0x0000f186, 0x00000004 }, { 0x000d0030, 0x00000038 }, { 0x0000f187, 0x00000004 }, { 0x000d0032, 0x00000038 }, { 0x0000f180, 0x00000004 }, { 0x000d0034, 0x00000038 }, { 0x0000f393, 0x00000004 }, { 0x000d0036, 0x00000038 }, { 0x0000f38a, 0x00000004 }, { 0x000d0038, 0x00000038 }, { 0x0000f38e, 0x00000004 }, { 0x0000e821, 0x00000004 }, { 0x0140a000, 0x00000004 }, { 0x00000043, 0x00000018 }, { 0x00cce800, 0x00000004 }, { 0x001b0001, 0x00000004 }, { 0x08004800, 0x00000004 }, { 0x001b0001, 0x00000004 }, { 0x08004800, 0x00000004 }, { 0x001b0001, 0x00000004 }, { 0x08004800, 0x00000004 }, { 0x0000003a, 0x00000008 }, { 0x0000a000, 0000000000 }, { 0x02c0a000, 0x00000004 }, { 0x000ca000, 0x00000004 }, { 0x00130000, 0x00000004 }, { 0x000c2000, 0x00000004 }, { 0xc980c045, 0x00000008 }, { 0x2000451d, 0x00000004 }, { 0x0000e580, 0x00000004 }, { 0x000ce581, 0x00000004 }, { 0x08004580, 0x00000004 }, { 0x000ce581, 0x00000004 }, { 0x0000004c, 0x00000008 }, { 0x0000a000, 0000000000 }, { 0x000c2000, 0x00000004 }, { 0x0000e50e, 0x00000004 }, { 0x00032000, 0x00000004 }, { 0x00022056, 0x00000028 }, { 0x00000056, 0x00000024 }, { 0x0800450f, 0x00000004 }, { 0x0000a050, 0x00000008 }, { 0x0000e565, 0x00000004 }, { 0x0000e566, 0x00000004 }, { 0x00000057, 0x00000008 }, { 0x03cca5b4, 0x00000004 }, { 0x05432000, 0x00000004 }, { 0x00022000, 0x00000004 }, { 0x4ccce063, 0x00000030 }, { 0x08274565, 0x00000004 }, { 0x00000063, 0x00000030 }, { 0x08004564, 0x00000004 }, { 0x0000e566, 0x00000004 }, { 0x0000005a, 0x00000008 }, { 0x00802066, 0x00000010 }, { 0x00202000, 0x00000004 }, { 0x001b00ff, 0x00000004 }, { 0x01000069, 0x00000010 }, { 0x001f2000, 0x00000004 }, { 0x001c00ff, 0x00000004 }, { 0000000000, 0x0000000c }, { 0x00000085, 0x00000030 }, { 0x0000005a, 0x00000008 }, { 0x0000e576, 0x00000004 }, { 0x000ca000, 0x00000004 }, { 0x00012000, 0x00000004 }, { 0x00082000, 0x00000004 }, { 0x1800650e, 0x00000004 }, { 0x00092000, 0x00000004 }, { 0x000a2000, 0x00000004 }, { 0x000f0000, 0x00000004 }, { 0x00400000, 0x00000004 }, { 0x00000079, 0x00000018 }, { 0x0000e563, 0x00000004 }, { 0x00c0e5f9, 0x000000c2 }, { 0x0000006e, 0x00000008 }, { 0x0000a06e, 0x00000008 }, { 0x0000e576, 0x00000004 }, { 0x0000e577, 0x00000004 }, { 0x0000e50e, 0x00000004 }, { 0x0000e50f, 0x00000004 }, { 0x0140a000, 0x00000004 }, { 0x0000007c, 0x00000018 }, { 0x00c0e5f9, 0x000000c2 }, { 0x0000007c, 0x00000008 }, { 0x0014e50e, 0x00000004 }, { 0x0040e50f, 0x00000004 }, { 0x00c0007f, 0x00000008 }, { 0x0000e570, 0x00000004 }, { 0x0000e571, 0x00000004 }, { 0x0000e572, 0x0000000c }, { 0x0000a000, 0x00000004 }, { 0x0140a000, 0x00000004 }, { 0x0000e568, 0x00000004 }, { 0x000c2000, 0x00000004 }, { 0x00000089, 0x00000018 }, { 0x000b0000, 0x00000004 }, { 0x18c0e562, 0x00000004 }, { 0x0000008b, 0x00000008 }, { 0x00c0008a, 0x00000008 }, { 0x000700e4, 0x00000004 }, { 0x00000097, 0x00000038 }, { 0x000ca099, 0x00000030 }, { 0x080045bb, 0x00000004 }, { 0x000c209a, 0x00000030 }, { 0x0800e5bc, 0000000000 }, { 0x0000e5bb, 0x00000004 }, { 0x0000e5bc, 0000000000 }, { 0x00120000, 0x0000000c }, { 0x00120000, 0x00000004 }, { 0x001b0002, 0x0000000c }, { 0x0000a000, 0x00000004 }, { 0x0000e821, 0x00000004 }, { 0x0000e800, 0000000000 }, { 0x0000e821, 0x00000004 }, { 0x0000e82e, 0000000000 }, { 0x02cca000, 0x00000004 }, { 0x00140000, 0x00000004 }, { 0x000ce1cc, 0x00000004 }, { 0x050de1cd, 0x00000004 }, { 0x000000a7, 0x00000020 }, { 0x4200e000, 0000000000 }, { 0x000000ae, 0x00000038 }, { 0x000ca000, 0x00000004 }, { 0x00140000, 0x00000004 }, { 0x000c2000, 0x00000004 }, { 0x00160000, 0x00000004 }, { 0x700ce000, 0x00000004 }, { 0x001400aa, 0x00000008 }, { 0x4000e000, 0000000000 }, { 0x02400000, 0x00000004 }, { 0x400ee000, 0x00000004 }, { 0x02400000, 0x00000004 }, { 0x4000e000, 0000000000 }, { 0x000c2000, 0x00000004 }, { 0x0240e51b, 0x00000004 }, { 0x0080e50a, 0x00000005 }, { 0x0080e50b, 0x00000005 }, { 0x00220000, 0x00000004 }, { 0x000700e4, 0x00000004 }, { 0x000000c1, 0x00000038 }, { 0x000c209a, 0x00000030 }, { 0x0880e5bd, 0x00000005 }, { 0x000c2099, 0x00000030 }, { 0x0800e5bb, 0x00000005 }, { 0x000c209a, 0x00000030 }, { 0x0880e5bc, 0x00000005 }, { 0x000000c4, 0x00000008 }, { 0x0080e5bd, 0x00000005 }, { 0x0000e5bb, 0x00000005 }, { 0x0080e5bc, 0x00000005 }, { 0x00210000, 0x00000004 }, { 0x02800000, 0x00000004 }, { 0x00c000c8, 0x00000018 }, { 0x4180e000, 0x00000040 }, { 0x000000ca, 0x00000024 }, { 0x01000000, 0x0000000c }, { 0x0100e51d, 0x0000000c }, { 0x000045bb, 0x00000004 }, { 0x000080c4, 0x00000008 }, { 0x0000f3ce, 0x00000004 }, { 0x0140a000, 0x00000004 }, { 0x00cc2000, 0x00000004 }, { 0x08c053cf, 0x00000040 }, { 0x00008000, 0000000000 }, { 0x0000f3d2, 0x00000004 }, { 0x0140a000, 0x00000004 }, { 0x00cc2000, 0x00000004 }, { 0x08c053d3, 0x00000040 }, { 0x00008000, 0000000000 }, { 0x0000f39d, 0x00000004 }, { 0x0140a000, 0x00000004 }, { 0x00cc2000, 0x00000004 }, { 0x08c0539e, 0x00000040 }, { 0x00008000, 0000000000 }, { 0x03c00830, 0x00000004 }, { 0x4200e000, 0000000000 }, { 0x0000a000, 0x00000004 }, { 0x200045e0, 0x00000004 }, { 0x0000e5e1, 0000000000 }, { 0x00000001, 0000000000 }, { 0x000700e1, 0x00000004 }, { 0x0800e394, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, { 0000000000, 0000000000 }, }; static int RADEON_READ_PLL(drm_device_t * dev, int addr) { drm_radeon_private_t *dev_priv = dev->dev_private; RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); return RADEON_READ(RADEON_CLOCK_CNTL_DATA); } static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) { RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); return RADEON_READ(RADEON_PCIE_DATA); } #if RADEON_FIFO_DEBUG static void radeon_status(drm_radeon_private_t * dev_priv) { printk("%s:\n", __FUNCTION__); printk("RBBM_STATUS = 0x%08x\n", (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); printk("CP_RB_RTPR = 0x%08x\n", (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); printk("CP_RB_WTPR = 0x%08x\n", (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); printk("AIC_CNTL = 0x%08x\n", (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); printk("AIC_STAT = 0x%08x\n", (unsigned int)RADEON_READ(RADEON_AIC_STAT)); printk("AIC_PT_BASE = 0x%08x\n", (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); printk("TLB_ADDR = 0x%08x\n", (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); printk("TLB_DATA = 0x%08x\n", (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); } #endif /* ================================================================ * Engine, FIFO control */ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) { u32 tmp; int i; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); tmp |= RADEON_RB3D_DC_FLUSH_ALL; RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); for (i = 0; i < dev_priv->usec_timeout; i++) { if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) { return 0; } DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG DRM_ERROR("failed!\n"); radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) { int i; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; for (i = 0; i < dev_priv->usec_timeout; i++) { int slots = (RADEON_READ(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK); if (slots >= entries) return 0; DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG DRM_ERROR("failed!\n"); radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) { int i, ret; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; ret = radeon_do_wait_for_fifo(dev_priv, 64); if (ret) return ret; for (i = 0; i < dev_priv->usec_timeout; i++) { if (!(RADEON_READ(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { radeon_do_pixcache_flush(dev_priv); return 0; } DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG DRM_ERROR("failed!\n"); radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } /* ================================================================ * CP control, initialization */ /* Load the microcode for the CP */ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) { int i; DRM_DEBUG("\n"); radeon_do_wait_for_idle(dev_priv); RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); if (dev_priv->microcode_version == UCODE_R200) { DRM_INFO("Loading R200 Microcode\n"); for (i = 0; i < 256; i++) { RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]); RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]); } } else if (dev_priv->microcode_version == UCODE_R300) { DRM_INFO("Loading R300 Microcode\n"); for (i = 0; i < 256; i++) { RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); } } else { for (i = 0; i < 256; i++) { RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, radeon_cp_microcode[i][1]); RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, radeon_cp_microcode[i][0]); } } } /* Flush any pending commands to the CP. This should only be used just * prior to a wait for idle, as it informs the engine that the command * stream is ending. */ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) { DRM_DEBUG("\n"); #if 0 u32 tmp; tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); #endif } /* Wait for the CP to go idle. */ int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) { RING_LOCALS; DRM_DEBUG("\n"); BEGIN_RING(6); RADEON_PURGE_CACHE(); RADEON_PURGE_ZCACHE(); RADEON_WAIT_UNTIL_IDLE(); ADVANCE_RING(); COMMIT_RING(); return radeon_do_wait_for_idle(dev_priv); } /* Start the Command Processor. */ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) { RING_LOCALS; DRM_DEBUG("\n"); radeon_do_wait_for_idle(dev_priv); RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); dev_priv->cp_running = 1; BEGIN_RING(6); RADEON_PURGE_CACHE(); RADEON_PURGE_ZCACHE(); RADEON_WAIT_UNTIL_IDLE(); ADVANCE_RING(); COMMIT_RING(); } /* Reset the Command Processor. This will not flush any pending * commands, so you must wait for the CP command stream to complete * before calling this routine. */ static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) { u32 cur_read_ptr; DRM_DEBUG("\n"); cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); SET_RING_HEAD(dev_priv, cur_read_ptr); dev_priv->ring.tail = cur_read_ptr; } /* Stop the Command Processor. This will not flush any pending * commands, so you must flush the command stream and wait for the CP * to go idle before calling this routine. */ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) { DRM_DEBUG("\n"); RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); dev_priv->cp_running = 0; } /* Reset the engine. This will stop the CP if it is running. */ static int radeon_do_engine_reset(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; DRM_DEBUG("\n"); radeon_do_pixcache_flush(dev_priv); clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | RADEON_FORCEON_MCLKA | RADEON_FORCEON_MCLKB | RADEON_FORCEON_YCLKA | RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC | RADEON_FORCEON_AIC)); rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_PP | RADEON_SOFT_RESET_E2 | RADEON_SOFT_RESET_RB)); RADEON_READ(RADEON_RBBM_SOFT_RESET); RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & ~(RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_PP | RADEON_SOFT_RESET_E2 | RADEON_SOFT_RESET_RB))); RADEON_READ(RADEON_RBBM_SOFT_RESET); RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); /* Reset the CP ring */ radeon_do_cp_reset(dev_priv); /* The CP is no longer running after an engine reset */ dev_priv->cp_running = 0; /* Reset any pending vertex, indirect buffers */ radeon_freelist_reset(dev); return 0; } static void radeon_cp_init_ring_buffer(drm_device_t * dev, drm_radeon_private_t * dev_priv) { u32 ring_start, cur_read_ptr; u32 tmp; /* Initialize the memory controller. With new memory map, the fb location * is not changed, it should have been properly initialized already. Part * of the problem is that the code below is bogus, assuming the GART is * always appended to the fb which is not necessarily the case */ if (!dev_priv->new_memmap) RADEON_WRITE(RADEON_MC_FB_LOCATION, ((dev_priv->gart_vm_start - 1) & 0xffff0000) | (dev_priv->fb_location >> 16)); #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) { RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); RADEON_WRITE(RADEON_MC_AGP_LOCATION, (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 0xffff0000) | (dev_priv->gart_vm_start >> 16))); ring_start = (dev_priv->cp_ring->offset - dev->agp->base + dev_priv->gart_vm_start); } else #endif ring_start = (dev_priv->cp_ring->offset - (unsigned long)dev->sg->virtual + dev_priv->gart_vm_start); RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); /* Set the write pointer delay */ RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); /* Initialize the ring buffer's read and write pointers */ cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); SET_RING_HEAD(dev_priv, cur_read_ptr); dev_priv->ring.tail = cur_read_ptr; #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) { RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, dev_priv->ring_rptr->offset - dev->agp->base + dev_priv->gart_vm_start); } else #endif { drm_sg_mem_t *entry = dev->sg; unsigned long tmp_ofs, page_ofs; tmp_ofs = dev_priv->ring_rptr->offset - (unsigned long)dev->sg->virtual; page_ofs = tmp_ofs >> PAGE_SHIFT; RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", (unsigned long)entry->busaddr[page_ofs], entry->handle + tmp_ofs); } /* Set ring buffer size */ #ifdef __BIG_ENDIAN RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT); #else RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw); #endif /* Start with assuming that writeback doesn't work */ dev_priv->writeback_works = 0; /* Initialize the scratch register pointer. This will cause * the scratch register values to be written out to memory * whenever they are updated. * * We simply put this behind the ring read pointer, this works * with PCI GART as well as (whatever kind of) AGP GART */ RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) + RADEON_SCRATCH_REG_OFFSET); dev_priv->scratch = ((__volatile__ u32 *) dev_priv->ring_rptr->handle + (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); /* Turn on bus mastering */ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; RADEON_WRITE(RADEON_BUS_CNTL, tmp); dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; RADEON_WRITE(RADEON_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); radeon_do_wait_for_idle(dev_priv); /* Sync everything up */ RADEON_WRITE(RADEON_ISYNC_CNTL, (RADEON_ISYNC_ANY2D_IDLE3D | RADEON_ISYNC_ANY3D_IDLE2D | RADEON_ISYNC_WAIT_IDLEGUI | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); } static void radeon_test_writeback(drm_radeon_private_t * dev_priv) { u32 tmp; /* Writeback doesn't seem to work everywhere, test it here and possibly * enable it if it appears to work */ DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == 0xdeadbeef) break; DRM_UDELAY(1); } if (tmp < dev_priv->usec_timeout) { dev_priv->writeback_works = 1; DRM_INFO("writeback test succeeded in %d usecs\n", tmp); } else { dev_priv->writeback_works = 0; DRM_INFO("writeback test failed\n"); } if (radeon_no_wb == 1) { dev_priv->writeback_works = 0; DRM_INFO("writeback forced off\n"); } if (!dev_priv->writeback_works) { /* Disable writeback to avoid unnecessary bus master transfers */ RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE); RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); } } /* Enable or disable PCI-E GART on the chip */ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) { u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); if (on) { DRM_DEBUG("programming pcie %08X %08lX %08X\n", dev_priv->gart_vm_start, (long)dev_priv->gart_info.bus_addr, dev_priv->gart_size); RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start); RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->gart_info.bus_addr); RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start); RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start + dev_priv->gart_size - 1); RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN); } else { RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); } } /* Enable or disable PCI GART on the chip */ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) { u32 tmp; if (dev_priv->flags & RADEON_IS_PCIE) { radeon_set_pciegart(dev_priv, on); return; } tmp = RADEON_READ(RADEON_AIC_CNTL); if (on) { RADEON_WRITE(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN); /* set PCI GART page-table base address */ RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); /* set address range for PCI address translate */ RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start + dev_priv->gart_size - 1); /* Turn off AGP aperture -- is this required for PCI GART? */ RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ } else { RADEON_WRITE(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); } } static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) { drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); /* if we require new memory map but we don't have it fail */ if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { DRM_DEBUG("Forcing AGP card to PCI mode\n"); dev_priv->flags &= ~RADEON_IS_AGP; } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) && !init->is_pci) { DRM_DEBUG("Restoring AGP flag\n"); dev_priv->flags |= RADEON_IS_AGP; } if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { DRM_ERROR("PCI GART memory not allocated!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->usec_timeout = init->usec_timeout; if (dev_priv->usec_timeout < 1 || dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { DRM_DEBUG("TIMEOUT problem!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } switch(init->func) { case RADEON_INIT_R200_CP: dev_priv->microcode_version = UCODE_R200; break; case RADEON_INIT_R300_CP: dev_priv->microcode_version = UCODE_R300; break; default: dev_priv->microcode_version = UCODE_R100; } dev_priv->do_boxes = 0; dev_priv->cp_mode = init->cp_mode; /* We don't support anything other than bus-mastering ring mode, * but the ring can be in either AGP or PCI space for the ring * read pointer. */ if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } switch (init->fb_bpp) { case 16: dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; break; case 32: default: dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; break; } dev_priv->front_offset = init->front_offset; dev_priv->front_pitch = init->front_pitch; dev_priv->back_offset = init->back_offset; dev_priv->back_pitch = init->back_pitch; switch (init->depth_bpp) { case 16: dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; break; case 32: default: dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; break; } dev_priv->depth_offset = init->depth_offset; dev_priv->depth_pitch = init->depth_pitch; /* Hardware state for depth clears. Remove this if/when we no * longer clear the depth buffer with a 3D rectangle. Hard-code * all values to prevent unwanted 3D state from slipping through * and screwing with the clear operation. */ dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | (dev_priv->color_fmt << 10) | (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0)); dev_priv->depth_clear.rb3d_zstencilcntl = (dev_priv->depth_fmt | RADEON_Z_TEST_ALWAYS | RADEON_STENCIL_TEST_ALWAYS | RADEON_STENCIL_S_FAIL_REPLACE | RADEON_STENCIL_ZPASS_REPLACE | RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | RADEON_BFACE_SOLID | RADEON_FFACE_SOLID | RADEON_FLAT_SHADE_VTX_LAST | RADEON_DIFFUSE_SHADE_FLAT | RADEON_ALPHA_SHADE_FLAT | RADEON_SPECULAR_SHADE_FLAT | RADEON_FOG_SHADE_FLAT | RADEON_VTX_PIX_CENTER_OGL | RADEON_ROUND_MODE_TRUNC | RADEON_ROUND_PREC_8TH_PIX); DRM_GETSAREA(); dev_priv->ring_offset = init->ring_offset; dev_priv->ring_rptr_offset = init->ring_rptr_offset; dev_priv->buffers_offset = init->buffers_offset; dev_priv->gart_textures_offset = init->gart_textures_offset; if (!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); if (!dev_priv->cp_ring) { DRM_ERROR("could not find cp ring region!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); if (!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); if (!dev->agp_buffer_map) { DRM_ERROR("could not find dma buffer region!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } if (init->gart_textures_offset) { dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset); if (!dev_priv->gart_textures) { DRM_ERROR("could not find GART texture region!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } } dev_priv->sarea_priv = (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) { drm_core_ioremap(dev_priv->cp_ring, dev); drm_core_ioremap(dev_priv->ring_rptr, dev); drm_core_ioremap(dev->agp_buffer_map, dev); if (!dev_priv->cp_ring->handle || !dev_priv->ring_rptr->handle || !dev->agp_buffer_map->handle) { DRM_ERROR("could not find ioremap agp regions!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } } else #endif { dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; dev_priv->ring_rptr->handle = (void *)dev_priv->ring_rptr->offset; dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; DRM_DEBUG("dev_priv->cp_ring->handle %p\n", dev_priv->cp_ring->handle); DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", dev_priv->ring_rptr->handle); DRM_DEBUG("dev->agp_buffer_map->handle %p\n", dev->agp_buffer_map->handle); } dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff) << 16; dev_priv->fb_size = ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000) - dev_priv->fb_location; dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | ((dev_priv->front_offset + dev_priv->fb_location) >> 10)); dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | ((dev_priv->back_offset + dev_priv->fb_location) >> 10)); dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | ((dev_priv->depth_offset + dev_priv->fb_location) >> 10)); dev_priv->gart_size = init->gart_size; /* New let's set the memory map ... */ if (dev_priv->new_memmap) { u32 base = 0; DRM_INFO("Setting GART location based on new memory map\n"); /* If using AGP, try to locate the AGP aperture at the same * location in the card and on the bus, though we have to * align it down. */ #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) { base = dev->agp->base; /* Check if valid */ if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", dev->agp->base); base = 0; } } #endif /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ if (base == 0) { base = dev_priv->fb_location + dev_priv->fb_size; if (base < dev_priv->fb_location || ((base + dev_priv->gart_size) & 0xfffffffful) < base) base = dev_priv->fb_location - dev_priv->gart_size; } dev_priv->gart_vm_start = base & 0xffc00000u; if (dev_priv->gart_vm_start != base) DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", base, dev_priv->gart_vm_start); } else { DRM_INFO("Setting GART location based on old memory map\n"); dev_priv->gart_vm_start = dev_priv->fb_location + RADEON_READ(RADEON_CONFIG_APER_SIZE); } #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - dev->agp->base + dev_priv->gart_vm_start); else #endif dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - (unsigned long)dev->sg->virtual + dev_priv->gart_vm_start); DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", dev_priv->gart_buffers_offset); dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle + init->ring_size / sizeof(u32)); dev_priv->ring.size = init->ring_size; dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) { /* Turn off PCI GART */ radeon_set_pcigart(dev_priv, 0); } else #endif { /* if we have an offset set from userspace */ if (dev_priv->pcigart_offset) { dev_priv->gart_info.bus_addr = dev_priv->pcigart_offset + dev_priv->fb_location; dev_priv->gart_info.mapping.offset = dev_priv->gart_info.bus_addr; dev_priv->gart_info.mapping.size = RADEON_PCIGART_TABLE_SIZE; drm_core_ioremap(&dev_priv->gart_info.mapping, dev); dev_priv->gart_info.addr = dev_priv->gart_info.mapping.handle; dev_priv->gart_info.is_pcie = !!(dev_priv->flags & RADEON_IS_PCIE); dev_priv->gart_info.gart_table_location = DRM_ATI_GART_FB; DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", dev_priv->gart_info.addr, dev_priv->pcigart_offset); } else { dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; dev_priv->gart_info.addr = NULL; dev_priv->gart_info.bus_addr = 0; if (dev_priv->flags & RADEON_IS_PCIE) { DRM_ERROR ("Cannot use PCI Express without GART in FB memory\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } } if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { DRM_ERROR("failed to init PCI GART!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(ENOMEM); } /* Turn on PCI GART */ radeon_set_pcigart(dev_priv, 1); } radeon_cp_load_microcode(dev_priv); radeon_cp_init_ring_buffer(dev, dev_priv); dev_priv->last_buf = 0; radeon_do_engine_reset(dev); radeon_test_writeback(dev_priv); return 0; } static int radeon_do_cleanup_cp(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ if (dev->irq_enabled) drm_irq_uninstall(dev); #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) { if (dev_priv->cp_ring != NULL) { drm_core_ioremapfree(dev_priv->cp_ring, dev); dev_priv->cp_ring = NULL; } if (dev_priv->ring_rptr != NULL) { drm_core_ioremapfree(dev_priv->ring_rptr, dev); dev_priv->ring_rptr = NULL; } if (dev->agp_buffer_map != NULL) { drm_core_ioremapfree(dev->agp_buffer_map, dev); dev->agp_buffer_map = NULL; } } else #endif { if (dev_priv->gart_info.bus_addr) { /* Turn off PCI GART */ radeon_set_pcigart(dev_priv, 0); if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) DRM_ERROR("failed to cleanup PCI GART!\n"); } if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); dev_priv->gart_info.addr = 0; } } /* only clear to the start of flags */ memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); return 0; } /* This code will reinit the Radeon CP hardware after a resume from disc. * AFAIK, it would be very difficult to pickle the state at suspend time, so * here we make sure that all Radeon hardware initialisation is re-done without * affecting running applications. * * Charl P. Botha <http://cpbotha.net> */ static int radeon_do_resume_cp(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; if (!dev_priv) { DRM_ERROR("Called with no initialization\n"); return DRM_ERR(EINVAL); } DRM_DEBUG("Starting radeon_do_resume_cp()\n"); #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) { /* Turn off PCI GART */ radeon_set_pcigart(dev_priv, 0); } else #endif { /* Turn on PCI GART */ radeon_set_pcigart(dev_priv, 1); } radeon_cp_load_microcode(dev_priv); radeon_cp_init_ring_buffer(dev, dev_priv); radeon_do_engine_reset(dev); DRM_DEBUG("radeon_do_resume_cp() complete\n"); return 0; } int radeon_cp_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_init_t init; LOCK_TEST_WITH_RETURN(dev, filp); DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data, sizeof(init)); if (init.func == RADEON_INIT_R300_CP) r300_init_reg_flags(); switch (init.func) { case RADEON_INIT_CP: case RADEON_INIT_R200_CP: case RADEON_INIT_R300_CP: return radeon_do_init_cp(dev, &init); case RADEON_CLEANUP_CP: return radeon_do_cleanup_cp(dev); } return DRM_ERR(EINVAL); } int radeon_cp_start(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, filp); if (dev_priv->cp_running) { DRM_DEBUG("%s while CP running\n", __FUNCTION__); return 0; } if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { DRM_DEBUG("%s called with bogus CP mode (%d)\n", __FUNCTION__, dev_priv->cp_mode); return 0; } radeon_do_cp_start(dev_priv); return 0; } /* Stop the CP. The engine must have been idled before calling this * routine. */ int radeon_cp_stop(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_cp_stop_t stop; int ret; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, filp); DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data, sizeof(stop)); if (!dev_priv->cp_running) return 0; /* Flush any pending CP commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ if (stop.flush) { radeon_do_cp_flush(dev_priv); } /* If we fail to make the engine go idle, we return an error * code so that the DRM ioctl wrapper can try again. */ if (stop.idle) { ret = radeon_do_cp_idle(dev_priv); if (ret) return ret; } /* Finally, we can turn off the CP. If the engine isn't idle, * we will get some dropped triangles as they won't be fully * rendered before the CP is shut down. */ radeon_do_cp_stop(dev_priv); /* Reset the engine */ radeon_do_engine_reset(dev); return 0; } void radeon_do_release(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; int i, ret; if (dev_priv) { if (dev_priv->cp_running) { /* Stop the cp */ while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { DRM_DEBUG("radeon_do_cp_idle %d\n", ret); #ifdef __linux__ schedule(); #else #if defined(__FreeBSD__) && __FreeBSD_version > 500000 msleep(&ret, &dev->dev_lock, PZERO, "rdnrel", 1); #else tsleep(&ret, PZERO, "rdnrel", 1); #endif #endif } radeon_do_cp_stop(dev_priv); radeon_do_engine_reset(dev); } /* Disable *all* interrupts */ if (dev_priv->mmio) /* remove this after permanent addmaps */ RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); if (dev_priv->mmio) { /* remove all surfaces */ for (i = 0; i < RADEON_MAX_SURFACES; i++) { RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, 0); RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, 0); } } /* Free memory heap structures */ radeon_mem_takedown(&(dev_priv->gart_heap)); radeon_mem_takedown(&(dev_priv->fb_heap)); /* deallocate kernel resources */ radeon_do_cleanup_cp(dev); } } /* Just reset the CP ring. Called as part of an X Server engine reset. */ int radeon_cp_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, filp); if (!dev_priv) { DRM_DEBUG("%s called before init done\n", __FUNCTION__); return DRM_ERR(EINVAL); } radeon_do_cp_reset(dev_priv); /* The CP is no longer running after an engine reset */ dev_priv->cp_running = 0; return 0; } int radeon_cp_idle(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, filp); return radeon_do_cp_idle(dev_priv); } /* Added by Charl P. Botha to call radeon_do_resume_cp(). */ int radeon_cp_resume(DRM_IOCTL_ARGS) { DRM_DEVICE; return radeon_do_resume_cp(dev); } int radeon_engine_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, filp); return radeon_do_engine_reset(dev); } /* ================================================================ * Fullscreen mode */ /* KW: Deprecated to say the least: */ int radeon_fullscreen(DRM_IOCTL_ARGS) { return 0; } /* ================================================================ * Freelist management */ /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through * bufs until freelist code is used. Note this hides a problem with * the scratch register * (used to keep track of last buffer * completed) being written to before * the last buffer has actually * completed rendering. * * KW: It's also a good way to find free buffers quickly. * * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't * sleep. However, bugs in older versions of radeon_accel.c mean that * we essentially have to do this, else old clients will break. * * However, it does leave open a potential deadlock where all the * buffers are held by other clients, which can't release them because * they can't get the lock. */ drm_buf_t *radeon_freelist_get(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv; drm_buf_t *buf; int i, t; int start; if (++dev_priv->last_buf >= dma->buf_count) dev_priv->last_buf = 0; start = dev_priv->last_buf; for (t = 0; t < dev_priv->usec_timeout; t++) { u32 done_age = GET_SCRATCH(1); DRM_DEBUG("done_age = %d\n", done_age); for (i = start; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; if (buf->filp == 0 || (buf->pending && buf_priv->age <= done_age)) { dev_priv->stats.requested_bufs++; buf->pending = 0; return buf; } start = 0; } if (t) { DRM_UDELAY(1); dev_priv->stats.freelist_loops++; } } DRM_DEBUG("returning NULL!\n"); return NULL; } #if 0 drm_buf_t *radeon_freelist_get(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv; drm_buf_t *buf; int i, t; int start; u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); if (++dev_priv->last_buf >= dma->buf_count) dev_priv->last_buf = 0; start = dev_priv->last_buf; dev_priv->stats.freelist_loops++; for (t = 0; t < 2; t++) { for (i = start; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; if (buf->filp == 0 || (buf->pending && buf_priv->age <= done_age)) { dev_priv->stats.requested_bufs++; buf->pending = 0; return buf; } } start = 0; } return NULL; } #endif void radeon_freelist_reset(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; int i; dev_priv->last_buf = 0; for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[i]; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; buf_priv->age = 0; } } /* ================================================================ * CP command submission */ int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) { drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; u32 last_head = GET_RING_HEAD(dev_priv); for (i = 0; i < dev_priv->usec_timeout; i++) { u32 head = GET_RING_HEAD(dev_priv); ring->space = (head - ring->tail) * sizeof(u32); if (ring->space <= 0) ring->space += ring->size; if (ring->space > n) return 0; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; if (head != last_head) i = 0; last_head = head; DRM_UDELAY(1); } /* FIXME: This return value is ignored in the BEGIN_RING macro! */ #if RADEON_FIFO_DEBUG radeon_status(dev_priv); DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) { int i; drm_buf_t *buf; for (i = d->granted_count; i < d->request_count; i++) { buf = radeon_freelist_get(dev); if (!buf) return DRM_ERR(EBUSY); /* NOTE: broken client */ buf->filp = filp; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) return DRM_ERR(EFAULT); if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, sizeof(buf->total))) return DRM_ERR(EFAULT); d->granted_count++; } return 0; } int radeon_cp_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; int ret = 0; drm_dma_t __user *argp = (void __user *)data; drm_dma_t d; LOCK_TEST_WITH_RETURN(dev, filp); DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); /* Please don't send us buffers. */ if (d.send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", DRM_CURRENTPID, d.send_count); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ if (d.request_count < 0 || d.request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", DRM_CURRENTPID, d.request_count, dma->buf_count); return DRM_ERR(EINVAL); } d.granted_count = 0; if (d.request_count) { ret = radeon_cp_get_buffers(filp, dev, &d); } DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); return ret; } int radeon_driver_load(struct drm_device *dev, unsigned long flags) { drm_radeon_private_t *dev_priv; int ret = 0; dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) return DRM_ERR(ENOMEM); memset(dev_priv, 0, sizeof(drm_radeon_private_t)); dev->dev_private = (void *)dev_priv; dev_priv->flags = flags; switch (flags & RADEON_FAMILY_MASK) { case CHIP_R100: case CHIP_RV200: case CHIP_R200: case CHIP_R300: case CHIP_R350: case CHIP_R420: case CHIP_RV410: dev_priv->flags |= RADEON_HAS_HIERZ; break; default: /* all other chips have no hierarchical z buffer */ break; } if (drm_device_is_agp(dev)) dev_priv->flags |= RADEON_IS_AGP; else if (drm_device_is_pcie(dev)) dev_priv->flags |= RADEON_IS_PCIE; else dev_priv->flags |= RADEON_IS_PCI; DRM_DEBUG("%s card detected\n", ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); return ret; } /* Create mappings for registers and framebuffer so userland doesn't necessarily * have to find them. */ int radeon_driver_firstopen(struct drm_device *dev) { int ret; drm_local_map_t *map; drm_radeon_private_t *dev_priv = dev->dev_private; ret = drm_addmap(dev, drm_get_resource_start(dev, 2), drm_get_resource_len(dev, 2), _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio); if (ret != 0) return ret; ret = drm_addmap(dev, drm_get_resource_start(dev, 0), drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, &map); if (ret != 0) return ret; return 0; } int radeon_driver_unload(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); dev->dev_private = NULL; return 0; }