linux-core/Kconfig


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#
# Drm device configuration
#
# This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
#
config DRM
	bool "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)"
	help
	  Kernel-level support for the Direct Rendering Infrastructure (DRI)
	  introduced in XFree86 4.0. If you say Y here, you need to select
	  the module that's right for your graphics card from the list below.
	  These modules provide support for synchronization, security, and
	  DMA transfers. Please see <http://dri.sourceforge.net/> for more
	  details.  You should also select and configure AGP
	  (/dev/agpgart) support.

config DRM_TDFX
	tristate "3dfx Banshee/Voodoo3+"
	depends on DRM && PCI
	help
	  Choose this option if you have a 3dfx Banshee or Voodoo3 (or later),
	  graphics card.  If M is selected, the module will be called tdfx.

config DRM_R128
	tristate "ATI Rage 128"
	depends on DRM && PCI
	help
	  Choose this option if you have an ATI Rage 128 graphics card.  If M
	  is selected, the module will be called r128.  AGP support for
	  this card is strongly suggested (unless you have a PCI version).

config DRM_RADEON
	tristate "ATI Radeon"
	depends on DRM && PCI
	help
	  Choose this option if you have an ATI Radeon graphics card.  There
	  are both PCI and AGP versions.  You don't need to choose this to
	  run the Radeon in plain VGA mode.  There is a product page at
	  <http://www.ati.com/na/pages/products/pc/radeon32/index.html>.
	  If M is selected, the module will be called radeon.

config DRM_I810
	tristate "Intel I810"
	depends on DRM && AGP && AGP_INTEL
	help
	  Choose this option if you have an Intel I810 graphics card.  If M is
	  selected, the module will be called i810.  AGP support is required
	  for this driver to work.

choice
	prompt "Intel 830M, 845G, 852GM, 855GM, 865G"
	depends on DRM && AGP && AGP_INTEL
	optional

config DRM_I915
	tristate "i915 driver"
	help
	  Choose this option if you have a system that has Intel 830M, 845G,
	  852GM, 855GM, 865G, 915G, 915GM, 945G, 945GM and 965G integrated 
	  graphics.  If M is selected, the module will be called i915.  
	  AGP support is required for this driver to work.
	
endchoice

config DRM_MGA
	tristate "Matrox g200/g400"
	depends on DRM && (!X86_64 || BROKEN) && (!PPC || BROKEN)
	help
	  Choose this option if you have a Matrox G200, G400, G450 or G550
	  graphics card.  If M is selected, the module will be called mga.

config DRM_SIS
	tristate "SiS video cards"
	depends on DRM
	help
	  Choose this option if you have a SiS 630 or compatible video 
	  chipset. If M is selected the module will be called sis.

config DRM_VIA
	tristate "Via unichrome video cards"
	depends on DRM 
	help
	  Choose this option if you have a Via unichrome or compatible video 
	  chipset. If M is selected the module will be called via.

config DRM_MACH64
	tristate "ATI Rage Pro (Mach64)"
	depends on DRM && PCI
	help
	  Choose this option if you have an ATI Rage Pro (mach64 chipset)
	  graphics card.  Example cards include:  3D Rage Pro, Xpert 98,
	  3D Rage LT Pro, 3D Rage XL/XC, and 3D Rage Mobility (P/M, M1).
	  Cards earlier than ATI Rage Pro (e.g. Rage II) are not supported.
	  If M is selected, the module will be called mach64.  AGP support for
	  this card is strongly suggested (unless you have a PCI version).
/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
 *
 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Kevin E. Martin <martin@valinux.com>
 *    Gareth Hughes <gareth@valinux.com>
 *    Keith Whitwell <keith@tungstengraphics.com>
 */

#ifndef __RADEON_DRM_H__
#define __RADEON_DRM_H__

/* WARNING: If you change any of these defines, make sure to change the
 * defines in the X server file (radeon_sarea.h)
 */
#ifndef __RADEON_SAREA_DEFINES__
#define __RADEON_SAREA_DEFINES__

/* Old style state flags, required for sarea interface (1.1 and 1.2
 * clears) and 1.2 drm_vertex2 ioctl.
 */
#define RADEON_UPLOAD_CONTEXT		0x00000001
#define RADEON_UPLOAD_VERTFMT		0x00000002
#define RADEON_UPLOAD_LINE		0x00000004
#define RADEON_UPLOAD_BUMPMAP		0x00000008
#define RADEON_UPLOAD_MASKS		0x00000010
#define RADEON_UPLOAD_VIEWPORT		0x00000020
#define RADEON_UPLOAD_SETUP		0x00000040
#define RADEON_UPLOAD_TCL		0x00000080
#define RADEON_UPLOAD_MISC		0x00000100
#define RADEON_UPLOAD_TEX0		0x00000200
#define RADEON_UPLOAD_TEX1		0x00000400
#define RADEON_UPLOAD_TEX2		0x00000800
#define RADEON_UPLOAD_TEX0IMAGES	0x00001000
#define RADEON_UPLOAD_TEX1IMAGES	0x00002000
#define RADEON_UPLOAD_TEX2IMAGES	0x00004000
#define RADEON_UPLOAD_CLIPRECTS		0x00008000 /* handled client-side */
#define RADEON_REQUIRE_QUIESCENCE	0x00010000
#define RADEON_UPLOAD_ZBIAS		0x00020000 /* version 1.2 and newer */
#define RADEON_UPLOAD_ALL		0x003effff
#define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff


/* New style per-packet identifiers for use in cmd_buffer ioctl with
 * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
 * state bits and the packet size:
 */
#define RADEON_EMIT_PP_MISC                         0 /* context/7 */
#define RADEON_EMIT_PP_CNTL                         1 /* context/3 */
#define RADEON_EMIT_RB3D_COLORPITCH                 2 /* context/1 */
#define RADEON_EMIT_RE_LINE_PATTERN                 3 /* line/2 */
#define RADEON_EMIT_SE_LINE_WIDTH                   4 /* line/1 */
#define RADEON_EMIT_PP_LUM_MATRIX                   5 /* bumpmap/1 */
#define RADEON_EMIT_PP_ROT_MATRIX_0                 6 /* bumpmap/2 */
#define RADEON_EMIT_RB3D_STENCILREFMASK             7 /* masks/3 */
#define RADEON_EMIT_SE_VPORT_XSCALE                 8 /* viewport/6 */
#define RADEON_EMIT_SE_CNTL                         9 /* setup/2 */
#define RADEON_EMIT_SE_CNTL_STATUS                  10 /* setup/1 */
#define RADEON_EMIT_RE_MISC                         11 /* misc/1 */
#define RADEON_EMIT_PP_TXFILTER_0                   12 /* tex0/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_0               13 /* tex0/1 */
#define RADEON_EMIT_PP_TXFILTER_1                   14 /* tex1/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_1               15 /* tex1/1 */
#define RADEON_EMIT_PP_TXFILTER_2                   16 /* tex2/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_2               17 /* tex2/1 */
#define RADEON_EMIT_SE_ZBIAS_FACTOR                 18 /* zbias/2 */
#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19 /* tcl/11 */
#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20 /* material/17 */
#define R200_EMIT_PP_TXCBLEND_0                     21 /* tex0/4 */
#define R200_EMIT_PP_TXCBLEND_1                     22 /* tex1/4 */
#define R200_EMIT_PP_TXCBLEND_2                     23 /* tex2/4 */
#define R200_EMIT_PP_TXCBLEND_3                     24 /* tex3/4 */
#define R200_EMIT_PP_TXCBLEND_4                     25 /* tex4/4 */
#define R200_EMIT_PP_TXCBLEND_5                     26 /* tex5/4 */
#define R200_EMIT_PP_TXCBLEND_6                     27 /* /4 */
#define R200_EMIT_PP_TXCBLEND_7                     28 /* /4 */
#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29 /* tcl/7 */
#define R200_EMIT_TFACTOR_0                         30 /* tf/7 */
#define R200_EMIT_VTX_FMT_0                         31 /* vtx/5 */
#define R200_EMIT_VAP_CTL                           32 /* vap/1 */
#define R200_EMIT_MATRIX_SELECT_0                   33 /* msl/5 */
#define R200_EMIT_TEX_PROC_CTL_2                    34 /* tcg/5 */
#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35 /* tcl/1 */
#define R200_EMIT_PP_TXFILTER_0                     36 /* tex0/6 */
#define R200_EMIT_PP_TXFILTER_1                     37 /* tex1/6 */
#define R200_EMIT_PP_TXFILTER_2                     38 /* tex2/6 */
#define R200_EMIT_PP_TXFILTER_3                     39 /* tex3/6 */
#define R200_EMIT_PP_TXFILTER_4                     40 /* tex4/6 */
#define R200_EMIT_PP_TXFILTER_5                     41 /* tex5/6 */
#define R200_EMIT_PP_TXOFFSET_0                     42 /* tex0/1 */
#define R200_EMIT_PP_TXOFFSET_1                     43 /* tex1/1 */
#define R200_EMIT_PP_TXOFFSET_2                     44 /* tex2/1 */
#define R200_EMIT_PP_TXOFFSET_3                     45 /* tex3/1 */
#define R200_EMIT_PP_TXOFFSET_4                     46 /* tex4/1 */
#define R200_EMIT_PP_TXOFFSET_5                     47 /* tex5/1 */
#define R200_EMIT_VTE_CNTL                          48 /* vte/1 */
#define R200_EMIT_OUTPUT_VTX_COMP_SEL               49 /* vtx/1 */
#define R200_EMIT_PP_TAM_DEBUG3                     50 /* tam/1 */
#define R200_EMIT_PP_CNTL_X                         51 /* cst/1 */
#define R200_EMIT_RB3D_DEPTHXY_OFFSET               52 /* cst/1 */
#define R200_EMIT_RE_AUX_SCISSOR_CNTL               53 /* cst/1 */
#define R200_EMIT_RE_SCISSOR_TL_0                   54 /* cst/2 */
#define R200_EMIT_RE_SCISSOR_TL_1                   55 /* cst/2 */
#define R200_EMIT_RE_SCISSOR_TL_2                   56 /* cst/2 */
#define R200_EMIT_SE_VAP_CNTL_STATUS                57 /* cst/1 */
#define R200_EMIT_SE_VTX_STATE_CNTL                 58 /* cst/1 */
#define R200_EMIT_RE_POINTSIZE                      59 /* cst/1 */
#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60 /* cst/4 */
#define R200_EMIT_PP_CUBIC_FACES_0                  61
#define R200_EMIT_PP_CUBIC_OFFSETS_0                62
#define R200_EMIT_PP_CUBIC_FACES_1                  63
#define R200_EMIT_PP_CUBIC_OFFSETS_1                64
#define R200_EMIT_PP_CUBIC_FACES_2                  65
#define R200_EMIT_PP_CUBIC_OFFSETS_2                66
#define R200_EMIT_PP_CUBIC_FACES_3                  67
#define R200_EMIT_PP_CUBIC_OFFSETS_3                68
#define R200_EMIT_PP_CUBIC_FACES_4                  69
#define R200_EMIT_PP_CUBIC_OFFSETS_4                70
#define R200_EMIT_PP_CUBIC_FACES_5                  71
#define R200_EMIT_PP_CUBIC_OFFSETS_5                72
#define RADEON_EMIT_PP_TEX_SIZE_0                   73
#define RADEON_EMIT_PP_TEX_SIZE_1                   74
#define RADEON_EMIT_PP_TEX_SIZE_2                   75
#define R200_EMIT_RB3D_BLENDCOLOR                   76
#define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
#define RADEON_EMIT_PP_CUBIC_FACES_0                78
#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
#define RADEON_EMIT_PP_CUBIC_FACES_1                80
#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
#define RADEON_EMIT_PP_CUBIC_FACES_2                82
#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
#define R200_EMIT_PP_TRI_PERF_CNTL                  84
#define RADEON_MAX_STATE_PACKETS                    85


/* Commands understood by cmd_buffer ioctl.  More can be added but
 * obviously these can't be removed or changed:
 */
#define RADEON_CMD_PACKET      1 /* emit one of the register packets above */
#define RADEON_CMD_SCALARS     2 /* emit scalar data */
#define RADEON_CMD_VECTORS     3 /* emit vector data */
#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
#define RADEON_CMD_PACKET3     5 /* emit hw packet */
#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
#define RADEON_CMD_SCALARS2     7 /* r200 stopgap */
#define RADEON_CMD_WAIT         8 /* emit hw wait commands -- note:
				   *  doesn't make the cpu wait, just
				   *  the graphics hardware */


typedef union {
	int i;
	struct { 
		unsigned char cmd_type, pad0, pad1, pad2;