/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com */ /* * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Gareth Hughes * Kevin E. Martin */ #ifndef __R128_DRM_H__ #define __R128_DRM_H__ /* WARNING: If you change any of these defines, make sure to change the * defines in the X server file (r128_sarea.h) */ #ifndef __R128_SAREA_DEFINES__ #define __R128_SAREA_DEFINES__ /* What needs to be changed for the current vertex buffer? */ #define R128_UPLOAD_CONTEXT 0x001 #define R128_UPLOAD_SETUP 0x002 #define R128_UPLOAD_TEX0 0x004 #define R128_UPLOAD_TEX1 0x008 #define R128_UPLOAD_TEX0IMAGES 0x010 #define R128_UPLOAD_TEX1IMAGES 0x020 #define R128_UPLOAD_CORE 0x040 #define R128_UPLOAD_MASKS 0x080 #define R128_UPLOAD_WINDOW 0x100 #define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ #define R128_REQUIRE_QUIESCENCE 0x400 #define R128_UPLOAD_ALL 0x7ff #define R128_FRONT 0x1 #define R128_BACK 0x2 #define R128_DEPTH 0x4 /* Primitive types */ #define R128_POINTS 0x1 #define R128_LINES 0x2 #define R128_LINE_STRIP 0x3 #define R128_TRIANGLES 0x4 #define R128_TRIANGLE_FAN 0x5 #define R128_TRIANGLE_STRIP 0x6 /* Vertex/indirect buffer size */ #define R128_BUFFER_SIZE 16384 /* Byte offsets for indirect buffer data */ #define R128_INDEX_PRIM_OFFSET 20 #define R128_HOSTDATA_BLIT_OFFSET 32 /* Keep these small for testing. */ #define R128_NR_SAREA_CLIPRECTS 12 /* There are 2 heaps (local/AGP). Each region within a heap is a * minimum of 64k, and there are at most 64 of them per heap. */ #define R128_LOCAL_TEX_HEAP 0 #define R128_AGP_TEX_HEAP 1 #define R128_NR_TEX_HEAPS 2 #define R128_NR_TEX_REGIONS 64 #define R128_LOG_TEX_GRANULARITY 16 #define R128_NR_CONTEXT_REGS 12 #define R128_MAX_TEXTURE_LEVELS 11 #define R128_MAX_TEXTURE_UNITS 2 #endif /* __R128_SAREA_DEFINES__ */ typedef struct { /* Context state - can be written in one large chunk */ unsigned int dst_pitch_offset_c; unsigned int dp_gui_master_cntl_c; unsigned int sc_top_left_c; unsigned int sc_bottom_right_c; unsigned int z_offset_c; unsigned int z_pitch_c; unsigned int z_sten_cntl_c; unsigned int tex_cntl_c; unsigned int misc_3d_state_cntl_reg; unsigned int texture_clr_cmp_clr_c; unsigned int texture_clr_cmp_msk_c; unsigned int fog_color_c; /* Texture state */ unsigned int tex_size_pitch_c; unsigned int constant_color_c; /* Setup state */ unsigned int pm4_vc_fpu_setup; unsigned int setup_cntl; /* Mask state */ unsigned int dp_write_mask; unsigned int sten_ref_mask_c; unsigned int plane_3d_mask_c; /* Window state */ unsigned int window_xy_offset; /* Core state */ unsigned int scale_3d_cntl; } drm_r128_context_regs_t; /* Setup registers for each texture unit */ typedef struct { unsigned int tex_cntl; unsigned int tex_combine_cntl; unsigned int tex_size_pitch; unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; unsigned int tex_border_color; } drm_r128_texture_regs_t; typedef struct drm_r128_sarea { /* The channel for communication of state information to the kernel * on firing a vertex buffer. */ drm_r128_context_regs_t context_state; drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; unsigned int dirty; unsigned int vertsize; unsigned int vc_format; /* The current cliprects, or a subset thereof. */ struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Counters for client-side throttling of rendering clients. */ unsigned int last_frame; unsigned int last_dispatch; struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; unsigned int tex_age[R128_NR_TEX_HEAPS]; int ctx_owner; int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ int pfCurrentPage; /* which buffer is being displayed? */ } drm_r128_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmR128.h) */ /* Rage 128 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_R128_INIT 0x00 #define DRM_R128_CCE_START 0x01 #define DRM_R128_CCE_STOP 0x02 #define DRM_R128_CCE_RESET 0x03 #define DRM_R128_CCE_IDLE 0x04 /* 0x05 not used */ #define DRM_R128_RESET 0x06 #define DRM_R128_SWAP 0x07 #define DRM_R128_CLEAR 0x08 #define DRM_R128_VERTEX 0x09 #define DRM_R128_INDICES 0x0a #define DRM_R128_BLIT 0x0b #define DRM_R128_DEPTH 0x0c #define DRM_R128_STIPPLE 0x0d /* 0x0e not used */ #define DRM_R128_INDIRECT 0x0f #define DRM_R128_FULLSCREEN 0x10 #define DRM_R128_CLEAR2 0x11 #define DRM_R128_GETPARAM 0x12 #define DRM_R128_FLIP 0x13 #define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) #define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) #define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) #define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) #define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) /* 0x05 not used */ #define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) #define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) #define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) #define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) #define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) #define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) #define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) #define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) /* 0x0e not used */ #define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) #define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) #define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) #define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) typedef struct drm_r128_init { enum { R128_INIT_CCE = 0x01, R128_CLEANUP_CCE = 0x02 } func; unsigned long sarea_priv_offset; int is_pci; int cce_mode; int cce_secure; int ring_size; int usec_timeout; unsigned int fb_bpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_bpp; unsigned int depth_offset, depth_pitch; unsigned int span_offset; unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; unsigned long ring_rptr_offset; unsigned long buffers_offset; unsigned long agp_textures_offset; } drm_r128_init_t; typedef struct drm_r128_cce_stop { int flush; int idle; } drm_r128_cce_stop_t; typedef struct drm_r128_clear { unsigned int flags; unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; unsigned int depth_mask; } drm_r128_clear_t; typedef struct drm_r128_vertex { int prim; int idx; /* Index of vertex buffer */ int count; /* Number of vertices in buffer */ int discard; /* Client finished with buffer? */ } drm_r128_vertex_t; typedef struct drm_r128_indices { int prim; int idx; int start; int end; int discard; /* Client finished with buffer? */ } drm_r128_indices_t; typedef struct drm_r128_blit { int idx; int pitch; int offset; int format; unsigned short x, y; unsigned short width, height; } drm_r128_blit_t; typedef struct drm_r128_depth { enum { R128_WRITE_SPAN = 0x01, R128_WRITE_PIXELS = 0x02, R128_READ_SPAN = 0x03, R128_READ_PIXELS = 0x04 } func; int n; int *x; int *y; unsigned int *buffer; unsigned char *mask; } drm_r128_depth_t; typedef struct drm_r128_stipple { unsigned int *mask; } drm_r128_stipple_t; typedef struct drm_r128_indirect { int idx; int start; int end; int discard; } drm_r128_indirect_t; typedef struct drm_r128_fullscreen { enum { R128_INIT_FULLSCREEN = 0x01, R128_CLEANUP_FULLSCREEN = 0x02 } func; } drm_r128_fullscreen_t; /* 2.3: An ioctl to get parameters that aren't available to the 3d * client any other way. */ #define R128_PARAM_IRQ_NR 1 typedef struct drm_r128_getparam { int param; void *value; } drm_r128_getparam_t; #endif id='n211' href='#n211'>211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 
/* mga_state.c -- State support for mga g200/g400
 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors: Jeff Hartmann <jhartmann@precisioninsight.com>
 * 	    Keith Whitwell <keithw@precisioninsight.com>
 *
 */

#define __NO_VERSION__
#include "drmP.h"
#include "mga_drv.h"
#include "drm.h"

typedef u_int16_t u16;
typedef u_int32_t u32;

static void mgaEmitClipRect(drm_mga_private_t * dev_priv,
			    drm_clip_rect_t * box)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->ContextState;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	/* This takes 10 dwords */
	PRIMGETPTR(dev_priv);

	/* Force reset of dwgctl (eliminates clip disable) */
#if 0
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DWGSYNC, 0);
	PRIMOUTREG(MGAREG_DWGSYNC, 0);
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
#else
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
	PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000);
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
	PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000);
#endif

	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_CXBNDRY, ((box->x2) << 16) | (box->x1));
	PRIMOUTREG(MGAREG_YTOP, box->y1 * dev_priv->stride / 2);
	PRIMOUTREG(MGAREG_YBOT, box->y2 * dev_priv->stride / 2);

	PRIMADVANCE(dev_priv);
}

static void mgaEmitContext(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->ContextState;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	/* This takes a max of 15 dwords */
	PRIMGETPTR(dev_priv);

	PRIMOUTREG(MGAREG_DSTORG, regs[MGA_CTXREG_DSTORG]);
	PRIMOUTREG(MGAREG_MACCESS, regs[MGA_CTXREG_MACCESS]);
	PRIMOUTREG(MGAREG_PLNWT, regs[MGA_CTXREG_PLNWT]);
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);

	PRIMOUTREG(MGAREG_ALPHACTRL, regs[MGA_CTXREG_ALPHACTRL]);
	PRIMOUTREG(MGAREG_FOGCOL, regs[MGA_CTXREG_FOGCOLOR]);
	PRIMOUTREG(MGAREG_WFLAG, regs[MGA_CTXREG_WFLAG]);
	PRIMOUTREG(MGAREG_ZORG, dev_priv->depthOffset);	/* invarient */

	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
		PRIMOUTREG(MGAREG_WFLAG1, regs[MGA_CTXREG_WFLAG]);
		PRIMOUTREG(MGAREG_TDUALSTAGE0, regs[MGA_CTXREG_TDUAL0]);
		PRIMOUTREG(MGAREG_TDUALSTAGE1, regs[MGA_CTXREG_TDUAL1]);
		PRIMOUTREG(MGAREG_FCOL, regs[MGA_CTXREG_FCOL]);
	} else {
		PRIMOUTREG(MGAREG_FCOL, regs[MGA_CTXREG_FCOL]);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
	}

	PRIMADVANCE(dev_priv);
}

static void mgaG200EmitTex(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->TexState[0];
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	PRIMGETPTR(dev_priv);

	/* This takes 20 dwords */

	PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2]);
	PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
	PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
	PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);

	PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]);
	PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]);
	PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]);
	PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]);

	PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]);
	PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]);
	PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]);
	PRIMOUTREG(0x2d00 + 24 * 4, regs[MGA_TEXREG_WIDTH]);

	PRIMOUTREG(0x2d00 + 34 * 4, regs[MGA_TEXREG_HEIGHT]);
	PRIMOUTREG(MGAREG_TEXTRANS, 0xffff);
	PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff);
	PRIMOUTREG(MGAREG_DMAPAD, 0);

	PRIMADVANCE(dev_priv);
}

static void mgaG400EmitTex0(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->TexState[0];
	int multitex = sarea_priv->WarpPipe & MGA_T2;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	PRIMGETPTR(dev_priv);

	/* This takes a max of 30 dwords */

	PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000);
	PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
	PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
	PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);

	PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]);
	PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]);
	PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]);
	PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]);

	PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]);
	PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]);
	PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]);
	PRIMOUTREG(0x2d00 + 49 * 4, 0);

	PRIMOUTREG(0x2d00 + 57 * 4, 0);
	PRIMOUTREG(0x2d00 + 53 * 4, 0);
	PRIMOUTREG(0x2d00 + 61 * 4, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);

	if (!multitex) {
		PRIMOUTREG(0x2d00 + 52 * 4, 0x40);
		PRIMOUTREG(0x2d00 + 60 * 4, 0x40);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
	}

	PRIMOUTREG(0x2d00 + 54 * 4, regs[MGA_TEXREG_WIDTH] | 0x40);
	PRIMOUTREG(0x2d00 + 62 * 4, regs[MGA_TEXREG_HEIGHT] | 0x40);
	PRIMOUTREG(MGAREG_TEXTRANS, 0xffff);
	PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff);

	PRIMADVANCE(dev_priv);
}

#define TMC_map1_enable 		0x80000000

static void mgaG400EmitTex1(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->TexState[1];
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	PRIMGETPTR(dev_priv);

	/* This takes 25 dwords */

	PRIMOUTREG(MGAREG_TEXCTL2,
		   regs[MGA_TEXREG_CTL2] | TMC_map1_enable | 0x00008000);
	PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]);
	PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]);
	PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]);

	PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]);
	PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]);
	PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]);
	PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]);

	PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]);
	PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]);
	PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]);
	PRIMOUTREG(0x2d00 + 49 * 4, 0);

	PRIMOUTREG(0x2d00 + 57 * 4, 0);
	PRIMOUTREG(0x2d00 + 53 * 4, 0);
	PRIMOUTREG(0x2d00 + 61 * 4, 0);
	PRIMOUTREG(0x2d00 + 52 * 4, regs[MGA_TEXREG_WIDTH] | 0x40);

	PRIMOUTREG(0x2d00 + 60 * 4, regs[MGA_TEXREG_HEIGHT] | 0x40);
	PRIMOUTREG(MGAREG_TEXTRANS, 0xffff);
	PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff);
	PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000);

	PRIMADVANCE(dev_priv);
}

#define EMIT_PIPE 50
static void mgaG400EmitPipe(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int pipe = sarea_priv->WarpPipe;
	float fParam = 12800.0f;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	PRIMGETPTR(dev_priv);

	/* This takes 50 dwords */

	/* Establish vertex size.  
	 */
	PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);

	if (pipe & MGA_T2) {
		PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
		PRIMOUTREG(MGAREG_DMAPAD, 0);

		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000);
	} else {
		if (dev_priv->WarpPipe & MGA_T2) {
			/* Flush the WARP pipe */
			PRIMOUTREG(MGAREG_YDST, 0);
			PRIMOUTREG(MGAREG_FXLEFT, 0);
			PRIMOUTREG(MGAREG_FXRIGHT, 1);
			PRIMOUTREG(MGAREG_DWGCTL, MGA_FLUSH_CMD);

			PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 1);
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_DWGSYNC, 0x7000);
			PRIMOUTREG(MGAREG_DMAPAD, 0);

			PRIMOUTREG(MGAREG_TEXCTL2, 0 | 0x00008000);
			PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0);
			PRIMOUTREG(MGAREG_TEXCTL2, 0x80 | 0x00008000);
			PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0);
		}

		PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
		PRIMOUTREG(MGAREG_DMAPAD, 0);
		PRIMOUTREG(MGAREG_DMAPAD, 0);

		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0);
		PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x18000000);
	}

	PRIMOUTREG(MGAREG_WFLAG, 0);
	PRIMOUTREG(MGAREG_WFLAG1, 0);
	PRIMOUTREG(0x2d00 + 56 * 4, *((u32 *) (&fParam)));
	PRIMOUTREG(MGAREG_DMAPAD, 0);

	PRIMOUTREG(0x2d00 + 49 * 4, 0);	/* Tex stage 0 */
	PRIMOUTREG(0x2d00 + 57 * 4, 0);	/* Tex stage 0 */
	PRIMOUTREG(0x2d00 + 53 * 4, 0);	/* Tex stage 1 */
	PRIMOUTREG(0x2d00 + 61 * 4, 0);	/* Tex stage 1 */

	PRIMOUTREG(0x2d00 + 54 * 4, 0x40);	/* Tex stage 0 : w */
	PRIMOUTREG(0x2d00 + 62 * 4, 0x40);	/* Tex stage 0 : h */
	PRIMOUTREG(0x2d00 + 52 * 4, 0x40);	/* Tex stage 1 : w */
	PRIMOUTREG(0x2d00 + 60 * 4, 0x40);	/* Tex stage 1 : h */

	/* Dma pading required due to hw bug */
	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
	PRIMOUTREG(MGAREG_WIADDR2,
		   (u32) (dev_priv->WarpIndex[pipe].
			  phys_addr | WIA_wmode_start | WIA_wagp_agp));
	PRIMADVANCE(dev_priv);
}

static void mgaG200EmitPipe(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int pipe = sarea_priv->WarpPipe;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	PRIMGETPTR(dev_priv);

	/* This takes 15 dwords */

	PRIMOUTREG(MGAREG_WIADDR, WIA_wmode_suspend);
	PRIMOUTREG(MGAREG_WVRTXSZ, 7);
	PRIMOUTREG(MGAREG_WFLAG, 0);
	PRIMOUTREG(0x2d00 + 24 * 4, 0);	/* tex w/h */

	PRIMOUTREG(0x2d00 + 25 * 4, 0x100);
	PRIMOUTREG(0x2d00 + 34 * 4, 0);	/* tex w/h */
	PRIMOUTREG(0x2d00 + 42 * 4, 0xFFFF);
	PRIMOUTREG(0x2d00 + 60 * 4, 0xFFFF);

	/* Dma pading required due to hw bug */
	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
	PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
	PRIMOUTREG(MGAREG_WIADDR,
		   (u32) (dev_priv->WarpIndex[pipe].
			  phys_addr | WIA_wmode_start | WIA_wagp_agp));

	PRIMADVANCE(dev_priv);
}

static void mgaEmitState(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int dirty = sarea_priv->dirty;
	DRM_DEBUG("%s\n", __FUNCTION__);

	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
		int multitex = sarea_priv->WarpPipe & MGA_T2;

		if (sarea_priv->WarpPipe != dev_priv->WarpPipe) {
			mgaG400EmitPipe(dev_priv);
			dev_priv->WarpPipe = sarea_priv->WarpPipe;
		}

		if (dirty & MGA_UPLOAD_CTX) {
			mgaEmitContext(dev_priv);
			sarea_priv->dirty &= ~MGA_UPLOAD_CTX;
		}

		if (dirty & MGA_UPLOAD_TEX0) {
			mgaG400EmitTex0(dev_priv);
			sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
		}

		if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
			mgaG400EmitTex1(dev_priv);
			sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
		}
	} else {
		if (sarea_priv->WarpPipe != dev_priv->WarpPipe) {
			mgaG200EmitPipe(dev_priv);
			dev_priv->WarpPipe = sarea_priv->WarpPipe;
		}

		if (dirty & MGA_UPLOAD_CTX) {
			mgaEmitContext(dev_priv);
			sarea_priv->dirty &= ~MGA_UPLOAD_CTX;
		}

		if (dirty & MGA_UPLOAD_TEX0) {
			mgaG200EmitTex(dev_priv);
			sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
		}
	}
}


/* Disallow all write destinations except the front and backbuffer.
 */
static int mgaVerifyContext(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->ContextState;

	DRM_DEBUG("%s\n", __FUNCTION__);

	if (regs[MGA_CTXREG_DSTORG] != dev_priv->frontOffset &&
	    regs[MGA_CTXREG_DSTORG] != dev_priv->backOffset) {
		DRM_DEBUG("BAD DSTORG: %x (front %x, back %x)\n\n",
			  regs[MGA_CTXREG_DSTORG], dev_priv->frontOffset,
			  dev_priv->backOffset);
		regs[MGA_CTXREG_DSTORG] = 0;
		return -1;
	}

	return 0;
}

/* Disallow texture reads from PCI space.
 */
static int mgaVerifyTex(drm_mga_private_t * dev_priv, int unit)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;

	DRM_DEBUG("%s\n", __FUNCTION__);

	if ((sarea_priv->TexState[unit][MGA_TEXREG_ORG] & 0x3) == 0x1) {
		DRM_DEBUG("BAD TEXREG_ORG: %x, unit %d\n",
			  sarea_priv->TexState[unit][MGA_TEXREG_ORG],
			  unit);
		sarea_priv->TexState[unit][MGA_TEXREG_ORG] = 0;
		return -1;
	}

	return 0;
}

static int mgaVerifyState(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int dirty = sarea_priv->dirty;
	int rv = 0;

	DRM_DEBUG("%s\n", __FUNCTION__);

	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;

	if (dirty & MGA_UPLOAD_CTX)
		rv |= mgaVerifyContext(dev_priv);

	if (dirty & MGA_UPLOAD_TEX0)
		rv |= mgaVerifyTex(dev_priv, 0);

	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
		if (dirty & MGA_UPLOAD_TEX1)
			rv |= mgaVerifyTex(dev_priv, 1);

		if (dirty & MGA_UPLOAD_PIPE)
			rv |= (sarea_priv->WarpPipe > MGA_MAX_G400_PIPES);
	} else {
		if (dirty & MGA_UPLOAD_PIPE)
			rv |= (sarea_priv->WarpPipe > MGA_MAX_G200_PIPES);
	}

	return rv == 0;
}

static int mgaVerifyIload(drm_mga_private_t * dev_priv,
			  unsigned long bus_address,
			  unsigned int dstOrg, int length)
{
	DRM_DEBUG("%s\n", __FUNCTION__);

	if (dstOrg < dev_priv->textureOffset ||
	    dstOrg + length >
	    (dev_priv->textureOffset + dev_priv->textureSize)) {
		return EINVAL;
	}
	if (length % 64) {
		return EINVAL;
	}
	return 0;
}

/* This copies a 64 byte aligned agp region to the frambuffer
 * with a standard blit, the ioctl needs to do checking */

static void mga_dma_dispatch_tex_blit(drm_device_t * dev,
				      unsigned long bus_address,
				      int length, unsigned int destOrg)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	int use_agp = PDEA_pagpxfer_enable | 0x00000001;
	u16 y2;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	y2 = length / 64;

	PRIM_OVERFLOW(dev, dev_priv, 30);
	PRIMGETPTR(dev_priv);

	PRIMOUTREG(MGAREG_DSTORG, destOrg);
	PRIMOUTREG(MGAREG_MACCESS, 0x00000000);
	DRM_DEBUG("srcorg : %lx\n", bus_address | use_agp);
	PRIMOUTREG(MGAREG_SRCORG, (u32) bus_address | use_agp);
	PRIMOUTREG(MGAREG_AR5, 64);

	PRIMOUTREG(MGAREG_PITCH, 64);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD);

	PRIMOUTREG(MGAREG_AR0, 63);
	PRIMOUTREG(MGAREG_AR3, 0);
	PRIMOUTREG(MGAREG_FXBNDRY, (63 << 16));
	PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC, y2);

	PRIMOUTREG(MGAREG_SRCORG, 0);
	PRIMOUTREG(MGAREG_PITCH, dev_priv->stride / dev_priv->cpp);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMADVANCE(dev_priv);
}

static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned long address = (unsigned long) buf->bus_address;
	int length = buf->used;
	int use_agp = PDEA_pagpxfer_enable;
	int i = 0;
	int primary_needed;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	DRM_DEBUG("dispatch vertex %d addr 0x%lx, "
		  "length 0x%x nbox %d dirty %x\n",
		  buf->idx, address, length,
		  sarea_priv->nbox, sarea_priv->dirty);

	DRM_DEBUG("used : %d, total : %d\n", buf->used, buf->total);

	if (buf->used) {
		/* WARNING: if you change any of the state functions verify
		 * these numbers (Overestimating this doesn't hurt).  
		 */
		buf_priv->dispatched = 1;
		primary_needed = (50 + 15 + 15 + 30 + 25 +
				  10 + 15 * MGA_NR_SAREA_CLIPRECTS);
		PRIM_OVERFLOW(dev, dev_priv, primary_needed);
		mgaEmitState(dev_priv);

		do {
			if (i < sarea_priv->nbox) {
				DRM_DEBUG("idx %d Emit box %d/%d:"
					  "%d,%d - %d,%d\n",
					  buf->idx,
					  i, sarea_priv->nbox,
					  sarea_priv->boxes[i].x1,
					  sarea_priv->boxes[i].y1,
					  sarea_priv->boxes[i].x2,
					  sarea_priv->boxes[i].y2);

				mgaEmitClipRect(dev_priv,
						&sarea_priv->boxes[i]);
			}

			PRIMGETPTR(dev_priv);
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_SECADDRESS,
				   ((u32) address) | TT_VERTEX);
			PRIMOUTREG(MGAREG_SECEND,
				   (((u32) (address + length)) | use_agp));
			PRIMADVANCE(dev_priv);
		} while (++i < sarea_priv->nbox);
	}

	if (buf_priv->discard) {
		if (buf_priv->dispatched == 1)
			AGEBUF(dev_priv, buf_priv);
		buf_priv->dispatched = 0;
		mga_freelist_put(dev, buf);
	}


}


static void mga_dma_dispatch_indices(drm_device_t * dev,
				     drm_buf_t * buf,
				     unsigned int start, unsigned int end)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int address = (unsigned int) buf->bus_address;
	int use_agp = PDEA_pagpxfer_enable;
	int i = 0;
	int primary_needed;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	DRM_DEBUG("dispatch indices %d addr 0x%x, "
		  "start 0x%x end 0x%x nbox %d dirty %x\n",
		  buf->idx, address, start, end,
		  sarea_priv->nbox, sarea_priv->dirty);

	if (start != end) {
		/* WARNING: if you change any of the state functions verify
		 * these numbers (Overestimating this doesn't hurt).  
		 */
		buf_priv->dispatched = 1;
		primary_needed = (50 + 15 + 15 + 30 + 25 +
				  10 + 15 * MGA_NR_SAREA_CLIPRECTS);
		PRIM_OVERFLOW(dev, dev_priv, primary_needed);
		mgaEmitState(dev_priv);

		do {
			if (i < sarea_priv->nbox) {
				DRM_DEBUG("idx %d Emit box %d/%d:"
					  "%d,%d - %d,%d\n",
					  buf->idx,
					  i, sarea_priv->nbox,
					  sarea_priv->boxes[i].x1,
					  sarea_priv->boxes[i].y1,
					  sarea_priv->boxes[i].x2,
					  sarea_priv->boxes[i].y2);

				mgaEmitClipRect(dev_priv,
						&sarea_priv->boxes[i]);
			}

			PRIMGETPTR(dev_priv);
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_SETUPADDRESS,
				   ((address + start) |
				    SETADD_mode_vertlist));
			PRIMOUTREG(MGAREG_SETUPEND,
				   ((address + end) | use_agp));
			PRIMADVANCE(dev_priv);
		} while (++i < sarea_priv->nbox);
	}
	if (buf_priv->discard) {
		if (buf_priv->dispatched == 1)
			AGEBUF(dev_priv, buf_priv);
		buf_priv->dispatched = 0;
		mga_freelist_put(dev, buf);
	}
}


static void mga_dma_dispatch_clear(drm_device_t * dev, int flags,
				   unsigned int clear_color,
				   unsigned int clear_zval)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->ContextState;
	int nbox = sarea_priv->nbox;
	drm_clip_rect_t *pbox = sarea_priv->boxes;
	unsigned int cmd;
	int i;
	int primary_needed;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	if (dev_priv->sgram)
		cmd = MGA_CLEAR_CMD | DC_atype_blk;
	else
		cmd = MGA_CLEAR_CMD | DC_atype_rstr;

	primary_needed = nbox * 70;
	if (primary_needed == 0)
		primary_needed = 70;
	PRIM_OVERFLOW(dev, dev_priv, primary_needed);
	PRIMGETPTR(dev_priv);

	for (i = 0; i < nbox; i++) {
		unsigned int height = pbox[i].y2 - pbox[i].y1;

		DRM_DEBUG("dispatch clear %d,%d-%d,%d flags %x!\n",
			  pbox[i].x1, pbox[i].y1, pbox[i].x2,
			  pbox[i].y2, flags);

		if (flags & MGA_FRONT) {
			DRM_DEBUG("clear front\n");
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_YDSTLEN,
				   (pbox[i].y1 << 16) | height);
			PRIMOUTREG(MGAREG_FXBNDRY,
				   (pbox[i].x2 << 16) | pbox[i].x1);

			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_FCOL, clear_color);
			PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset);
			PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd);
		}

		if (flags & MGA_BACK) {
			DRM_DEBUG("clear back\n");
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_YDSTLEN,
				   (pbox[i].y1 << 16) | height);
			PRIMOUTREG(MGAREG_FXBNDRY,
				   (pbox[i].x2 << 16) | pbox[i].x1);

			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_FCOL, clear_color);
			PRIMOUTREG(MGAREG_DSTORG, dev_priv->backOffset);
			PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd);
		}

		if (flags & MGA_DEPTH) {
			DRM_DEBUG("clear depth\n");
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_YDSTLEN,
				   (pbox[i].y1 << 16) | height);
			PRIMOUTREG(MGAREG_FXBNDRY,
				   (pbox[i].x2 << 16) | pbox[i].x1);

			PRIMOUTREG(MGAREG_DMAPAD, 0);
			PRIMOUTREG(MGAREG_FCOL, clear_zval);
			PRIMOUTREG(MGAREG_DSTORG, dev_priv->depthOffset);
			PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd);
		}
	}

	/* Force reset of DWGCTL */
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
	PRIMADVANCE(dev_priv);
}

static void mga_dma_dispatch_swap(drm_device_t * dev)
{
	drm_mga_private_t *dev_priv = dev->dev_private;
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->ContextState;
	int nbox = sarea_priv->nbox;
	drm_clip_rect_t *pbox = sarea_priv->boxes;
	int i;
	int primary_needed;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	primary_needed = nbox * 5;
	primary_needed += 60;
	PRIM_OVERFLOW(dev, dev_priv, primary_needed);
	PRIMGETPTR(dev_priv);

	PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset);
	PRIMOUTREG(MGAREG_MACCESS, dev_priv->mAccess);
	PRIMOUTREG(MGAREG_SRCORG, dev_priv->backOffset);
	PRIMOUTREG(MGAREG_AR5, dev_priv->stride / 2);

	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD);

	for (i = 0; i < nbox; i++) {
		unsigned int h = pbox[i].y2 - pbox[i].y1;
		unsigned int start = pbox[i].y1 * dev_priv->stride / 2;

		DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
			  pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2);

		PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1);
		PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1);
		PRIMOUTREG(MGAREG_FXBNDRY,
			   pbox[i].x1 | ((pbox[i].x2 - 1) << 16));
		PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC,
			   (pbox[i].y1 << 16) | h);
	}

	/* Force reset of DWGCTL */
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_SRCORG, 0);
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);

	PRIMADVANCE(dev_priv);
}

int mga_clear_bufs(dev_t kdev, u_long cmd, caddr_t data,
		   int flags, struct proc *p)
{
	drm_device_t *dev = kdev->si_drv1;
	drm_mga_private_t *dev_priv =
	    (drm_mga_private_t *) dev->dev_private;
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	drm_mga_clear_t clear;
	int s;

	clear = *(drm_mga_clear_t *) data;
	DRM_DEBUG("%s\n", __FUNCTION__);

	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
		DRM_ERROR("mga_clear_bufs called without lock held\n");
		return EINVAL;
	}

	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;

	/* Make sure we restore the 3D state next time.
	 */
	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
	mga_dma_dispatch_clear(dev, clear.flags,
			       clear.clear_color, clear.clear_depth);
	PRIMUPDATE(dev_priv);
	mga_flush_write_combine();
	s = splsofttq();
	mga_dma_schedule(dev, 1);
	splx(s);
	return 0;
}

int mga_swap_bufs(dev_t kdev, u_long cmd, caddr_t data,
		  int flags, struct proc *p)
{
	drm_device_t *dev = kdev->si_drv1;
	drm_mga_private_t *dev_priv =
	    (drm_mga_private_t *) dev->dev_private;
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	int s;

	DRM_DEBUG("%s\n", __FUNCTION__);

	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
		DRM_ERROR("mga_swap_bufs called without lock held\n");
		return EINVAL;
	}

	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;

	/* Make sure we restore the 3D state next time.
	 */
	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
	mga_dma_dispatch_swap(dev);
	PRIMUPDATE(dev_priv);
	set_bit(MGA_BUF_SWAP_PENDING,
		&dev_priv->current_prim->buffer_status);
	mga_flush_write_combine();
	s = splsofttq();
	mga_dma_schedule(dev, 1);
	splx(s);
	return 0;
}

int mga_iload(dev_t kdev, u_long cmd, caddr_t data,
	      int flags, struct proc *p)
{
	drm_device_t *dev = kdev->si_drv1;
	drm_device_dma_t *dma = dev->dma;
	drm_mga_private_t *dev_priv =
	    (drm_mga_private_t *) dev->dev_private;
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	drm_buf_t *buf;
	drm_mga_buf_priv_t *buf_priv;
	drm_mga_iload_t iload;
	unsigned long bus_address;
	int s;

	DRM_DEBUG("%s\n", __FUNCTION__);

	DRM_DEBUG("Starting Iload\n");
	iload = *(drm_mga_iload_t *) data;

	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
		DRM_ERROR("mga_iload called without lock held\n");
		return EINVAL;
	}

	buf = dma->buflist[iload.idx];
	buf_priv = buf->dev_private;
	bus_address = buf->bus_address;
	DRM_DEBUG("bus_address %lx, length %d, destorg : %x\n",
		  bus_address, iload.length, iload.destOrg);

	if (mgaVerifyIload(dev_priv,
			   bus_address, iload.destOrg, iload.length)) {
		mga_freelist_put(dev, buf);
		return EINVAL;
	}

	sarea_priv->dirty |= MGA_UPLOAD_CTX;

	mga_dma_dispatch_tex_blit(dev, bus_address, iload.length,
				  iload.destOrg);
	AGEBUF(dev_priv, buf_priv);
	buf_priv->discard = 1;
	mga_freelist_put(dev, buf);
	mga_flush_write_combine();
	s = splsofttq();
	mga_dma_schedule(dev, 1);
	splx(s);
	return 0;
}

int mga_vertex(dev_t kdev, u_long cmd, caddr_t data,
	       int flags, struct proc *p)
{
	drm_device_t *dev = kdev->si_drv1;
	drm_mga_private_t *dev_priv =
	    (drm_mga_private_t *) dev->dev_private;
	drm_device_dma_t *dma = dev->dma;
	drm_buf_t *buf;
	drm_mga_buf_priv_t *buf_priv;
	drm_mga_vertex_t vertex;

	DRM_DEBUG("%s\n", __FUNCTION__);

	vertex = *(drm_mga_vertex_t *) data;

	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
		DRM_ERROR("mga_vertex called without lock held\n");
		return EINVAL;
	}

	DRM_DEBUG("mga_vertex\n");

	buf = dma->buflist[vertex.idx];
	buf_priv = buf->dev_private;

	buf->used = vertex.used;
	buf_priv->discard = vertex.discard;

	if (!mgaVerifyState(dev_priv)) {
		if (vertex.discard) {
			if (buf_priv->dispatched == 1)
				AGEBUF(dev_priv, buf_priv);
			buf_priv->dispatched = 0;
			mga_freelist_put(dev, buf);
		}
		DRM_DEBUG("bad state\n");
		return EINVAL;
	}

	mga_dma_dispatch_vertex(dev, buf);

	PRIMUPDATE(dev_priv);
	mga_flush_write_combine();
	mga_dma_schedule(dev, 1);
	return 0;
}


int mga_indices(dev_t kdev, u_long cmd, caddr_t data,
		int flags, struct proc *p)
{
	drm_device_t *dev = kdev->si_drv1;
	drm_mga_private_t *dev_priv =
	    (drm_mga_private_t *) dev->dev_private;
	drm_device_dma_t *dma = dev->dma;
	drm_buf_t *buf;
	drm_mga_buf_priv_t *buf_priv;
	drm_mga_indices_t indices;
	DRM_DEBUG("%s\n", __FUNCTION__);

	indices = *(drm_mga_indices_t *) data;

	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
		DRM_ERROR("mga_indices called without lock held\n");
		return EINVAL;
	}

	DRM_DEBUG("mga_indices\n");

	buf = dma->buflist[indices.idx];
	buf_priv = buf->dev_private;

	buf_priv->discard = indices.discard;

	if (!mgaVerifyState(dev_priv)) {
		if (indices.discard) {
			if (buf_priv->dispatched == 1)
				AGEBUF(dev_priv, buf_priv);
			buf_priv->dispatched = 0;
			mga_freelist_put(dev, buf);
		}
		return EINVAL;
	}

	mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);

	PRIMUPDATE(dev_priv);
	mga_flush_write_combine();
	mga_dma_schedule(dev, 1);
	return 0;
}



static int
mga_dma_get_buffers(drm_device_t * dev, drm_dma_t * d, struct proc *p)
{
	int i, error;
	drm_buf_t *buf;
	DRM_DEBUG("%s\n", __FUNCTION__);

	for (i = d->granted_count; i < d->request_count; i++) {
		buf = mga_freelist_get(dev);
		if (!buf)
			break;
		buf->pid = p->p_pid;
		error = copyout(&buf->idx,
				&d->request_indices[i],
				sizeof(buf->idx));
		if (error) return error;
		error = copyout(&buf->total,
				&d->request_sizes[i],
				sizeof(buf->total));
		if (error) return error;
		++d->granted_count;
	}
	return 0;
}

int mga_dma(dev_t kdev, u_long cmd, caddr_t data,
	    int flags, struct proc *p)
{
	drm_device_t *dev = kdev->si_drv1;
	drm_device_dma_t *dma = dev->dma;
	int retcode = 0;
	drm_dma_t d;
	DRM_DEBUG("%s\n", __FUNCTION__);

	d = *(drm_dma_t *) data;
	DRM_DEBUG("%d %d: %d send, %d req\n",
		  p->p_pid, d.context, d.send_count, d.request_count);

	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
		DRM_ERROR("mga_dma called without lock held\n");
		return EINVAL;
	}

	/* Please don't send us buffers.
	 */
	if (d.send_count != 0) {
		DRM_ERROR
		    ("Process %d trying to send %d buffers via drmDMA\n",
		     p->p_pid, d.send_count);
		return EINVAL;
	}

	/* We'll send you buffers.
	 */
	if (d.request_count < 0 || d.request_count > dma->buf_count) {
		DRM_ERROR
		    ("Process %d trying to get %d buffers (of %d max)\n",
		     p->p_pid, d.request_count, dma->buf_count);
		return EINVAL;
	}

	d.granted_count = 0;

	if (d.request_count) {
		retcode = mga_dma_get_buffers(dev, &d, p);
	}

	DRM_DEBUG("%d returning, granted = %d\n",
		  p->p_pid, d.granted_count);
	*(drm_dma_t *) data = d;
	return retcode;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-25 00:00:08 +0000