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path: root/bsd/drm_ioctl.h
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/* drm_ioctl.h -- IOCTL processing for DRM -*- linux-c -*-
 * Created: Fri Jan  8 09:01:26 1999 by faith@valinux.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Rickard E. (Rik) Faith <faith@valinux.com>
 *    Gareth Hughes <gareth@valinux.com>
 */

#include "drmP.h"

int DRM(irq_busid)( DRM_IOCTL_ARGS )
{
#ifdef __FreeBSD__
	drm_irq_busid_t id;
	devclass_t pci;
	device_t bus, dev;
	device_t *kids;
	int error, i, num_kids;

	DRM_COPY_FROM_USER_IOCTL( id, (drm_irq_busid_t *)data, sizeof(id) );

	pci = devclass_find("pci");
	if (!pci)
		return ENOENT;
	bus = devclass_get_device(pci, id.busnum);
	if (!bus)
		return ENOENT;
	error = device_get_children(bus, &kids, &num_kids);
	if (error)
		return error;

	dev = 0;
	for (i = 0; i < num_kids; i++) {
		dev = kids[i];
		if (pci_get_slot(dev) == id.devnum
		    && pci_get_function(dev) == id.funcnum)
			break;
	}

	free(kids, M_TEMP);

	if (i != num_kids)
		id.irq = pci_get_irq(dev);
	else
		id.irq = 0;
	DRM_DEBUG("%d:%d:%d => IRQ %d\n",
		  id.busnum, id.devnum, id.funcnum, id.irq);
	
	DRM_COPY_TO_USER_IOCTL( (drm_irq_busid_t *)data, id, sizeof(id) );

	return 0;
#else
	/* don't support interrupt-driven drivers on Net yet */
	return ENOENT;
#endif
}

int DRM(getunique)( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_unique_t	 u;

	DRM_COPY_FROM_USER_IOCTL( u, (drm_unique_t *)data, sizeof(u) );

	if (u.unique_len >= dev->unique_len) {
		if (DRM_COPY_TO_USER(u.unique, dev->unique, dev->unique_len))
			return DRM_ERR(EFAULT);
	}
	u.unique_len = dev->unique_len;

	DRM_COPY_TO_USER_IOCTL( (drm_unique_t *)data, u, sizeof(u) );

	return 0;
}

int DRM(setunique)( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_unique_t	 u;

	if (dev->unique_len || dev->unique)
		return DRM_ERR(EBUSY);

	DRM_COPY_FROM_USER_IOCTL( u, (drm_unique_t *)data, sizeof(u) );

	if (!u.unique_len || u.unique_len > 1024)
		return DRM_ERR(EINVAL);

	dev->unique_len = u.unique_len;
	dev->unique	= DRM(alloc)(u.unique_len + 1, DRM_MEM_DRIVER);

	if(!dev->unique) return DRM_ERR(ENOMEM);

	if (DRM_COPY_FROM_USER(dev->unique, u.unique, dev->unique_len))
		return DRM_ERR(EFAULT);

	dev->unique[dev->unique_len] = '\0';

	dev->devname = DRM(alloc)(strlen(dev->name) + strlen(dev->unique) + 2,
				  DRM_MEM_DRIVER);
	if(!dev->devname) {
		DRM(free)(dev->devname, sizeof(*dev->devname), DRM_MEM_DRIVER);
		return DRM_ERR(ENOMEM);
	}
	sprintf(dev->devname, "%s@%s", dev->name, dev->unique);


	return 0;
}


int DRM(getmap)( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_map_t    map;
	drm_map_t    *mapinlist;
	drm_map_list_entry_t *list;
	int          idx;
	int	     i = 0;

	DRM_COPY_FROM_USER_IOCTL( map, (drm_map_t *)data, sizeof(map) );

	idx = map.offset;

	DRM_LOCK;
	if (idx < 0 || idx >= dev->map_count) {
		DRM_UNLOCK;
		return DRM_ERR(EINVAL);
	}

	TAILQ_FOREACH(list, dev->maplist, link) {
		mapinlist = list->map;
		if (i==idx) {
			map.offset = mapinlist->offset;
			map.size   = mapinlist->size;
			map.type   = mapinlist->type;
			map.flags  = mapinlist->flags;
			map.handle = mapinlist->handle;
			map.mtrr   = mapinlist->mtrr;
			break;
		}
		i++;
	}

	DRM_UNLOCK;

 	if (!list)
		return EINVAL;

	DRM_COPY_TO_USER_IOCTL( (drm_map_t *)data, map, sizeof(map) );

	return 0;
}

int DRM(getclient)( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_client_t client;
	drm_file_t   *pt;
	int          idx;
	int          i = 0;

	DRM_COPY_FROM_USER_IOCTL( client, (drm_client_t *)data, sizeof(client) );

	idx = client.idx;
	DRM_LOCK;
	TAILQ_FOREACH(pt, &dev->files, link) {
		if (i==idx)
		{
			client.auth  = pt->authenticated;
			client.pid   = pt->pid;
			client.uid   = pt->uid;
			client.magic = pt->magic;
			client.iocs  = pt->ioctl_count;
			DRM_UNLOCK;

			*(drm_client_t *)data = client;
			return 0;
		}
		i++;
	}
	DRM_UNLOCK;

	DRM_COPY_TO_USER_IOCTL( (drm_client_t *)data, client, sizeof(client) );

	return 0;
}

int DRM(getstats)( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_stats_t  stats;
	int          i;

	memset(&stats, 0, sizeof(stats));
	
	DRM_LOCK;

	for (i = 0; i < dev->counters; i++) {
		if (dev->types[i] == _DRM_STAT_LOCK)
			stats.data[i].value
				= (dev->lock.hw_lock
				   ? dev->lock.hw_lock->lock : 0);
		else 
			stats.data[i].value = atomic_read(&dev->counts[i]);
		stats.data[i].type  = dev->types[i];
	}
	
	stats.count = dev->counters;

	DRM_UNLOCK;

	DRM_COPY_TO_USER_IOCTL( (drm_stats_t *)data, stats, sizeof(stats) );

	return 0;
}
ss="hl opt">( DRM_IOCTL_ARGS ); extern int mga_dma_indices( DRM_IOCTL_ARGS ); extern int mga_dma_iload( DRM_IOCTL_ARGS ); extern int mga_dma_blit( DRM_IOCTL_ARGS ); extern int mga_getparam( DRM_IOCTL_ARGS ); /* mga_warp.c */ extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); extern int mga_warp_init( drm_mga_private_t *dev_priv ); extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ); extern void mga_driver_irq_preinstall( drm_device_t *dev ); extern void mga_driver_irq_postinstall( drm_device_t *dev ); extern void mga_driver_irq_uninstall( drm_device_t *dev ); #define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() #if defined(__linux__) && defined(__alpha__) #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) static inline u32 _MGA_READ(u32 *addr) { DRM_MEMORYBARRIER(); return *(volatile u32 *)addr; } #else #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) #endif #define DWGREG0 0x1c00 #define DWGREG0_END 0x1dff #define DWGREG1 0x2c00 #define DWGREG1_END 0x2dff #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) #define DMAREG0(r) (u8)((r - DWGREG0) >> 2) #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) /* ================================================================ * Helper macross... */ #define MGA_EMIT_STATE( dev_priv, dirty ) \ do { \ if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \ mga_g400_emit_state( dev_priv ); \ } else { \ mga_g200_emit_state( dev_priv ); \ } \ } \ } while (0) #define WRAP_TEST_WITH_RETURN( dev_priv ) \ do { \ if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ if ( mga_is_idle( dev_priv ) ) { \ mga_do_dma_wrap_end( dev_priv ); \ } else if ( dev_priv->prim.space < \ dev_priv->prim.high_mark ) { \ if ( MGA_DMA_DEBUG ) \ DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ return DRM_ERR(EBUSY); \ } \ } \ } while (0) #define WRAP_WAIT_WITH_RETURN( dev_priv ) \ do { \ if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ if ( MGA_DMA_DEBUG ) \ DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ return DRM_ERR(EBUSY); \ } \ mga_do_dma_wrap_end( dev_priv ); \ } \ } while (0) /* ================================================================ * Primary DMA command stream */ #define MGA_VERBOSE 0 #define DMA_LOCALS unsigned int write; volatile u8 *prim; #define DMA_BLOCK_SIZE (5 * sizeof(u32)) #define BEGIN_DMA( n ) \ do { \ if ( MGA_VERBOSE ) { \ DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ (n), __FUNCTION__ ); \ DRM_INFO( " space=0x%x req=0x%Zx\n", \ dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ } \ prim = dev_priv->prim.start; \ write = dev_priv->prim.tail; \ } while (0) #define BEGIN_DMA_WRAP() \ do { \ if ( MGA_VERBOSE ) { \ DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ } \ prim = dev_priv->prim.start; \ write = dev_priv->prim.tail; \ } while (0) #define ADVANCE_DMA() \ do { \ dev_priv->prim.tail = write; \ if ( MGA_VERBOSE ) { \ DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ write, dev_priv->prim.space ); \ } \ } while (0) #define FLUSH_DMA() \ do { \ if ( 0 ) { \ DRM_INFO( "%s:\n", __FUNCTION__ ); \ DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ dev_priv->prim.tail, \ MGA_READ( MGA_PRIMADDRESS ) - \ dev_priv->primary->offset ); \ } \ if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ if ( dev_priv->prim.space < \ dev_priv->prim.high_mark ) { \ mga_do_dma_wrap_start( dev_priv ); \ } else { \ mga_do_dma_flush( dev_priv ); \ } \ } \ } while (0) /* Never use this, always use DMA_BLOCK(...) for primary DMA output. */ #define DMA_WRITE( offset, val ) \ do { \ if ( MGA_VERBOSE ) { \ DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ (u32)(val), write + (offset) * sizeof(u32) ); \ } \ *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ } while (0) #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ do { \ DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ (DMAREG( reg1 ) << 8) | \ (DMAREG( reg2 ) << 16) | \ (DMAREG( reg3 ) << 24)) ); \ DMA_WRITE( 1, val0 ); \ DMA_WRITE( 2, val1 ); \ DMA_WRITE( 3, val2 ); \ DMA_WRITE( 4, val3 ); \ write += DMA_BLOCK_SIZE; \ } while (0) /* Buffer aging via primary DMA stream head pointer. */ #define SET_AGE( age, h, w ) \ do { \ (age)->head = h; \ (age)->wrap = w; \ } while (0) #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ ( (age)->wrap == w && \ (age)->head < h ) ) #define AGE_BUFFER( buf_priv ) \ do { \ drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ if ( (buf_priv)->dispatched ) { \ entry->age.head = (dev_priv->prim.tail + \ dev_priv->primary->offset); \ entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ } else { \ entry->age.head = 0; \ entry->age.wrap = 0; \ } \ } while (0) #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ MGA_DWGENGSTS | \ MGA_ENDPRDMASTS) #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ MGA_ENDPRDMASTS) #define MGA_DMA_DEBUG 0 /* A reduced set of the mga registers. */ #define MGA_CRTC_INDEX 0x1fd4 #define MGA_CRTC_DATA 0x1fd5 /* CRTC11 */ #define MGA_VINTCLR (1 << 4) #define MGA_VINTEN (1 << 5) #define MGA_ALPHACTRL 0x2c7c #define MGA_AR0 0x1c60 #define MGA_AR1 0x1c64 #define MGA_AR2 0x1c68 #define MGA_AR3 0x1c6c #define MGA_AR4 0x1c70 #define MGA_AR5 0x1c74 #define MGA_AR6 0x1c78 #define MGA_CXBNDRY 0x1c80 #define MGA_CXLEFT 0x1ca0 #define MGA_CXRIGHT 0x1ca4 #define MGA_DMAPAD 0x1c54 #define MGA_DSTORG 0x2cb8 #define MGA_DWGCTL 0x1c00 # define MGA_OPCOD_MASK (15 << 0) # define MGA_OPCOD_TRAP (4 << 0) # define MGA_OPCOD_TEXTURE_TRAP (6 << 0) # define MGA_OPCOD_BITBLT (8 << 0) # define MGA_OPCOD_ILOAD (9 << 0) # define MGA_ATYPE_MASK (7 << 4) # define MGA_ATYPE_RPL (0 << 4) # define MGA_ATYPE_RSTR (1 << 4) # define MGA_ATYPE_ZI (3 << 4) # define MGA_ATYPE_BLK (4 << 4) # define MGA_ATYPE_I (7 << 4) # define MGA_LINEAR (1 << 7) # define MGA_ZMODE_MASK (7 << 8) # define MGA_ZMODE_NOZCMP (0 << 8) # define MGA_ZMODE_ZE (2 << 8) # define MGA_ZMODE_ZNE (3 << 8) # define MGA_ZMODE_ZLT (4 << 8) # define MGA_ZMODE_ZLTE (5 << 8) # define MGA_ZMODE_ZGT (6 << 8) # define MGA_ZMODE_ZGTE (7 << 8) # define MGA_SOLID (1 << 11) # define MGA_ARZERO (1 << 12) # define MGA_SGNZERO (1 << 13) # define MGA_SHIFTZERO (1 << 14) # define MGA_BOP_MASK (15 << 16) # define MGA_BOP_ZERO (0 << 16) # define MGA_BOP_DST (10 << 16) # define MGA_BOP_SRC (12 << 16) # define MGA_BOP_ONE (15 << 16) # define MGA_TRANS_SHIFT 20 # define MGA_TRANS_MASK (15 << 20) # define MGA_BLTMOD_MASK (15 << 25) # define MGA_BLTMOD_BMONOLEF (0 << 25) # define MGA_BLTMOD_BMONOWF (4 << 25) # define MGA_BLTMOD_PLAN (1 << 25) # define MGA_BLTMOD_BFCOL (2 << 25) # define MGA_BLTMOD_BU32BGR (3 << 25) # define MGA_BLTMOD_BU32RGB (7 << 25) # define MGA_BLTMOD_BU24BGR (11 << 25) # define MGA_BLTMOD_BU24RGB (15 << 25) # define MGA_PATTERN (1 << 29) # define MGA_TRANSC (1 << 30) # define MGA_CLIPDIS (1 << 31) #define MGA_DWGSYNC 0x2c4c #define MGA_FCOL 0x1c24 #define MGA_FIFOSTATUS 0x1e10 #define MGA_FOGCOL 0x1cf4 #define MGA_FXBNDRY 0x1c84 #define MGA_FXLEFT 0x1ca8 #define MGA_FXRIGHT 0x1cac #define MGA_ICLEAR 0x1e18 # define MGA_SOFTRAPICLR (1 << 0) # define MGA_VLINEICLR (1 << 5) #define MGA_IEN 0x1e1c # define MGA_SOFTRAPIEN (1 << 0) # define MGA_VLINEIEN (1 << 5) #define MGA_LEN 0x1c5c #define MGA_MACCESS 0x1c04 #define MGA_PITCH 0x1c8c #define MGA_PLNWT 0x1c1c #define MGA_PRIMADDRESS 0x1e58 # define MGA_DMA_GENERAL (0 << 0) # define MGA_DMA_BLIT (1 << 0) # define MGA_DMA_VECTOR (2 << 0) # define MGA_DMA_VERTEX (3 << 0) #define MGA_PRIMEND 0x1e5c # define MGA_PRIMNOSTART (1 << 0) # define MGA_PAGPXFER (1 << 1) #define MGA_PRIMPTR 0x1e50 # define MGA_PRIMPTREN0 (1 << 0) # define MGA_PRIMPTREN1 (1 << 1) #define MGA_RST 0x1e40 # define MGA_SOFTRESET (1 << 0) # define MGA_SOFTEXTRST (1 << 1) #define MGA_SECADDRESS 0x2c40 #define MGA_SECEND 0x2c44 #define MGA_SETUPADDRESS 0x2cd0 #define MGA_SETUPEND 0x2cd4 #define MGA_SGN 0x1c58 #define MGA_SOFTRAP 0x2c48 #define MGA_SRCORG 0x2cb4 # define MGA_SRMMAP_MASK (1 << 0) # define MGA_SRCMAP_FB (0 << 0) # define MGA_SRCMAP_SYSMEM (1 << 0) # define MGA_SRCACC_MASK (1 << 1) # define MGA_SRCACC_PCI (0 << 1) # define MGA_SRCACC_AGP (1 << 1) #define MGA_STATUS 0x1e14 # define MGA_SOFTRAPEN (1 << 0) # define MGA_VSYNCPEN (1 << 4) # define MGA_VLINEPEN (1 << 5) # define MGA_DWGENGSTS (1 << 16) # define MGA_ENDPRDMASTS (1 << 17) #define MGA_STENCIL 0x2cc8 #define MGA_STENCILCTL 0x2ccc #define MGA_TDUALSTAGE0 0x2cf8 #define MGA_TDUALSTAGE1 0x2cfc #define MGA_TEXBORDERCOL 0x2c5c #define MGA_TEXCTL 0x2c30 #define MGA_TEXCTL2 0x2c3c # define MGA_DUALTEX (1 << 7) # define MGA_G400_TC2_MAGIC (1 << 15) # define MGA_MAP1_ENABLE (1 << 31) #define MGA_TEXFILTER 0x2c58 #define MGA_TEXHEIGHT 0x2c2c #define MGA_TEXORG 0x2c24 # define MGA_TEXORGMAP_MASK (1 << 0) # define MGA_TEXORGMAP_FB (0 << 0) # define MGA_TEXORGMAP_SYSMEM (1 << 0) # define MGA_TEXORGACC_MASK (1 << 1) # define MGA_TEXORGACC_PCI (0 << 1) # define MGA_TEXORGACC_AGP (1 << 1) #define MGA_TEXORG1 0x2ca4 #define MGA_TEXORG2 0x2ca8 #define MGA_TEXORG3 0x2cac #define MGA_TEXORG4 0x2cb0 #define MGA_TEXTRANS 0x2c34 #define MGA_TEXTRANSHIGH 0x2c38 #define MGA_TEXWIDTH 0x2c28