/* * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sub license, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef _VIA_DRM_H_ #define _VIA_DRM_H_ /* WARNING: These defines must be the same as what the Xserver uses. * if you change them, you must change the defines in the Xserver. */ #ifndef _VIA_DEFINES_ #define _VIA_DEFINES_ #define VIA_DMA_BUF_ORDER 12 #define VIA_DMA_BUF_SZ (1 << VIA_DMA_BUF_ORDER) #define VIA_DMA_BUF_NR 256 #define VIA_NR_SAREA_CLIPRECTS 8 #define VIA_NR_XVMC_PORTS 10 #define VIA_NR_XVMC_LOCKS 5 #define VIA_MAX_CACHELINE_SIZE 64 #define XVMCLOCKPTR(saPriv,lockNo) \ ((volatile int *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ (VIA_MAX_CACHELINE_SIZE - 1)) & \ ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ VIA_MAX_CACHELINE_SIZE*(lockNo))) /* Each region is a minimum of 64k, and there are at most 64 of them. */ #define VIA_NR_TEX_REGIONS 64 #define VIA_LOG_MIN_TEX_REGION_SIZE 16 #endif #define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ #define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ #define VIA_UPLOAD_CTX 0x4 #define VIA_UPLOAD_BUFFERS 0x8 #define VIA_UPLOAD_TEX0 0x10 #define VIA_UPLOAD_TEX1 0x20 #define VIA_UPLOAD_CLIPRECTS 0x40 #define VIA_UPLOAD_ALL 0xff /* VIA specific ioctls */ #define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(0x40, drm_via_mem_t) #define DRM_IOCTL_VIA_FREEMEM DRM_IOW(0x41, drm_via_mem_t) #define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(0x42, drm_via_agp_t) #define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(0x43, drm_via_fb_t) #define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(0x44, drm_via_init_t) #define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW(0x45, drm_via_futex_t) #define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(0x47, drm_via_dma_init_t) #define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW(0x48, drm_via_cmdbuffer_t) #define DRM_IOCTL_VIA_FLUSH DRM_IO(0x49) #define DRM_IOCTL_VIA_PCICMD DRM_IOW(0x4A, drm_via_cmdbuffer_t) /* Indices into buf.Setup where various bits of state are mirrored per * context and per buffer. These can be fired at the card as a unit, * or in a piecewise fashion as required. */ #define VIA_TEX_SETUP_SIZE 8 /* Flags for clear ioctl */ #define VIA_FRONT 0x1 #define VIA_BACK 0x2 #define VIA_DEPTH 0x4 #define VIA_STENCIL 0x8 #define VIDEO 0 #define AGP 1 typedef struct { unsigned long offset; unsigned long size; } drm_via_agp_t; typedef struct { unsigned long offset; unsigned long size; } drm_via_fb_t; typedef struct { uint32_t context; uint32_t type; unsigned long size; unsigned long index; unsigned long offset; } drm_via_mem_t; typedef struct _drm_via_init { enum { VIA_INIT_MAP = 0x01, VIA_CLEANUP_MAP = 0x02 } func; unsigned long sarea_priv_offset; unsigned long fb_offset; unsigned long mmio_offset; unsigned long agpAddr; } drm_via_init_t; typedef struct _drm_via_futex { enum { VIA_FUTEX_WAIT = 0x00, VIA_FUTEX_WAKE = 0X01 } func; uint32_t ms; uint32_t lock; uint32_t val; } drm_via_futex_t; typedef struct _drm_via_dma_init { enum { VIA_INIT_DMA = 0x01, VIA_CLEANUP_DMA = 0x02, VIA_DMA_INITIALIZED = 0x03 } func; unsigned long offset; unsigned long size; unsigned long reg_pause_addr; } drm_via_dma_init_t; typedef struct _drm_via_cmdbuffer { char *buf; unsigned long size; } drm_via_cmdbuffer_t; /* Warning: If you change the SAREA structure you must change the Xserver * structure as well */ typedef struct _drm_via_tex_region { unsigned char next, prev; /* indices to form a circular LRU */ unsigned char inUse; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_via_tex_region_t; typedef struct _drm_via_sarea { unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS]; drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; int texAge; /* last time texture was uploaded */ int ctxOwner; /* last context to upload state */ int vertexPrim; /* * Below is for XvMC. * We want the lock integers alone on, and aligned to, a cache line. * Therefore this somewhat strange construct. */ char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */ } drm_via_sarea_t; typedef struct _drm_via_flush_agp { unsigned int offset; unsigned int size; unsigned int index; int discard; /* client is finished with the buffer? */ } drm_via_flush_agp_t; typedef struct _drm_via_flush_sys { unsigned int offset; unsigned int size; unsigned long index; int discard; /* client is finished with the buffer? */ } drm_via_flush_sys_t; #ifdef __KERNEL__ int via_fb_init(DRM_IOCTL_ARGS); int via_mem_alloc(DRM_IOCTL_ARGS); int via_mem_free(DRM_IOCTL_ARGS); int via_agp_init(DRM_IOCTL_ARGS); int via_map_init(DRM_IOCTL_ARGS); int via_decoder_futex(DRM_IOCTL_ARGS); int via_dma_init(DRM_IOCTL_ARGS); int via_cmdbuffer(DRM_IOCTL_ARGS); int via_flush_ioctl(DRM_IOCTL_ARGS); int via_pci_cmdbuffer(DRM_IOCTL_ARGS); #endif #endif /* _VIA_DRM_H_ */ ef='#n105'>105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 
/*
 * Copyright 2008 Jérôme Glisse
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
#include "radeon_ms.h"
#include "amd.h"

#define RADEON_DST_Y_X                      0x1438
#define RADEON_SRC_Y_X                      0x1434
#define RADEON_DP_CNTL                      0x16c0
#define RADEON_DP_GUI_MASTER_CNTL           0x146c
#define RADEON_DP_BRUSH_BKGD_CLR            0x1478
#define RADEON_DP_BRUSH_FRGD_CLR            0x147c
#define RADEON_DP_WRITE_MASK                0x16cc
#define RADEON_DST_PITCH_OFFSET             0x142c
#define RADEON_SRC_PITCH_OFFSET             0x1428
#define RADEON_DST_HEIGHT_WIDTH             0x143c

struct legacy_check
{
	/* for 2D operations */
	uint32_t                dp_gui_master_cntl;
	uint32_t                dst_offset;
	uint32_t                dst_pitch;
	struct amd_cmd_bo       *dst;
	uint32_t                dst_x;
	uint32_t                dst_y;
	uint32_t                dst_h;
	uint32_t                dst_w;
	struct amd_cmd_bo       *src;
	uint32_t                src_pitch;
	uint32_t                src_x;
	uint32_t                src_y;
};

static int check_blit(struct drm_device *dev, struct amd_cmd *cmd)
{
	struct legacy_check *legacy_check;
	long bpp, start, end;
	
	legacy_check = (struct legacy_check *)cmd->driver;
	/* check that gui master cntl have been set */
	if (legacy_check->dp_gui_master_cntl == 0xffffffff) {
		return -EINVAL;
	}
	switch ((legacy_check->dp_gui_master_cntl >> 8) & 0xf) {
	case 2:
		bpp = 1;