/* mach64_drv.h -- Private header for mach64 driver -*- linux-c -*- * Created: Fri Nov 24 22:07:58 2000 by gareth@valinux.com * * Copyright 2000 Gareth Hughes * Copyright 2002 Frank C. Earl * Copyright 2002-2003 Leif Delgass * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Gareth Hughes * Frank C. Earl * Leif Delgass * José Fonseca */ #ifndef __MACH64_DRV_H__ #define __MACH64_DRV_H__ /* FIXME: remove these when not needed */ /* Development driver options */ #define MACH64_EXTRA_CHECKING 0 /* Extra sanity checks for DMA/freelist management */ #define MACH64_VERBOSE 0 /* Verbose debugging output */ typedef struct drm_mach64_freelist { struct list_head list; /* List pointers for free_list, placeholders, or pending list */ drm_buf_t *buf; /* Pointer to the buffer */ int discard; /* This flag is set when we're done (re)using a buffer */ u32 ring_ofs; /* dword offset in ring of last descriptor for this buffer */ } drm_mach64_freelist_t; typedef struct drm_mach64_descriptor_ring { dma_addr_t handle; /* handle (bus address) of ring returned by pci_alloc_consistent() */ void *start; /* write pointer (cpu address) to start of descriptor ring */ u32 start_addr; /* bus address of beginning of descriptor ring */ int size; /* size of ring in bytes */ u32 head_addr; /* bus address of descriptor ring head */ u32 head; /* dword offset of descriptor ring head */ u32 tail; /* dword offset of descriptor ring tail */ u32 tail_mask; /* mask used to wrap ring */ int space; /* number of free bytes in ring */ } drm_mach64_descriptor_ring_t; typedef struct drm_mach64_private { drm_mach64_sarea_t *sarea_priv; int is_pci; drm_mach64_dma_mode_t driver_mode; /* Async DMA, sync DMA, or MMIO */ int usec_timeout; /* Timeout for the wait functions */ drm_mach64_descriptor_ring_t ring; /* DMA descriptor table (ring buffer) */ int ring_running; /* Is bus mastering is enabled */ struct list_head free_list; /* Free-list head */ struct list_head placeholders; /* Placeholder list for buffers held by clients */ struct list_head pending; /* Buffers pending completion */ u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */ unsigned int fb_bpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_bpp; unsigned int depth_offset, depth_pitch; u32 front_offset_pitch; u32 back_offset_pitch; u32 depth_offset_pitch; drm_local_map_t *sarea; drm_local_map_t *fb; drm_local_map_t *mmio; drm_local_map_t *ring_map; drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */ drm_local_map_t *agp_textures; } drm_mach64_private_t; /* mach64_dma.c */ extern int mach64_dma_init( DRM_IOCTL_ARGS ); extern int mach64_dma_idle( DRM_IOCTL_ARGS ); extern int mach64_dma_flush( DRM_IOCTL_ARGS ); extern int mach64_engine_reset( DRM_IOCTL_ARGS ); extern int mach64_dma_buffers( DRM_IOCTL_ARGS ); extern int mach64_init_freelist( drm_device_t *dev ); extern void mach64_destroy_freelist( drm_device_t *dev ); extern drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv ); extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, int entries ); extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv ); extern int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n ); extern int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ); extern int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv ); extern void mach64_dump_engine_info( drm_mach64_private_t *dev_priv ); extern void mach64_dump_ring_info( drm_mach64_private_t *dev_priv ); extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv ); extern int mach64_do_dma_idle( drm_mach64_private_t *dev_priv ); extern int mach64_do_dma_flush( drm_mach64_private_t *dev_priv ); extern int mach64_do_cleanup_dma( drm_device_t *dev ); /* mach64_state.c */ extern int mach64_dma_clear( DRM_IOCTL_ARGS ); extern int mach64_dma_swap( DRM_IOCTL_ARGS ); extern int mach64_dma_vertex( DRM_IOCTL_ARGS ); extern int mach64_dma_blit( DRM_IOCTL_ARGS ); extern int mach64_get_param( DRM_IOCTL_ARGS ); extern int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); extern irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS ); extern void mach64_driver_irq_preinstall( drm_device_t *dev ); extern void mach64_driver_irq_postinstall( drm_device_t *dev ); extern void mach64_driver_irq_uninstall( drm_device_t *dev ); /* ================================================================ * Registers */ #define MACH64_AGP_BASE 0x0148 #define MACH64_AGP_CNTL 0x014c #define MACH64_ALPHA_TST_CNTL 0x0550 #define MACH64_DSP_CONFIG 0x0420 #define MACH64_DSP_ON_OFF 0x0424 #define MACH64_EXT_MEM_CNTL 0x04ac #define MACH64_GEN_TEST_CNTL 0x04d0 #define MACH64_HW_DEBUG 0x047c #define MACH64_MEM_ADDR_CONFIG 0x0434 #define MACH64_MEM_BUF_CNTL 0x042c #define MACH64_MEM_CNTL 0x04b0 #define MACH64_BM_ADDR 0x0648 #define MACH64_BM_COMMAND 0x0188 #define MACH64_BM_DATA 0x0648 #define MACH64_BM_FRAME_BUF_OFFSET 0x0180 #define MACH64_BM_GUI_TABLE 0x01b8 #define MACH64_BM_GUI_TABLE_CMD 0x064c # define MACH64_CIRCULAR_BUF_SIZE_16KB (0 << 0) # define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0) # define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0) # define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0) # define MACH64_LAST_DESCRIPTOR (1 << 31) #define MACH64_BM_HOSTDATA 0x0644 #define MACH64_BM_STATUS 0x018c #define MACH64_BM_SYSTEM_MEM_ADDR 0x0184 #define MACH64_BM_SYSTEM_TABLE 0x01bc #define MACH64_BUS_CNTL 0x04a0 # define MACH64_BUS_MSTR_RESET (1 << 1) # define MACH64_BUS_APER_REG_DIS (1 << 4) # define MACH64_BUS_FLUSH_BUF (1 << 2) # define MACH64_BUS_MASTER_DIS (1 << 6) # define MACH64_BUS_EXT_REG_EN (1 << 27) #define MACH64_CLR_CMP_CLR 0x0700 #define MACH64_CLR_CMP_CNTL 0x0708 #define MACH64_CLR_CMP_MASK 0x0704 #define MACH64_CONFIG_CHIP_ID 0x04e0 #define MACH64_CONFIG_CNTL 0x04dc #define MACH64_CONFIG_STAT0 0x04e4 #define MACH64_CONFIG_STAT1 0x0494 #define MACH64_CONFIG_STAT2 0x0498 #define MACH64_CONTEXT_LOAD_CNTL 0x072c #define MACH64_CONTEXT_MASK 0x0720 #define MACH64_COMPOSITE_SHADOW_ID 0x0798 #define MACH64_CRC_SIG 0x04e8 #define MACH64_CUSTOM_MACRO_CNTL 0x04d4 #define MACH64_DP_BKGD_CLR 0x06c0 #define MACH64_DP_FOG_CLR 0x06c4 #define MACH64_DP_FGRD_BKGD_CLR 0x06e0 #define MACH64_DP_FRGD_CLR 0x06c4 #define MACH64_DP_FGRD_CLR_MIX 0x06dc #define MACH64_DP_MIX 0x06d4 # define BKGD_MIX_NOT_D (0 << 0) # define BKGD_MIX_ZERO (1 << 0) # define BKGD_MIX_ONE (2 << 0) # define MACH64_BKGD_MIX_D (3 << 0) # define BKGD_MIX_NOT_S (4 << 0) # define BKGD_MIX_D_XOR_S (5 << 0) # define BKGD_MIX_NOT_D_XOR_S (6 << 0) # define MACH64_BKGD_MIX_S (7 << 0) # define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) # define BKGD_MIX_D_OR_NOT_S (9 << 0) # define BKGD_MIX_NOT_D_OR_S (10 << 0) # define BKGD_MIX_D_OR_S (11 << 0) # define BKGD_MIX_D_AND_S (12 << 0) # define BKGD_MIX_NOT_D_AND_S (13 << 0) # define BKGD_MIX_D_AND_NOT_S (14 << 0) # define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0) # define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0) # define FRGD_MIX_NOT_D (0 << 16) # define FRGD_MIX_ZERO (1 << 16) # define FRGD_MIX_ONE (2 << 16) # define FRGD_MIX_D (3 << 16) # define FRGD_MIX_NOT_S (4 << 16) # define FRGD_MIX_D_XOR_S (5 << 16) # define FRGD_MIX_NOT_D_XOR_S (6 << 16) # define MACH64_FRGD_MIX_S (7 << 16) # define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16) # define FRGD_MIX_D_OR_NOT_S (9 << 16) # define FRGD_MIX_NOT_D_OR_S (10 << 16) # define FRGD_MIX_D_OR_S (11 << 16) # define FRGD_MIX_D_AND_S (12 << 16) # define FRGD_MIX_NOT_D_AND_S (13 << 16) # define FRGD_MIX_D_AND_NOT_S (14 << 16) # define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16) # define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16) #define MACH64_DP_PIX_WIDTH 0x06d0 # define MACH64_HOST_TRIPLE_ENABLE (1 << 13) # define MACH64_BYTE_ORDER_MSB_TO_LSB (0 << 24) # define MACH64_BYTE_ORDER_LSB_TO_MSB (1 << 24) #define MACH64_DP_SRC 0x06d8 # define MACH64_BKGD_SRC_BKGD_CLR (0 << 0) # define MACH64_BKGD_SRC_FRGD_CLR (1 << 0) # define MACH64_BKGD_SRC_HOST (2 << 0) # define MACH64_BKGD_SRC_BLIT (3 << 0) # define MACH64_BKGD_SRC_PATTERN (4 << 0) # define MACH64_BKGD_SRC_3D (5 << 0) # define MACH64_FRGD_SRC_BKGD_CLR (0 << 8) # define MACH64_FRGD_SRC_FRGD_CLR (1 << 8) # define MACH64_FRGD_SRC_HOST (2 << 8) # define MACH64_FRGD_SRC_BLIT (3 << 8) # define MACH64_FRGD_SRC_PATTERN (4 << 8) # define MACH64_FRGD_SRC_3D (5 << 8) # define MACH64_MONO_SRC_ONE (0 << 16) # define MACH64_MONO_SRC_PATTERN (1 << 16) # define MACH64_MONO_SRC_HOST (2 << 16) # define MACH64_MONO_SRC_BLIT (3 << 16) #define MACH64_DP_WRITE_MASK 0x06c8 #define MACH64_DST_CNTL 0x0530 # define MACH64_DST_X_RIGHT_TO_LEFT (0 << 0) # define MACH64_DST_X_LEFT_TO_RIGHT (1 << 0) # define MACH64_DST_Y_BOTTOM_TO_TOP (0 << 1) # define MACH64_DST_Y_TOP_TO_BOTTOM (1 << 1) # define MACH64_DST_X_MAJOR (0 << 2) # define MACH64_DST_Y_MAJOR (1 << 2) # define MACH64_DST_X_TILE (1 << 3) # define MACH64_DST_Y_TILE (1 << 4) # define MACH64_DST_LAST_PEL (1 << 5) # define MACH64_DST_POLYGON_ENABLE (1 << 6) # define MACH64_DST_24_ROTATION_ENABLE (1 << 7) #define MACH64_DST_HEIGHT_WIDTH 0x0518 #define MACH64_DST_OFF_PITCH 0x0500 #define MACH64_DST_WIDTH_HEIGHT 0x06ec #define MACH64_DST_X_Y 0x06e8 #define MACH64_DST_Y_X 0x050c #define MACH64_FIFO_STAT 0x0710 # define MACH64_FIFO_SLOT_MASK 0x0000ffff # define MACH64_FIFO_ERR (1 << 31) #define MACH64_GEN_TEST_CNTL 0x04d0 # define MACH64_GUI_ENGINE_ENABLE (1 << 8) #define MACH64_GUI_CMDFIFO_DEBUG 0x0170 #define MACH64_GUI_CMDFIFO_DATA 0x0174 #define MACH64_GUI_CNTL 0x0178 # define MACH64_CMDFIFO_SIZE_MASK 0x00000003ul # define MACH64_CMDFIFO_SIZE_192 0x00000000ul # define MACH64_CMDFIFO_SIZE_128 0x00000001ul # define MACH64_CMDFIFO_SIZE_64 0x00000002ul #define MACH64_GUI_STAT 0x0738 # define MACH64_GUI_ACTIVE (1 << 0) #define MACH64_GUI_TRAJ_CNTL 0x0730 #define MACH64_HOST_CNTL 0x0640 #define MACH64_HOST_DATA0 0x0600 #define MACH64_ONE_OVER_AREA 0x029c #define MACH64_ONE_OVER_AREA_UC 0x0300 #define MACH64_PAT_REG0 0x0680 #define MACH64_PAT_REG1 0x0684 #define MACH64_SC_LEFT 0x06a0 #define MACH64_SC_RIGHT 0x06a4 #define MACH64_SC_LEFT_RIGHT 0x06a8 #define MACH64_SC_TOP 0x06ac #define MACH64_SC_BOTTOM 0x06b0 #define MACH64_SC_TOP_BOTTOM 0x06b4 #define MACH64_SCALE_3D_CNTL 0x05fc #define MACH64_SCRATCH_REG0 0x0480 #define MACH64_SCRATCH_REG1 0x0484 #define MACH64_SECONDARY_TEX_OFF 0x0778 #define MACH64_SETUP_CNTL 0x0304 #define MACH64_SRC_CNTL 0x05b4 # define MACH64_SRC_BM_ENABLE (1 << 8) # define MACH64_SRC_BM_SYNC (1 << 9) # define MACH64_SRC_BM_OP_FRAME_TO_SYSTEM (0 << 10) # define MACH64_SRC_BM_OP_SYSTEM_TO_FRAME (1 << 10) # define MACH64_SRC_BM_OP_REG_TO_SYSTEM (2 << 10) # define MACH64_SRC_BM_OP_SYSTEM_TO_REG (3 << 10) #define MACH64_SRC_HEIGHT1 0x0594 #define MACH64_SRC_HEIGHT2 0x05ac #define MACH64_SRC_HEIGHT1_WIDTH1 0x0598 #define MACH64_SRC_HEIGHT2_WIDTH2 0x05b0 #define MACH64_SRC_OFF_PITCH 0x0580 #define MACH64_SRC_WIDTH1 0x0590 #define MACH64_SRC_Y_X 0x058c #define MACH64_TEX_0_OFF 0x05c0 #define MACH64_TEX_CNTL 0x0774 #define MACH64_TEX_SIZE_PITCH 0x0770 #define MACH64_TIMER_CONFIG 0x0428 #define MACH64_VERTEX_1_ARGB 0x0254 #define MACH64_VERTEX_1_S 0x0240 #define MACH64_VERTEX_1_SECONDARY_S 0x0328 #define MACH64_VERTEX_1_SECONDARY_T 0x032c #define MACH64_VERTEX_1_SECONDARY_W 0x0330 #define MACH64_VERTEX_1_SPEC_ARGB 0x024c #define MACH64_VERTEX_1_T 0x0244 #define MACH64_VERTEX_1_W 0x0248 #define MACH64_VERTEX_1_X_Y 0x0258 #define MACH64_VERTEX_1_Z 0x0250 #define MACH64_VERTEX_2_ARGB 0x0274 #define MACH64_VERTEX_2_S 0x0260 #define MACH64_VERTEX_2_SECONDARY_S 0x0334 #define MACH64_VERTEX_2_SECONDARY_T 0x0338 #define MACH64_VERTEX_2_SECONDARY_W 0x033c #define MACH64_VERTEX_2_SPEC_ARGB 0x026c #define MACH64_VERTEX_2_T 0x0264 #define MACH64_VERTEX_2_W 0x0268 #define MACH64_VERTEX_2_X_Y 0x0278 #define MACH64_VERTEX_2_Z 0x0270 #define MACH64_VERTEX_3_ARGB 0x0294 #define MACH64_VERTEX_3_S 0x0280 #define MACH64_VERTEX_3_SECONDARY_S 0x02a0 #define MACH64_VERTEX_3_SECONDARY_T 0x02a4 #define MACH64_VERTEX_3_SECONDARY_W 0x02a8 #define MACH64_VERTEX_3_SPEC_ARGB 0x028c #define MACH64_VERTEX_3_T 0x0284 #define MACH64_VERTEX_3_W 0x0288 #define MACH64_VERTEX_3_X_Y 0x0298 #define MACH64_VERTEX_3_Z 0x0290 #define MACH64_Z_CNTL 0x054c #define MACH64_Z_OFF_PITCH 0x0548 #define MACH64_CRTC_VLINE_CRNT_VLINE 0x0410 # define MACH64_CRTC_VLINE_MASK 0x000007ff # define MACH64_CRTC_CRNT_VLINE_MASK 0x07ff0000 #define MACH64_CRTC_OFF_PITCH 0x0414 #define MACH64_CRTC_INT_CNTL 0x0418 # define MACH64_CRTC_VBLANK (1 << 0) # define MACH64_CRTC_VBLANK_INT_EN (1 << 1) # define MACH64_CRTC_VBLANK_INT (1 << 2) # define MACH64_CRTC_VLINE_INT_EN (1 << 3) # define MACH64_CRTC_VLINE_INT (1 << 4) # define MACH64_CRTC_VLINE_SYNC (1 << 5) /* 0=even, 1=odd */ # define MACH64_CRTC_FRAME (1 << 6) /* 0=even, 1=odd */ # define MACH64_CRTC_SNAPSHOT_INT_EN (1 << 7) # define MACH64_CRTC_SNAPSHOT_INT (1 << 8) # define MACH64_CRTC_I2C_INT_EN (1 << 9) # define MACH64_CRTC_I2C_INT (1 << 10) # define MACH64_CRTC2_VBLANK (1 << 11) /* LT Pro */ # define MACH64_CRTC2_VBLANK_INT_EN (1 << 12) /* LT Pro */ # define MACH64_CRTC2_VBLANK_INT (1 << 13) /* LT Pro */ # define MACH64_CRTC2_VLINE_INT_EN (1 << 14) /* LT Pro */ # define MACH64_CRTC2_VLINE_INT (1 << 15) /* LT Pro */ # define MACH64_CRTC_CAPBUF0_INT_EN (1 << 16) # define MACH64_CRTC_CAPBUF0_INT (1 << 17) # define MACH64_CRTC_CAPBUF1_INT_EN (1 << 18) # define MACH64_CRTC_CAPBUF1_INT (1 << 19) # define MACH64_CRTC_OVERLAY_EOF_INT_EN (1 << 20) # define MACH64_CRTC_OVERLAY_EOF_INT (1 << 21) # define MACH64_CRTC_ONESHOT_CAP_INT_EN (1 << 22) # define MACH64_CRTC_ONESHOT_CAP_INT (1 << 23) # define MACH64_CRTC_BUSMASTER_EOL_INT_EN (1 << 24) # define MACH64_CRTC_BUSMASTER_EOL_INT (1 << 25) # define MACH64_CRTC_GP_INT_EN (1 << 26) # define MACH64_CRTC_GP_INT (1 << 27) # define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */ # define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */ # define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */ # define MACH64_CRTC_VBLANK2_INT (1 << 31) # define MACH64_CRTC_INT_ENS \ ( \ MACH64_CRTC_VBLANK_INT_EN | \ MACH64_CRTC_VLINE_INT_EN | \ MACH64_CRTC_SNAPSHOT_INT_EN | \ MACH64_CRTC_I2C_INT_EN | \ MACH64_CRTC2_VBLANK_INT_EN | \ MACH64_CRTC2_VLINE_INT_EN | \ MACH64_CRTC_CAPBUF0_INT_EN | \ MACH64_CRTC_CAPBUF1_INT_EN | \ MACH64_CRTC_OVERLAY_EOF_INT_EN | \ MACH64_CRTC_ONESHOT_CAP_INT_EN | \ MACH64_CRTC_BUSMASTER_EOL_INT_EN | \ MACH64_CRTC_GP_INT_EN | \ MACH64_CRTC_SNAPSHOT2_INT_EN | \ 0 \ ) # define MACH64_CRTC_INT_ACKS \ ( \ MACH64_CRTC_VBLANK_INT | \ MACH64_CRTC_VLINE_INT | \ MACH64_CRTC_SNAPSHOT_INT | \ MACH64_CRTC_I2C_INT | \ MACH64_CRTC2_VBLANK_INT | \ MACH64_CRTC2_VLINE_INT | \ MACH64_CRTC_CAPBUF0_INT | \ MACH64_CRTC_CAPBUF1_INT | \ MACH64_CRTC_OVERLAY_EOF_INT | \ MACH64_CRTC_ONESHOT_CAP_INT | \ MACH64_CRTC_BUSMASTER_EOL_INT | \ MACH64_CRTC_GP_INT | \ MACH64_CRTC_SNAPSHOT2_INT | \ MACH64_CRTC_VBLANK2_INT | \ 0 \ ) #define MACH64_DATATYPE_CI8 2 #define MACH64_DATATYPE_ARGB1555 3 #define MACH64_DATATYPE_RGB565 4 #define MACH64_DATATYPE_ARGB8888 6 #define MACH64_DATATYPE_RGB332 7 #define MACH64_DATATYPE_Y8 8 #define MACH64_DATATYPE_RGB8 9 #define MACH64_DATATYPE_VYUY422 11 #define MACH64_DATATYPE_YVYU422 12 #define MACH64_DATATYPE_AYUV444 14 #define MACH64_DATATYPE_ARGB4444 15 #define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) ) #define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) ) #define DWMREG0 0x0400 #define DWMREG0_END 0x07ff #define DWMREG1 0x0000 #define DWMREG1_END 0x03ff #define ISREG0(r) (((r) >= DWMREG0) && ((r) <= DWMREG0_END)) #define DMAREG0(r) (((r) - DWMREG0) >> 2) #define DMAREG1(r) ((((r) - DWMREG1) >> 2 ) | 0x0100) #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) #define MMREG0 0x0000 #define MMREG0_END 0x00ff #define ISMMREG0(r) (((r) >= MMREG0) && ((r) <= MMREG0_END)) #define MMSELECT0(r) (((r) << 2) + DWMREG0) #define MMSELECT1(r) (((((r) & 0xff) << 2) + DWMREG1)) #define MMSELECT(r) (ISMMREG0(r) ? MMSELECT0(r) : MMSELECT1(r)) /* ================================================================ * DMA constants */ /* DMA descriptor field indices: * The descriptor fields are loaded into the read-only * BM_* system bus master registers during a bus-master operation */ #define MACH64_DMA_FRAME_BUF_OFFSET 0 /* BM_FRAME_BUF_OFFSET */ #define MACH64_DMA_SYS_MEM_ADDR 1 /* BM_SYSTEM_MEM_ADDR */ #define MACH64_DMA_COMMAND 2 /* BM_COMMAND */ #define MACH64_DMA_RESERVED 3 /* BM_STATUS */ /* BM_COMMAND descriptor field flags */ #define MACH64_DMA_HOLD_OFFSET (1<<30) /* Don't increment DMA_FRAME_BUF_OFFSET */ #define MACH64_DMA_EOL (1<<31) /* End of descriptor list flag */ #define MACH64_DMA_CHUNKSIZE 0x1000 /* 4kB per DMA descriptor */ #define MACH64_APERTURE_OFFSET 0x7ff800 /* frame-buffer offset for gui-masters */ /* ================================================================ * Misc helper macros */ static __inline__ void mach64_set_dma_eol( volatile u32 * addr ) { #if defined(__i386__) int nr = 31; /* Taken from include/asm-i386/bitops.h linux header */ __asm__ __volatile__( "lock;" "btsl %1,%0" :"=m" (*addr) :"Ir" (nr)); #elif defined(__powerpc__) u32 old; u32 mask = cpu_to_le32( MACH64_DMA_EOL ); /* Taken from the include/asm-ppc/bitops.h linux header */ __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ or %0,%0,%2 \n\ stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (old), "=m" (*addr) : "r" (mask), "r" (addr), "m" (*addr) : "cc"); #elif defined(__alpha__) u32 temp; u32 mask = MACH64_DMA_EOL; /* Taken from the include/asm-alpha/bitops.h linux header */ __asm__ __volatile__( "1: ldl_l %0,%3\n" " bis %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (*addr) :"Ir" (mask), "m" (*addr)); #else u32 mask = cpu_to_le32( MACH64_DMA_EOL ); *addr |= mask; #endif } static __inline__ void mach64_clear_dma_eol( volatile u32 * addr ) { #if defined(__i386__) int nr = 31; /* Taken from include/asm-i386/bitops.h linux header */ __asm__ __volatile__( "lock;" "btrl %1,%0" :"=m" (*addr) :"Ir" (nr)); #elif defined(__powerpc__) u32 old; u32 mask = cpu_to_le32( MACH64_DMA_EOL ); /* Taken from the include/asm-ppc/bitops.h linux header */ __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ andc %0,%0,%2 \n\ stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (old), "=m" (*addr) : "r" (mask), "r" (addr), "m" (*addr) : "cc"); #elif defined(__alpha__) u32 temp; u32 mask = ~MACH64_DMA_EOL; /* Taken from the include/asm-alpha/bitops.h linux header */ __asm__ __volatile__( "1: ldl_l %0,%3\n" " and %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (*addr) :"Ir" (mask), "m" (*addr)); #else u32 mask = cpu_to_le32( ~MACH64_DMA_EOL ); *addr &= mask; #endif } static __inline__ void mach64_ring_start( drm_mach64_private_t *dev_priv ) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", __FUNCTION__, ring->head_addr, ring->head, ring->tail, ring->space ); if ( mach64_do_wait_for_idle( dev_priv ) < 0 ) { mach64_do_engine_reset( dev_priv ); } if (dev_priv->driver_mode != MACH64_MODE_MMIO ) { /* enable bus mastering and block 1 registers */ MACH64_WRITE( MACH64_BUS_CNTL, ( MACH64_READ(MACH64_BUS_CNTL) & ~MACH64_BUS_MASTER_DIS ) | MACH64_BUS_EXT_REG_EN ); mach64_do_wait_for_idle( dev_priv ); } /* reset descriptor table ring head */ MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); dev_priv->ring_running = 1; } static __inline__ void mach64_ring_resume( drm_mach64_private_t *dev_priv, drm_mach64_descriptor_ring_t *ring ) { DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", __FUNCTION__, ring->head_addr, ring->head, ring->tail, ring->space ); /* reset descriptor table ring head */ MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); if ( dev_priv->driver_mode == MACH64_MODE_MMIO ) { mach64_do_dispatch_pseudo_dma( dev_priv ); } else { /* enable GUI bus mastering, and sync the bus master to the GUI */ MACH64_WRITE( MACH64_SRC_CNTL, MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | MACH64_SRC_BM_OP_SYSTEM_TO_REG ); /* kick off the transfer */ MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 ); if ( dev_priv->driver_mode == MACH64_MODE_DMA_SYNC ) { if ( (mach64_do_wait_for_idle( dev_priv )) < 0 ) { DRM_ERROR( "%s: idle failed, resetting engine\n", __FUNCTION__); mach64_dump_engine_info( dev_priv ); mach64_do_engine_reset( dev_priv ); return; } mach64_do_release_used_buffers( dev_priv ); } } } static __inline__ void mach64_ring_tick( drm_mach64_private_t *dev_priv, drm_mach64_descriptor_ring_t *ring ) { DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", __FUNCTION__, ring->head_addr, ring->head, ring->tail, ring->space ); if ( !dev_priv->ring_running ) { mach64_ring_start( dev_priv ); if ( ring->head != ring->tail ) { mach64_ring_resume( dev_priv, ring ); } } else { /* GUI_ACTIVE must be read before BM_GUI_TABLE to * correctly determine the ring head */ int gui_active = MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE; ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0; if ( gui_active ) { /* If not idle, BM_GUI_TABLE points one descriptor * past the current head */ if ( ring->head_addr == ring->start_addr ) { ring->head_addr += ring->size; } ring->head_addr -= 4 * sizeof(u32); } if( ring->head_addr < ring->start_addr || ring->head_addr >= ring->start_addr + ring->size ) { DRM_ERROR( "bad ring head address: 0x%08x\n", ring->head_addr ); mach64_dump_ring_info( dev_priv ); mach64_do_engine_reset( dev_priv ); return; } ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32); if ( !gui_active && ring->head != ring->tail ) { mach64_ring_resume( dev_priv, ring ); } } } static __inline__ void mach64_ring_stop( drm_mach64_private_t *dev_priv ) { DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", __FUNCTION__, dev_priv->ring.head_addr, dev_priv->ring.head, dev_priv->ring.tail, dev_priv->ring.space ); /* restore previous SRC_CNTL to disable busmastering */ mach64_do_wait_for_fifo( dev_priv, 1 ); MACH64_WRITE( MACH64_SRC_CNTL, 0 ); /* disable busmastering but keep the block 1 registers enabled */ mach64_do_wait_for_idle( dev_priv ); MACH64_WRITE( MACH64_BUS_CNTL, MACH64_READ( MACH64_BUS_CNTL ) | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN ); dev_priv->ring_running = 0; } static __inline__ void mach64_update_ring_snapshot( drm_mach64_private_t *dev_priv ) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; DRM_DEBUG( "%s\n", __FUNCTION__ ); mach64_ring_tick( dev_priv, ring ); ring->space = (ring->head - ring->tail) * sizeof(u32); if ( ring->space <= 0 ) { ring->space += ring->size; } } /* ================================================================ * DMA descriptor ring macros */ #define RING_LOCALS \ int _ring_tail, _ring_write; unsigned int _ring_mask; volatile u32 *_ring #define RING_WRITE_OFS _ring_write #define BEGIN_RING( n ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ (n), __FUNCTION__ ); \ } \ if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ int ret; \ if ((ret=mach64_wait_ring( dev_priv, (n) * sizeof(u32))) < 0 ) { \ DRM_ERROR( "wait_ring failed, resetting engine\n"); \ mach64_dump_engine_info( dev_priv ); \ mach64_do_engine_reset( dev_priv ); \ return ret; \ } \ } \ dev_priv->ring.space -= (n) * sizeof(u32); \ _ring = (u32 *) dev_priv->ring.start; \ _ring_tail = _ring_write = dev_priv->ring.tail; \ _ring_mask = dev_priv->ring.tail_mask; \ } while (0) #define OUT_RING( x ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ (unsigned int)(x), _ring_write ); \ } \ _ring[_ring_write++] = cpu_to_le32( x ); \ _ring_write &= _ring_mask; \ } while (0) #define ADVANCE_RING() \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ _ring_write, _ring_tail ); \ } \ DRM_MEMORYBARRIER(); \ mach64_clear_dma_eol( &_ring[(_ring_tail - 2) & _ring_mask] ); \ DRM_MEMORYBARRIER(); \ dev_priv->ring.tail = _ring_write; \ mach64_ring_tick( dev_priv, &(dev_priv)->ring ); \ } while (0) /* ================================================================ * DMA macros */ #define DMALOCALS \ drm_mach64_freelist_t *_entry = NULL; \ drm_buf_t *_buf = NULL; \ u32 *_buf_wptr; int _outcount #define GETBUFPTR( __buf ) \ ((dev_priv->is_pci) ? \ ((u32 *)(__buf)->address) : \ ((u32 *)((char *)dev_priv->dev_buffers->handle + (__buf)->offset))) #define GETBUFADDR( __buf ) ((u32)(__buf)->bus_address) #define GETRINGOFFSET() (_entry->ring_ofs) static __inline__ int mach64_find_pending_buf_entry ( drm_mach64_private_t *dev_priv, drm_mach64_freelist_t **entry, drm_buf_t *buf ) { struct list_head *ptr; #if MACH64_EXTRA_CHECKING if (list_empty(&dev_priv->pending)) { DRM_ERROR("Empty pending list in %s\n", __FUNCTION__); return DRM_ERR(EINVAL); } #endif ptr = dev_priv->pending.prev; *entry = list_entry(ptr, drm_mach64_freelist_t, list); while ((*entry)->buf != buf) { if (ptr == &dev_priv->pending) { return DRM_ERR(EFAULT); } ptr = ptr->prev; *entry = list_entry(ptr, drm_mach64_freelist_t, list); } return 0; } #define DMASETPTR( _p ) \ do { \ _buf = (_p); \ _outcount = 0; \ _buf_wptr = GETBUFPTR( _buf ); \ } while(0) /* FIXME: use a private set of smaller buffers for state emits, clears, and swaps? */ #define DMAGETPTR( filp, dev_priv, n ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "DMAGETPTR( %d ) in %s\n", \ n, __FUNCTION__ ); \ } \ _buf = mach64_freelist_get( dev_priv ); \ if (_buf == NULL) { \ DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n", \ __FUNCTION__ ); \ return DRM_ERR(EAGAIN); \ } \ if (_buf->pending) { \ DRM_ERROR("%s: pending buf in DMAGETPTR\n", \ __FUNCTION__ ); \ return DRM_ERR(EFAULT); \ } \ _buf->filp = filp; \ _outcount = 0; \ \ _buf_wptr = GETBUFPTR( _buf ); \ } while (0) #define DMAOUTREG( reg, val ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( " DMAOUTREG( 0x%x = 0x%08x )\n", \ reg, val ); \ } \ _buf_wptr[_outcount++] = cpu_to_le32(DMAREG(reg)); \ _buf_wptr[_outcount++] = cpu_to_le32((val)); \ _buf->used += 8; \ } while (0) #define DMAADVANCE( dev_priv, _discard ) \ do { \ struct list_head *ptr; \ RING_LOCALS; \ \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "DMAADVANCE() in %s\n", __FUNCTION__ ); \ } \ \ if (_buf->used <= 0) { \ DRM_ERROR( "DMAADVANCE() in %s: sending empty buf %d\n", \ __FUNCTION__, _buf->idx ); \ return DRM_ERR(EFAULT); \ } \ if (_buf->pending) { \ /* This is a resued buffer, so we need to find it in the pending list */ \ int ret; \ if ( (ret=mach64_find_pending_buf_entry(dev_priv, &_entry, _buf)) ) { \ DRM_ERROR( "DMAADVANCE() in %s: couldn't find pending buf %d\n", \ __FUNCTION__, _buf->idx ); \ return ret; \ } \ if (_entry->discard) { \ DRM_ERROR( "DMAADVANCE() in %s: sending discarded pending buf %d\n", \ __FUNCTION__, _buf->idx ); \ return DRM_ERR(EFAULT); \ } \ } else { \ if (list_empty(&dev_priv->placeholders)) { \ DRM_ERROR( "DMAADVANCE() in %s: empty placeholder list\n", \ __FUNCTION__ ); \ return DRM_ERR(EFAULT); \ } \ ptr = dev_priv->placeholders.next; \ list_del(ptr); \ _entry = list_entry(ptr, drm_mach64_freelist_t, list); \ _buf->pending = 1; \ _entry->buf = _buf; \ list_add_tail(ptr, &dev_priv->pending); \ } \ _entry->discard = (_discard); \ ADD_BUF_TO_RING( dev_priv ); \ } while (0) #define DMADISCARDBUF() \ do { \ if (_entry == NULL) { \ int ret; \ if ( (ret=mach64_find_pending_buf_entry(dev_priv, &_entry, _buf)) ) { \ DRM_ERROR( "%s: couldn't find pending buf %d\n", \ __FUNCTION__, _buf->idx ); \ return ret; \ } \ } \ _entry->discard = 1; \ } while(0) #define ADD_BUF_TO_RING( dev_priv ) \ do { \ int bytes, pages, remainder; \ u32 address, page; \ int i; \ \ bytes = _buf->used; \ address = GETBUFADDR( _buf ); \ \ pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; \ \ BEGIN_RING( pages * 4 ); \ \ for ( i = 0 ; i < pages-1 ; i++ ) { \ page = address + i * MACH64_DMA_CHUNKSIZE; \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ OUT_RING( page ); \ OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); \ OUT_RING( 0 ); \ } \ \ /* generate the final descriptor for any remaining commands in this buffer */ \ page = address + i * MACH64_DMA_CHUNKSIZE; \ remainder = bytes - i * MACH64_DMA_CHUNKSIZE; \ \ /* Save dword offset of last descriptor for this buffer. \ * This is needed to check for completion of the buffer in freelist_get \ */ \ _entry->ring_ofs = RING_WRITE_OFS; \ \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ OUT_RING( page ); \ OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); \ OUT_RING( 0 ); \ \ ADVANCE_RING(); \ } while(0) #define DMAADVANCEHOSTDATA( dev_priv ) \ do { \ struct list_head *ptr; \ RING_LOCALS; \ \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "DMAADVANCEHOSTDATA() in %s\n", __FUNCTION__ ); \ } \ \ if (_buf->used <= 0) { \ DRM_ERROR( "DMAADVANCEHOSTDATA() in %s: sending empty buf %d\n", \ __FUNCTION__, _buf->idx ); \ return DRM_ERR(EFAULT); \ } \ if (list_empty(&dev_priv->placeholders)) { \ DRM_ERROR( "%s: empty placeholder list in DMAADVANCEHOSTDATA()\n", \ __FUNCTION__ ); \ return DRM_ERR(EFAULT); \ } \ \ ptr = dev_priv->placeholders.next; \ list_del(ptr); \ _entry = list_entry(ptr, drm_mach64_freelist_t, list); \ _entry->buf = _buf; \ _entry->buf->pending = 1; \ list_add_tail(ptr, &dev_priv->pending); \ _entry->discard = 1; \ ADD_HOSTDATA_BUF_TO_RING( dev_priv ); \ } while (0) #define ADD_HOSTDATA_BUF_TO_RING( dev_priv ) \ do { \ int bytes, pages, remainder; \ u32 address, page; \ int i; \ \ bytes = _buf->used - MACH64_HOSTDATA_BLIT_OFFSET; \ pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; \ address = GETBUFADDR( _buf ); \ \ BEGIN_RING( 4 + pages * 4 ); \ \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ OUT_RING( address ); \ OUT_RING( MACH64_HOSTDATA_BLIT_OFFSET | MACH64_DMA_HOLD_OFFSET ); \ OUT_RING( 0 ); \ \ address += MACH64_HOSTDATA_BLIT_OFFSET; \ \ for ( i = 0 ; i < pages-1 ; i++ ) { \ page = address + i * MACH64_DMA_CHUNKSIZE; \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \ OUT_RING( page ); \ OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); \ OUT_RING( 0 ); \ } \ \ /* generate the final descriptor for any remaining commands in this buffer */ \ page = address + i * MACH64_DMA_CHUNKSIZE; \ remainder = bytes - i * MACH64_DMA_CHUNKSIZE; \ \ /* Save dword offset of last descriptor for this buffer. \ * This is needed to check for completion of the buffer in freelist_get \ */ \ _entry->ring_ofs = RING_WRITE_OFS; \ \ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \ OUT_RING( page ); \ OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); \ OUT_RING( 0 ); \ \ ADVANCE_RING(); \ } while(0) #endif /* __MACH64_DRV_H__ */ 4' href='#n974'>974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 
/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
 *
 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Kevin E. Martin <martin@valinux.com>
 *    Gareth Hughes <gareth@valinux.com>
 */

#include "radeon.h"
#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"

#define RADEON_FIFO_DEBUG	0

/* CP microcode (from ATI) */
static u32 R200_cp_microcode[][2] = {
	{ 0x21007000, 0000000000 },        
	{ 0x20007000, 0000000000 }, 
	{ 0x000000ab, 0x00000004 },
	{ 0x000000af, 0x00000004 },
	{ 0x66544a49, 0000000000 },
	{ 0x49494174, 0000000000 },
	{ 0x54517d83, 0000000000 },
	{ 0x498d8b64, 0000000000 },
	{ 0x49494949, 0000000000 },
	{ 0x49da493c, 0000000000 },
	{ 0x49989898, 0000000000 },
	{ 0xd34949d5, 0000000000 },
	{ 0x9dc90e11, 0000000000 },
	{ 0xce9b9b9b, 0000000000 },
	{ 0x000f0000, 0x00000016 },
	{ 0x352e232c, 0000000000 },
	{ 0x00000013, 0x00000004 },
	{ 0x000f0000, 0x00000016 },
	{ 0x352e272c, 0000000000 },
	{ 0x000f0001, 0x00000016 },
	{ 0x3239362f, 0000000000 },
	{ 0x000077ef, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x00000020, 0x0000001a },
	{ 0x00004000, 0x0000001e },
	{ 0x00061000, 0x00000002 },
	{ 0x00000020, 0x0000001a },
	{ 0x00004000, 0x0000001e },
	{ 0x00061000, 0x00000002 },
	{ 0x00000020, 0x0000001a },
	{ 0x00004000, 0x0000001e },
	{ 0x00000016, 0x00000004 },
	{ 0x0003802a, 0x00000002 },
	{ 0x040067e0, 0x00000002 },
	{ 0x00000016, 0x00000004 },
	{ 0x000077e0, 0x00000002 },
	{ 0x00065000, 0x00000002 },
	{ 0x000037e1, 0x00000002 },
	{ 0x040067e1, 0x00000006 },
	{ 0x000077e0, 0x00000002 },
	{ 0x000077e1, 0x00000002 },
	{ 0x000077e1, 0x00000006 },
	{ 0xffffffff, 0000000000 },
	{ 0x10000000, 0000000000 },
	{ 0x0003802a, 0x00000002 },
	{ 0x040067e0, 0x00000006 },
	{ 0x00007675, 0x00000002 },
	{ 0x00007676, 0x00000002 },
	{ 0x00007677, 0x00000002 },
	{ 0x00007678, 0x00000006 },
	{ 0x0003802b, 0x00000002 },
	{ 0x04002676, 0x00000002 },
	{ 0x00007677, 0x00000002 },
	{ 0x00007678, 0x00000006 },
	{ 0x0000002e, 0x00000018 },
	{ 0x0000002e, 0x00000018 },
	{ 0000000000, 0x00000006 },
	{ 0x0000002f, 0x00000018 },
	{ 0x0000002f, 0x00000018 },
	{ 0000000000, 0x00000006 },
	{ 0x01605000, 0x00000002 },
	{ 0x00065000, 0x00000002 },
	{ 0x00098000, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x64c0603d, 0x00000004 },
	{ 0x00080000, 0x00000016 },
	{ 0000000000, 0000000000 },
	{ 0x0400251d, 0x00000002 },
	{ 0x00007580, 0x00000002 },
	{ 0x00067581, 0x00000002 },
	{ 0x04002580, 0x00000002 },
	{ 0x00067581, 0x00000002 },
	{ 0x00000046, 0x00000004 },
	{ 0x00005000, 0000000000 },
	{ 0x00061000, 0x00000002 },
	{ 0x0000750e, 0x00000002 },
	{ 0x00019000, 0x00000002 },
	{ 0x00011055, 0x00000014 },
	{ 0x00000055, 0x00000012 },
	{ 0x0400250f, 0x00000002 },
	{ 0x0000504a, 0x00000004 },
	{ 0x00007565, 0x00000002 },
	{ 0x00007566, 0x00000002 },
	{ 0x00000051, 0x00000004 },
	{ 0x01e655b4, 0x00000002 },
	{ 0x4401b0dc, 0x00000002 },
	{ 0x01c110dc, 0x00000002 },
	{ 0x2666705d, 0x00000018 },
	{ 0x040c2565, 0x00000002 },
	{ 0x0000005d, 0x00000018 },
	{ 0x04002564, 0x00000002 },
	{ 0x00007566, 0x00000002 },
	{ 0x00000054, 0x00000004 },
	{ 0x00401060, 0x00000008 },
	{ 0x00101000, 0x00000002 },
	{ 0x000d80ff, 0x00000002 },
	{ 0x00800063, 0x00000008 },
	{ 0x000f9000, 0x00000002 },
	{ 0x000e00ff, 0x00000002 },
	{ 0000000000, 0x00000006 },
	{ 0x00000080, 0x00000018 },
	{ 0x00000054, 0x00000004 },
	{ 0x00007576, 0x00000002 },
	{ 0x00065000, 0x00000002 },
	{ 0x00009000, 0x00000002 },
	{ 0x00041000, 0x00000002 },
	{ 0x0c00350e, 0x00000002 },
	{ 0x00049000, 0x00000002 },
	{ 0x00051000, 0x00000002 },
	{ 0x01e785f8, 0x00000002 },
	{ 0x00200000, 0x00000002 },
	{ 0x00600073, 0x0000000c },
	{ 0x00007563, 0x00000002 },
	{ 0x006075f0, 0x00000021 },
	{ 0x20007068, 0x00000004 },
	{ 0x00005068, 0x00000004 },
	{ 0x00007576, 0x00000002 },
	{ 0x00007577, 0x00000002 },
	{ 0x0000750e, 0x00000002 },
	{ 0x0000750f, 0x00000002 },
	{ 0x00a05000, 0x00000002 },
	{ 0x00600076, 0x0000000c },
	{ 0x006075f0, 0x00000021 },
	{ 0x000075f8, 0x00000002 },
	{ 0x00000076, 0x00000004 },
	{ 0x000a750e, 0x00000002 },
	{ 0x0020750f, 0x00000002 },
	{ 0x00600079, 0x00000004 },
	{ 0x00007570, 0x00000002 },
	{ 0x00007571, 0x00000002 },
	{ 0x00007572, 0x00000006 },
	{ 0x00005000, 0x00000002 },
	{ 0x00a05000, 0x00000002 },
	{ 0x00007568, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x00000084, 0x0000000c },
	{ 0x00058000, 0x00000002 },
	{ 0x0c607562, 0x00000002 },
	{ 0x00000086, 0x00000004 },
	{ 0x00600085, 0x00000004 },
	{ 0x400070dd, 0000000000 },
	{ 0x000380dd, 0x00000002 },
	{ 0x00000093, 0x0000001c },
	{ 0x00065095, 0x00000018 },
	{ 0x040025bb, 0x00000002 },
	{ 0x00061096, 0x00000018 },
	{ 0x040075bc, 0000000000 },
	{ 0x000075bb, 0x00000002 },
	{ 0x000075bc, 0000000000 },
	{ 0x00090000, 0x00000006 },
	{ 0x00090000, 0x00000002 },
	{ 0x000d8002, 0x00000006 },
	{ 0x00005000, 0x00000002 },
	{ 0x00007821, 0x00000002 },
	{ 0x00007800, 0000000000 },
	{ 0x00007821, 0x00000002 },
	{ 0x00007800, 0000000000 },
	{ 0x01665000, 0x00000002 },
	{ 0x000a0000, 0x00000002 },
	{ 0x000671cc, 0x00000002 },
	{ 0x0286f1cd, 0x00000002 },
	{ 0x000000a3, 0x00000010 },
	{ 0x21007000, 0000000000 },
	{ 0x000000aa, 0x0000001c },
	{ 0x00065000, 0x00000002 },
	{ 0x000a0000, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x000b0000, 0x00000002 },
	{ 0x38067000, 0x00000002 },
	{ 0x000a00a6, 0x00000004 },
	{ 0x20007000, 0000000000 },
	{ 0x01200000, 0x00000002 },
	{ 0x20077000, 0x00000002 },
	{ 0x01200000, 0x00000002 },
	{ 0x20007000, 0000000000 },
	{ 0x00061000, 0x00000002 },
	{ 0x0120751b, 0x00000002 },
	{ 0x8040750a, 0x00000002 },
	{ 0x8040750b, 0x00000002 },
	{ 0x00110000, 0x00000002 },
	{ 0x000380dd, 0x00000002 },
	{ 0x000000bd, 0x0000001c },
	{ 0x00061096, 0x00000018 },
	{ 0x844075bd, 0x00000002 },
	{ 0x00061095, 0x00000018 },
	{ 0x840075bb, 0x00000002 },
	{ 0x00061096, 0x00000018 },
	{ 0x844075bc, 0x00000002 },
	{ 0x000000c0, 0x00000004 },
	{ 0x804075bd, 0x00000002 },
	{ 0x800075bb, 0x00000002 },
	{ 0x804075bc, 0x00000002 },
	{ 0x00108000, 0x00000002 },
	{ 0x01400000, 0x00000002 },
	{ 0x006000c4, 0x0000000c },
	{ 0x20c07000, 0x00000020 },
	{ 0x000000c6, 0x00000012 },
	{ 0x00800000, 0x00000006 },
	{ 0x0080751d, 0x00000006 },
	{ 0x000025bb, 0x00000002 },
	{ 0x000040c0, 0x00000004 },
	{ 0x0000775c, 0x00000002 },
	{ 0x00a05000, 0x00000002 },
	{ 0x00661000, 0x00000002 },
	{ 0x0460275d, 0x00000020 },
	{ 0x00004000, 0000000000 },
	{ 0x00007999, 0x00000002 },
	{ 0x00a05000, 0x00000002 },
	{ 0x00661000, 0x00000002 },
	{ 0x0460299b, 0x00000020 },
	{ 0x00004000, 0000000000 },
	{ 0x01e00830, 0x00000002 },
	{ 0x21007000, 0000000000 },
	{ 0x00005000, 0x00000002 },
	{ 0x00038042, 0x00000002 },
	{ 0x040025e0, 0x00000002 },
	{ 0x000075e1, 0000000000 },
	{ 0x00000001, 0000000000 },
	{ 0x000380d9, 0x00000002 },
	{ 0x04007394, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
};


static u32 radeon_cp_microcode[][2] = {
	{ 0x21007000, 0000000000 },
	{ 0x20007000, 0000000000 },
	{ 0x000000b4, 0x00000004 },
	{ 0x000000b8, 0x00000004 },
	{ 0x6f5b4d4c, 0000000000 },
	{ 0x4c4c427f, 0000000000 },
	{ 0x5b568a92, 0000000000 },
	{ 0x4ca09c6d, 0000000000 },
	{ 0xad4c4c4c, 0000000000 },
	{ 0x4ce1af3d, 0000000000 },
	{ 0xd8afafaf, 0000000000 },
	{ 0xd64c4cdc, 0000000000 },
	{ 0x4cd10d10, 0000000000 },
	{ 0x000f0000, 0x00000016 },
	{ 0x362f242d, 0000000000 },
	{ 0x00000012, 0x00000004 },
	{ 0x000f0000, 0x00000016 },
	{ 0x362f282d, 0000000000 },
	{ 0x000380e7, 0x00000002 },
	{ 0x04002c97, 0x00000002 },
	{ 0x000f0001, 0x00000016 },
	{ 0x333a3730, 0000000000 },
	{ 0x000077ef, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x00000021, 0x0000001a },
	{ 0x00004000, 0x0000001e },
	{ 0x00061000, 0x00000002 },
	{ 0x00000021, 0x0000001a },
	{ 0x00004000, 0x0000001e },
	{ 0x00061000, 0x00000002 },
	{ 0x00000021, 0x0000001a },
	{ 0x00004000, 0x0000001e },
	{ 0x00000017, 0x00000004 },
	{ 0x0003802b, 0x00000002 },
	{ 0x040067e0, 0x00000002 },
	{ 0x00000017, 0x00000004 },
	{ 0x000077e0, 0x00000002 },
	{ 0x00065000, 0x00000002 },
	{ 0x000037e1, 0x00000002 },
	{ 0x040067e1, 0x00000006 },
	{ 0x000077e0, 0x00000002 },
	{ 0x000077e1, 0x00000002 },
	{ 0x000077e1, 0x00000006 },
	{ 0xffffffff, 0000000000 },
	{ 0x10000000, 0000000000 },
	{ 0x0003802b, 0x00000002 },
	{ 0x040067e0, 0x00000006 },
	{ 0x00007675, 0x00000002 },
	{ 0x00007676, 0x00000002 },
	{ 0x00007677, 0x00000002 },
	{ 0x00007678, 0x00000006 },
	{ 0x0003802c, 0x00000002 },
	{ 0x04002676, 0x00000002 },
	{ 0x00007677, 0x00000002 },
	{ 0x00007678, 0x00000006 },
	{ 0x0000002f, 0x00000018 },
	{ 0x0000002f, 0x00000018 },
	{ 0000000000, 0x00000006 },
	{ 0x00000030, 0x00000018 },
	{ 0x00000030, 0x00000018 },
	{ 0000000000, 0x00000006 },
	{ 0x01605000, 0x00000002 },
	{ 0x00065000, 0x00000002 },
	{ 0x00098000, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x64c0603e, 0x00000004 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x00080000, 0x00000016 },
	{ 0000000000, 0000000000 },
	{ 0x0400251d, 0x00000002 },
	{ 0x00007580, 0x00000002 },
	{ 0x00067581, 0x00000002 },
	{ 0x04002580, 0x00000002 },
	{ 0x00067581, 0x00000002 },
	{ 0x00000049, 0x00000004 },
	{ 0x00005000, 0000000000 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x0000750e, 0x00000002 },
	{ 0x00019000, 0x00000002 },
	{ 0x00011055, 0x00000014 },
	{ 0x00000055, 0x00000012 },
	{ 0x0400250f, 0x00000002 },
	{ 0x0000504f, 0x00000004 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x00007565, 0x00000002 },
	{ 0x00007566, 0x00000002 },
	{ 0x00000058, 0x00000004 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x01e655b4, 0x00000002 },
	{ 0x4401b0e4, 0x00000002 },
	{ 0x01c110e4, 0x00000002 },
	{ 0x26667066, 0x00000018 },
	{ 0x040c2565, 0x00000002 },
	{ 0x00000066, 0x00000018 },
	{ 0x04002564, 0x00000002 },
	{ 0x00007566, 0x00000002 },
	{ 0x0000005d, 0x00000004 },
	{ 0x00401069, 0x00000008 },
	{ 0x00101000, 0x00000002 },
	{ 0x000d80ff, 0x00000002 },
	{ 0x0080006c, 0x00000008 },
	{ 0x000f9000, 0x00000002 },
	{ 0x000e00ff, 0x00000002 },
	{ 0000000000, 0x00000006 },
	{ 0x0000008f, 0x00000018 },
	{ 0x0000005b, 0x00000004 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x00007576, 0x00000002 },
	{ 0x00065000, 0x00000002 },
	{ 0x00009000, 0x00000002 },
	{ 0x00041000, 0x00000002 },
	{ 0x0c00350e, 0x00000002 },
	{ 0x00049000, 0x00000002 },
	{ 0x00051000, 0x00000002 },
	{ 0x01e785f8, 0x00000002 },
	{ 0x00200000, 0x00000002 },
	{ 0x0060007e, 0x0000000c },
	{ 0x00007563, 0x00000002 },
	{ 0x006075f0, 0x00000021 },
	{ 0x20007073, 0x00000004 },
	{ 0x00005073, 0x00000004 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x00007576, 0x00000002 },
	{ 0x00007577, 0x00000002 },
	{ 0x0000750e, 0x00000002 },
	{ 0x0000750f, 0x00000002 },
	{ 0x00a05000, 0x00000002 },
	{ 0x00600083, 0x0000000c },
	{ 0x006075f0, 0x00000021 },
	{ 0x000075f8, 0x00000002 },
	{ 0x00000083, 0x00000004 },
	{ 0x000a750e, 0x00000002 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x0020750f, 0x00000002 },
	{ 0x00600086, 0x00000004 },
	{ 0x00007570, 0x00000002 },
	{ 0x00007571, 0x00000002 },
	{ 0x00007572, 0x00000006 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x00005000, 0x00000002 },
	{ 0x00a05000, 0x00000002 },
	{ 0x00007568, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x00000095, 0x0000000c },
	{ 0x00058000, 0x00000002 },
	{ 0x0c607562, 0x00000002 },
	{ 0x00000097, 0x00000004 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x00600096, 0x00000004 },
	{ 0x400070e5, 0000000000 },
	{ 0x000380e6, 0x00000002 },
	{ 0x040025c5, 0x00000002 },
	{ 0x000380e5, 0x00000002 },
	{ 0x000000a8, 0x0000001c },
	{ 0x000650aa, 0x00000018 },
	{ 0x040025bb, 0x00000002 },
	{ 0x000610ab, 0x00000018 },
	{ 0x040075bc, 0000000000 },
	{ 0x000075bb, 0x00000002 },
	{ 0x000075bc, 0000000000 },
	{ 0x00090000, 0x00000006 },
	{ 0x00090000, 0x00000002 },
	{ 0x000d8002, 0x00000006 },
	{ 0x00007832, 0x00000002 },
	{ 0x00005000, 0x00000002 },
	{ 0x000380e7, 0x00000002 },
	{ 0x04002c97, 0x00000002 },
	{ 0x00007820, 0x00000002 },
	{ 0x00007821, 0x00000002 },
	{ 0x00007800, 0000000000 },
	{ 0x01200000, 0x00000002 },
	{ 0x20077000, 0x00000002 },
	{ 0x01200000, 0x00000002 },
	{ 0x20007000, 0x00000002 },
	{ 0x00061000, 0x00000002 },
	{ 0x0120751b, 0x00000002 },
	{ 0x8040750a, 0x00000002 },
	{ 0x8040750b, 0x00000002 },
	{ 0x00110000, 0x00000002 },
	{ 0x000380e5, 0x00000002 },
	{ 0x000000c6, 0x0000001c },
	{ 0x000610ab, 0x00000018 },
	{ 0x844075bd, 0x00000002 },
	{ 0x000610aa, 0x00000018 },
	{ 0x840075bb, 0x00000002 },
	{ 0x000610ab, 0x00000018 },
	{ 0x844075bc, 0x00000002 },
	{ 0x000000c9, 0x00000004 },
	{ 0x804075bd, 0x00000002 },
	{ 0x800075bb, 0x00000002 },
	{ 0x804075bc, 0x00000002 },
	{ 0x00108000, 0x00000002 },
	{ 0x01400000, 0x00000002 },
	{ 0x006000cd, 0x0000000c },
	{ 0x20c07000, 0x00000020 },
	{ 0x000000cf, 0x00000012 },
	{ 0x00800000, 0x00000006 },
	{ 0x0080751d, 0x00000006 },
	{ 0000000000, 0000000000 },
	{ 0x0000775c, 0x00000002 },
	{ 0x00a05000, 0x00000002 },
	{ 0x00661000, 0x00000002 },
	{ 0x0460275d, 0x00000020 },
	{ 0x00004000, 0000000000 },
	{ 0x01e00830, 0x00000002 },
	{ 0x21007000, 0000000000 },
	{ 0x6464614d, 0000000000 },
	{ 0x69687420, 0000000000 },
	{ 0x00000073, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0x00005000, 0x00000002 },
	{ 0x000380d0, 0x00000002 },
	{ 0x040025e0, 0x00000002 },
	{ 0x000075e1, 0000000000 },
	{ 0x00000001, 0000000000 },
	{ 0x000380e0, 0x00000002 },
	{ 0x04002394, 0x00000002 },
	{ 0x00005000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0x00000008, 0000000000 },
	{ 0x00000004, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
};

static u32 R300_cp_microcode[][2] = {
	{ 0x4200e000, 0000000000 },
	{ 0x4000e000, 0000000000 },
	{ 0x000000af, 0x00000008 },
	{ 0x000000b3, 0x00000008 },
	{ 0x6c5a504f, 0000000000 },
	{ 0x4f4f497a, 0000000000 },
	{ 0x5a578288, 0000000000 },
	{ 0x4f91906a, 0000000000 },
	{ 0x4f4f4f4f, 0000000000 },
	{ 0x4fe24f44, 0000000000 },
	{ 0x4f9c9c9c, 0000000000 },
	{ 0xdc4f4fde, 0000000000 },
	{ 0xa1cd4f4f, 0000000000 },
	{ 0xd29d9d9d, 0000000000 },
	{ 0x4f0f9fd7, 0000000000 },
	{ 0x000ca000, 0x00000004 },
	{ 0x000d0012, 0x00000038 },
	{ 0x0000e8b4, 0x00000004 },
	{ 0x000d0014, 0x00000038 },
	{ 0x0000e8b6, 0x00000004 },
	{ 0x000d0016, 0x00000038 },
	{ 0x0000e854, 0x00000004 },
	{ 0x000d0018, 0x00000038 },
	{ 0x0000e855, 0x00000004 },
	{ 0x000d001a, 0x00000038 },
	{ 0x0000e856, 0x00000004 },
	{ 0x000d001c, 0x00000038 },
	{ 0x0000e857, 0x00000004 },
	{ 0x000d001e, 0x00000038 },
	{ 0x0000e824, 0x00000004 },
	{ 0x000d0020, 0x00000038 },
	{ 0x0000e825, 0x00000004 },
	{ 0x000d0022, 0x00000038 },
	{ 0x0000e830, 0x00000004 },
	{ 0x000d0024, 0x00000038 },
	{ 0x0000f0c0, 0x00000004 },
	{ 0x000d0026, 0x00000038 },
	{ 0x0000f0c1, 0x00000004 },
	{ 0x000d0028, 0x00000038 },
	{ 0x0000f041, 0x00000004 },
	{ 0x000d002a, 0x00000038 },
	{ 0x0000f184, 0x00000004 },
	{ 0x000d002c, 0x00000038 },
	{ 0x0000f185, 0x00000004 },
	{ 0x000d002e, 0x00000038 },
	{ 0x0000f186, 0x00000004 },
	{ 0x000d0030, 0x00000038 },
	{ 0x0000f187, 0x00000004 },
	{ 0x000d0032, 0x00000038 },
	{ 0x0000f180, 0x00000004 },
	{ 0x000d0034, 0x00000038 },
	{ 0x0000f393, 0x00000004 },
	{ 0x000d0036, 0x00000038 },
	{ 0x0000f38a, 0x00000004 },
	{ 0x000d0038, 0x00000038 },
	{ 0x0000f38e, 0x00000004 },
	{ 0x0000e821, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x00000043, 0x00000018 },
	{ 0x00cce800, 0x00000004 },
	{ 0x001b0001, 0x00000004 },
	{ 0x08004800, 0x00000004 },
	{ 0x001b0001, 0x00000004 },
	{ 0x08004800, 0x00000004 },
	{ 0x001b0001, 0x00000004 },
	{ 0x08004800, 0x00000004 },
	{ 0x0000003a, 0x00000008 },
	{ 0x0000a000, 0000000000 },
	{ 0x02c0a000, 0x00000004 },
	{ 0x000ca000, 0x00000004 },
	{ 0x00130000, 0x00000004 },
	{ 0x000c2000, 0x00000004 },
	{ 0xc980c045, 0x00000008 },
	{ 0x2000451d, 0x00000004 },
	{ 0x0000e580, 0x00000004 },
	{ 0x000ce581, 0x00000004 },
	{ 0x08004580, 0x00000004 },
	{ 0x000ce581, 0x00000004 },
	{ 0x0000004c, 0x00000008 },
	{ 0x0000a000, 0000000000 },
	{ 0x000c2000, 0x00000004 },
	{ 0x0000e50e, 0x00000004 },
	{ 0x00032000, 0x00000004 },
	{ 0x00022056, 0x00000028 },
	{ 0x00000056, 0x00000024 },
	{ 0x0800450f, 0x00000004 },
	{ 0x0000a050, 0x00000008 },
	{ 0x0000e565, 0x00000004 },
	{ 0x0000e566, 0x00000004 },
	{ 0x00000057, 0x00000008 },
	{ 0x03cca5b4, 0x00000004 },
	{ 0x05432000, 0x00000004 },
	{ 0x00022000, 0x00000004 },
	{ 0x4ccce063, 0x00000030 },
	{ 0x08274565, 0x00000004 },
	{ 0x00000063, 0x00000030 },
	{ 0x08004564, 0x00000004 },
	{ 0x0000e566, 0x00000004 },
	{ 0x0000005a, 0x00000008 },
	{ 0x00802066, 0x00000010 },
	{ 0x00202000, 0x00000004 },
	{ 0x001b00ff, 0x00000004 },
	{ 0x01000069, 0x00000010 },
	{ 0x001f2000, 0x00000004 },
	{ 0x001c00ff, 0x00000004 },
	{ 0000000000, 0x0000000c },
	{ 0x00000085, 0x00000030 },
	{ 0x0000005a, 0x00000008 },
	{ 0x0000e576, 0x00000004 },
	{ 0x000ca000, 0x00000004 },
	{ 0x00012000, 0x00000004 },
	{ 0x00082000, 0x00000004 },
	{ 0x1800650e, 0x00000004 },
	{ 0x00092000, 0x00000004 },
	{ 0x000a2000, 0x00000004 },
	{ 0x000f0000, 0x00000004 },
	{ 0x00400000, 0x00000004 },
	{ 0x00000079, 0x00000018 },
	{ 0x0000e563, 0x00000004 },
	{ 0x00c0e5f9, 0x000000c2 },
	{ 0x0000006e, 0x00000008 },
	{ 0x0000a06e, 0x00000008 },
	{ 0x0000e576, 0x00000004 },
	{ 0x0000e577, 0x00000004 },
	{ 0x0000e50e, 0x00000004 },
	{ 0x0000e50f, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x0000007c, 0x00000018 },
	{ 0x00c0e5f9, 0x000000c2 },
	{ 0x0000007c, 0x00000008 },
	{ 0x0014e50e, 0x00000004 },
	{ 0x0040e50f, 0x00000004 },
	{ 0x00c0007f, 0x00000008 },
	{ 0x0000e570, 0x00000004 },
	{ 0x0000e571, 0x00000004 },
	{ 0x0000e572, 0x0000000c },
	{ 0x0000a000, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x0000e568, 0x00000004 },
	{ 0x000c2000, 0x00000004 },
	{ 0x00000089, 0x00000018 },
	{ 0x000b0000, 0x00000004 },
	{ 0x18c0e562, 0x00000004 },
	{ 0x0000008b, 0x00000008 },
	{ 0x00c0008a, 0x00000008 },
	{ 0x000700e4, 0x00000004 },
	{ 0x00000097, 0x00000038 },
	{ 0x000ca099, 0x00000030 },
	{ 0x080045bb, 0x00000004 },
	{ 0x000c209a, 0x00000030 },
	{ 0x0800e5bc, 0000000000 },
	{ 0x0000e5bb, 0x00000004 },
	{ 0x0000e5bc, 0000000000 },
	{ 0x00120000, 0x0000000c },
	{ 0x00120000, 0x00000004 },
	{ 0x001b0002, 0x0000000c },
	{ 0x0000a000, 0x00000004 },
	{ 0x0000e821, 0x00000004 },
	{ 0x0000e800, 0000000000 },
	{ 0x0000e821, 0x00000004 },
	{ 0x0000e82e, 0000000000 },
	{ 0x02cca000, 0x00000004 },
	{ 0x00140000, 0x00000004 },
	{ 0x000ce1cc, 0x00000004 },
	{ 0x050de1cd, 0x00000004 },
	{ 0x000000a7, 0x00000020 },
	{ 0x4200e000, 0000000000 },
	{ 0x000000ae, 0x00000038 },
	{ 0x000ca000, 0x00000004 },
	{ 0x00140000, 0x00000004 },
	{ 0x000c2000, 0x00000004 },
	{ 0x00160000, 0x00000004 },
	{ 0x700ce000, 0x00000004 },
	{ 0x001400aa, 0x00000008 },
	{ 0x4000e000, 0000000000 },
	{ 0x02400000, 0x00000004 },
	{ 0x400ee000, 0x00000004 },
	{ 0x02400000, 0x00000004 },
	{ 0x4000e000, 0000000000 },
	{ 0x000c2000, 0x00000004 },
	{ 0x0240e51b, 0x00000004 },
	{ 0x0080e50a, 0x00000005 },
	{ 0x0080e50b, 0x00000005 },
	{ 0x00220000, 0x00000004 },
	{ 0x000700e4, 0x00000004 },
	{ 0x000000c1, 0x00000038 },
	{ 0x000c209a, 0x00000030 },
	{ 0x0880e5bd, 0x00000005 },
	{ 0x000c2099, 0x00000030 },
	{ 0x0800e5bb, 0x00000005 },
	{ 0x000c209a, 0x00000030 },
	{ 0x0880e5bc, 0x00000005 },
	{ 0x000000c4, 0x00000008 },
	{ 0x0080e5bd, 0x00000005 },
	{ 0x0000e5bb, 0x00000005 },
	{ 0x0080e5bc, 0x00000005 },
	{ 0x00210000, 0x00000004 },
	{ 0x02800000, 0x00000004 },
	{ 0x00c000c8, 0x00000018 },
	{ 0x4180e000, 0x00000040 },
	{ 0x000000ca, 0x00000024 },
	{ 0x01000000, 0x0000000c },
	{ 0x0100e51d, 0x0000000c },
	{ 0x000045bb, 0x00000004 },
	{ 0x000080c4, 0x00000008 },
	{ 0x0000f3ce, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x00cc2000, 0x00000004 },
	{ 0x08c053cf, 0x00000040 },
	{ 0x00008000, 0000000000 },
	{ 0x0000f3d2, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x00cc2000, 0x00000004 },
	{ 0x08c053d3, 0x00000040 },
	{ 0x00008000, 0000000000 },
	{ 0x0000f39d, 0x00000004 },
	{ 0x0140a000, 0x00000004 },
	{ 0x00cc2000, 0x00000004 },
	{ 0x08c0539e, 0x00000040 },
	{ 0x00008000, 0000000000 },
	{ 0x03c00830, 0x00000004 },
	{ 0x4200e000, 0000000000 },
	{ 0x0000a000, 0x00000004 },
	{ 0x200045e0, 0x00000004 },
	{ 0x0000e5e1, 0000000000 },
	{ 0x00000001, 0000000000 },
	{ 0x000700e1, 0x00000004 },
	{ 0x0800e394, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
	{ 0000000000, 0000000000 },
};

int RADEON_READ_PLL(drm_device_t *dev, int addr)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;

	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
}

#if RADEON_FIFO_DEBUG
static void radeon_status( drm_radeon_private_t *dev_priv )
{
	printk( "%s:\n", __FUNCTION__ );
	printk( "RBBM_STATUS = 0x%08x\n",
		(unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
	printk( "CP_RB_RTPR = 0x%08x\n",
		(unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
	printk( "CP_RB_WTPR = 0x%08x\n",
		(unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
	printk( "AIC_CNTL = 0x%08x\n",
		(unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
	printk( "AIC_STAT = 0x%08x\n",
		(unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
	printk( "AIC_PT_BASE = 0x%08x\n",
		(unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
	printk( "TLB_ADDR = 0x%08x\n",
		(unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
	printk( "TLB_DATA = 0x%08x\n",
		(unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
}
#endif


/* ================================================================
 * Engine, FIFO control
 */

static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
{
	u32 tmp;
	int i;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
	tmp |= RADEON_RB2D_DC_FLUSH_ALL;
	RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );

	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
		if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
		       & RADEON_RB2D_DC_BUSY) ) {
			return 0;
		}
		DRM_UDELAY( 1 );
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR( "failed!\n" );
	radeon_status( dev_priv );
#endif
	return DRM_ERR(EBUSY);
}

static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
				    int entries )
{
	int i;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
		int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
			      & RADEON_RBBM_FIFOCNT_MASK );
		if ( slots >= entries ) return 0;
		DRM_UDELAY( 1 );
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR( "failed!\n" );
	radeon_status( dev_priv );
#endif
	return DRM_ERR(EBUSY);
}

static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
{
	int i, ret;

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	ret = radeon_do_wait_for_fifo( dev_priv, 64 );
	if ( ret ) return ret;

	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
		if ( !(RADEON_READ( RADEON_RBBM_STATUS )
		       & RADEON_RBBM_ACTIVE) ) {
			radeon_do_pixcache_flush( dev_priv );
			return 0;
		}
		DRM_UDELAY( 1 );
	}

#if RADEON_FIFO_DEBUG
	DRM_ERROR( "failed!\n" );
	radeon_status( dev_priv );
#endif
	return DRM_ERR(EBUSY);
}


/* ================================================================
 * CP control, initialization
 */

/* Load the microcode for the CP */
static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
{
	int i;
	DRM_DEBUG( "\n" );

	radeon_do_wait_for_idle( dev_priv );

	RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );

	if (dev_priv->microcode_version==UCODE_R200) {
		DRM_INFO("Loading R200 Microcode\n");
		for ( i = 0 ; i < 256 ; i++ ) 
		{
			RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
				      R200_cp_microcode[i][1] );
			RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
				      R200_cp_microcode[i][0] );
		}
	} else if (dev_priv->microcode_version==UCODE_R300) {
		DRM_INFO("Loading R300 Microcode\n");
		for ( i = 0 ; i < 256 ; i++ ) {
			RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
				      R300_cp_microcode[i][1] );
			RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
				      R300_cp_microcode[i][0] );
		}
	} else {
		for ( i = 0 ; i < 256 ; i++ ) {
			RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
				      radeon_cp_microcode[i][1] );
			RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
				      radeon_cp_microcode[i][0] );
		}
	}
}

/* Flush any pending commands to the CP.  This should only be used just
 * prior to a wait for idle, as it informs the engine that the command
 * stream is ending.
 */
static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
{
	DRM_DEBUG( "\n" );
#if 0
	u32 tmp;

	tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
	RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
#endif
}

/* Wait for the CP to go idle.
 */
int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
{
	RING_LOCALS;
	DRM_DEBUG( "\n" );

	BEGIN_RING( 6 );

	RADEON_PURGE_CACHE();
	RADEON_PURGE_ZCACHE();
	RADEON_WAIT_UNTIL_IDLE();

	ADVANCE_RING();
	COMMIT_RING();

	return radeon_do_wait_for_idle( dev_priv );
}

/* Start the Command Processor.
 */
static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
{
	RING_LOCALS;
	DRM_DEBUG( "\n" );

	radeon_do_wait_for_idle( dev_priv );

	RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );

	dev_priv->cp_running = 1;

	BEGIN_RING( 6 );

	RADEON_PURGE_CACHE();
	RADEON_PURGE_ZCACHE();
	RADEON_WAIT_UNTIL_IDLE();

	ADVANCE_RING();
	COMMIT_RING();
}

/* Reset the Command Processor.  This will not flush any pending
 * commands, so you must wait for the CP command stream to complete
 * before calling this routine.
 */
static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
{
	u32 cur_read_ptr;
	DRM_DEBUG( "\n" );

	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
	SET_RING_HEAD( dev_priv, cur_read_ptr );
	dev_priv->ring.tail = cur_read_ptr;
}

/* Stop the Command Processor.  This will not flush any pending
 * commands, so you must flush the command stream and wait for the CP
 * to go idle before calling this routine.
 */
static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
{
	DRM_DEBUG( "\n" );

	RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

	dev_priv->cp_running = 0;
}

/* Reset the engine.  This will stop the CP if it is running.
 */
static int radeon_do_engine_reset( drm_device_t *dev )
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
	DRM_DEBUG( "\n" );

	radeon_do_pixcache_flush( dev_priv );

	clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
	mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );

	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
					      RADEON_FORCEON_MCLKA |
					      RADEON_FORCEON_MCLKB |
 					      RADEON_FORCEON_YCLKA |
					      RADEON_FORCEON_YCLKB |
					      RADEON_FORCEON_MC |
					      RADEON_FORCEON_AIC ) );

	rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );

	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
						RADEON_SOFT_RESET_CP |
						RADEON_SOFT_RESET_HI |
						RADEON_SOFT_RESET_SE |
						RADEON_SOFT_RESET_RE |
						RADEON_SOFT_RESET_PP |
						RADEON_SOFT_RESET_E2 |
						RADEON_SOFT_RESET_RB ) );
	RADEON_READ( RADEON_RBBM_SOFT_RESET );
	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
						~( RADEON_SOFT_RESET_CP |
						   RADEON_SOFT_RESET_HI |
						   RADEON_SOFT_RESET_SE |
						   RADEON_SOFT_RESET_RE |
						   RADEON_SOFT_RESET_PP |
						   RADEON_SOFT_RESET_E2 |
						   RADEON_SOFT_RESET_RB ) ) );
	RADEON_READ( RADEON_RBBM_SOFT_RESET );


	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
	RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
	RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );

	/* Reset the CP ring */
	radeon_do_cp_reset( dev_priv );

	/* The CP is no longer running after an engine reset */
	dev_priv->cp_running = 0;

	/* Reset any pending vertex, indirect buffers */
	radeon_freelist_reset( dev );

	return 0;
}

static void radeon_cp_init_ring_buffer( drm_device_t *dev,
				        drm_radeon_private_t *dev_priv )
{
	u32 ring_start, cur_read_ptr;
	u32 tmp;

	/* Initialize the memory controller */
	RADEON_WRITE( RADEON_MC_FB_LOCATION,
		      ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
		    | ( dev_priv->fb_location >> 16 ) );

#if __OS_HAS_AGP
	if (dev_priv->flags & CHIP_IS_AGP) {
		RADEON_WRITE( RADEON_MC_AGP_LOCATION,
			      (((dev_priv->gart_vm_start - 1 +
				 dev_priv->gart_size) & 0xffff0000) |
			       (dev_priv->gart_vm_start >> 16)) );

		ring_start = (dev_priv->cp_ring->offset
			      - dev->agp->base
			      + dev_priv->gart_vm_start);
	} else
#endif
		ring_start = (dev_priv->cp_ring->offset
			      - dev->sg->handle
			      + dev_priv->gart_vm_start);

	RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );

	/* Set the write pointer delay */
	RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );

	/* Initialize the ring buffer's read and write pointers */
	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
	SET_RING_HEAD( dev_priv, cur_read_ptr );
	dev_priv->ring.tail = cur_read_ptr;

#if __OS_HAS_AGP
	if (dev_priv->flags & CHIP_IS_AGP) {
		/* set RADEON_AGP_BASE here instead of relying on X from user space */
		RADEON_WRITE( RADEON_AGP_BASE, (unsigned int)dev->agp->base );
		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
			      dev_priv->ring_rptr->offset
			      - dev->agp->base
			      + dev_priv->gart_vm_start);
	} else
#endif
	{
		drm_sg_mem_t *entry = dev->sg;
		unsigned long tmp_ofs, page_ofs;

		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
		page_ofs = tmp_ofs >> PAGE_SHIFT;

		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
			     entry->busaddr[page_ofs]);
		DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
			   (unsigned long) entry->busaddr[page_ofs],
			   entry->handle + tmp_ofs );
	}

	/* Initialize the scratch register pointer.  This will cause
	 * the scratch register values to be written out to memory
	 * whenever they are updated.
	 *
	 * We simply put this behind the ring read pointer, this works
	 * with PCI GART as well as (whatever kind of) AGP GART
	 */
	RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
					 + RADEON_SCRATCH_REG_OFFSET );

	dev_priv->scratch = ((__volatile__ u32 *)
			     dev_priv->ring_rptr->handle +
			     (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));

	RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );

	/* Writeback doesn't seem to work everywhere, test it first */
	DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
	RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );

	for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
		if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
			break;
		DRM_UDELAY( 1 );
	}

	if ( tmp < dev_priv->usec_timeout ) {
		dev_priv->writeback_works = 1;
		DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
	} else {
		dev_priv->writeback_works = 0;
		DRM_DEBUG( "writeback test failed\n" );
	}

	dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
	RADEON_WRITE( RADEON_LAST_FRAME_REG,
		      dev_priv->sarea_priv->last_frame );

	dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
	RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
		      dev_priv->sarea_priv->last_dispatch );

	dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
	RADEON_WRITE( RADEON_LAST_CLEAR_REG,
		      dev_priv->sarea_priv->last_clear );

	/* Set ring buffer size */
#ifdef __BIG_ENDIAN
	RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
#else
	RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
#endif

	radeon_do_wait_for_idle( dev_priv );

	/* Turn on bus mastering */
	tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
	RADEON_WRITE( RADEON_BUS_CNTL, tmp );

	/* Sync everything up */
	RADEON_WRITE( RADEON_ISYNC_CNTL,
		      (RADEON_ISYNC_ANY2D_IDLE3D |
		       RADEON_ISYNC_ANY3D_IDLE2D |
		       RADEON_ISYNC_WAIT_IDLEGUI |
		       RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
}

/* Enable or disable PCI GART on the chip */
static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
{
	u32 tmp	= RADEON_READ( RADEON_AIC_CNTL );

	if ( on ) {
		RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );

		/* set PCI GART page-table base address
		 */
		RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );

		/* set address range for PCI address translate
		 */
		RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
		RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
						  + dev_priv->gart_size - 1);

		/* Turn off AGP aperture -- is this required for PCI GART?
		 */
		RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
		RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
	} else {
		RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
	}
}

static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	DRM_DEBUG( "\n" );

	if ( (!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg ) {
		DRM_ERROR( "PCI GART memory not allocated!\n" );
		radeon_do_cleanup_cp(dev);
		return DRM_ERR(EINVAL);
	}

	dev_priv->usec_timeout = init->usec_timeout;
	if ( dev_priv->usec_timeout < 1 ||
	     dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
		DRM_DEBUG( "TIMEOUT problem!\n" );
		radeon_do_cleanup_cp(dev);
		return DRM_ERR(EINVAL);
	}

	switch(init->func) {
	case RADEON_INIT_R200_CP:
		dev_priv->microcode_version=UCODE_R200;
		break;
	case RADEON_INIT_R300_CP:
		dev_priv->microcode_version=UCODE_R300;
		break;
	default:
		dev_priv->microcode_version=UCODE_R100;
		break;
	}

	dev_priv->do_boxes = 0;
	dev_priv->cp_mode = init->cp_mode;

	/* We don't support anything other than bus-mastering ring mode,
	 * but the ring can be in either AGP or PCI space for the ring
	 * read pointer.
	 */
	if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
	     ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
		DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
		radeon_do_cleanup_cp(dev);
		return DRM_ERR(EINVAL);
	}

	switch ( init->fb_bpp ) {
	case 16:
		dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
		break;
	case 32:
	default:
		dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
		break;
	}
	dev_priv->front_offset	= init->front_offset;
	dev_priv->front_pitch	= init->front_pitch;
	dev_priv->back_offset	= init->back_offset;
	dev_priv->back_pitch	= init->back_pitch;

	switch ( init->depth_bpp ) {
	case 16:
		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
		break;
	case 32:
	default:
		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
		break;
	}
	dev_priv->depth_offset	= init->depth_offset;
	dev_priv->depth_pitch	= init->depth_pitch;

	/* Hardware state for depth clears.  Remove this if/when we no
	 * longer clear the depth buffer with a 3D rectangle.  Hard-code
	 * all values to prevent unwanted 3D state from slipping through
	 * and screwing with the clear operation.
	 */
	dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
					   (dev_priv->color_fmt << 10) |
					   (dev_priv->microcode_version == UCODE_R100 ?
						RADEON_ZBLOCK16 : 0));

	dev_priv->depth_clear.rb3d_zstencilcntl = 
		(dev_priv->depth_fmt |
		 RADEON_Z_TEST_ALWAYS |
		 RADEON_STENCIL_TEST_ALWAYS |
		 RADEON_STENCIL_S_FAIL_REPLACE |
		 RADEON_STENCIL_ZPASS_REPLACE |
		 RADEON_STENCIL_ZFAIL_REPLACE |
		 RADEON_Z_WRITE_ENABLE);

	dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
					 RADEON_BFACE_SOLID |
					 RADEON_FFACE_SOLID |
					 RADEON_FLAT_SHADE_VTX_LAST |
					 RADEON_DIFFUSE_SHADE_FLAT |
					 RADEON_ALPHA_SHADE_FLAT |
					 RADEON_SPECULAR_SHADE_FLAT |
					 RADEON_FOG_SHADE_FLAT |
					 RADEON_VTX_PIX_CENTER_OGL |
					 RADEON_ROUND_MODE_TRUNC |
					 RADEON_ROUND_PREC_8TH_PIX);

	DRM_GETSAREA();

	dev_priv->fb_offset = init->fb_offset;
	dev_priv->mmio_offset = init->mmio_offset;
	dev_priv->ring_offset = init->ring_offset;
	dev_priv->ring_rptr_offset = init->ring_rptr_offset;
	dev_priv->buffers_offset = init->buffers_offset;
	dev_priv->gart_textures_offset = init->gart_textures_offset;
	
	if(!dev_priv->sarea) {
		DRM_ERROR("could not find sarea!\n");
		radeon_do_cleanup_cp(dev);
		return DRM_ERR(EINVAL);
	}

	dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
	if(!dev_priv->mmio) {
		DRM_ERROR("could not find mmio region!\n");
		radeon_do_cleanup_cp(dev);
		return DRM_ERR(EINVAL);
	}
	dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
	if(!dev_priv->cp_ring) {
		DRM_ERROR("could not find cp ring region!\n");
		radeon_do_cleanup_cp(dev);
		return DRM_ERR(EINVAL);
	}
	dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
	if(!dev_priv->ring_rptr) {
		DRM_ERROR("could not find ring read pointer!\n");
		radeon_do_cleanup_cp(dev);
		return DRM_ERR(EINVAL);
	}
	dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
	if(!dev->agp_buffer_map) {
		DRM_ERROR("could not find dma buffer region!\n");
		radeon_do_cleanup_cp(dev);
		return DRM_ERR(EINVAL);
	}

	if ( init->gart_textures_offset ) {
		dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
		if ( !dev_priv->gart_textures ) {
			DRM_ERROR("could not find GART texture region!\n");
			radeon_do_cleanup_cp(dev);
			return DRM_ERR(EINVAL);
		}
	}

	dev_priv->sarea_priv =
		(drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
				       init->sarea_priv_offset);

#if __OS_HAS_AGP
	if ( dev_priv->flags & CHIP_IS_AGP ) {
		drm_core_ioremap( dev_priv->cp_ring, dev );
		drm_core_ioremap( dev_priv->ring_rptr, dev );
		drm_core_ioremap( dev->agp_buffer_map, dev );
		if(!dev_priv->cp_ring->handle ||
		   !dev_priv->ring_rptr->handle ||
		   !dev->agp_buffer_map->handle) {
			DRM_ERROR("could not find ioremap agp regions!\n");
			radeon_do_cleanup_cp(dev);
			return DRM_ERR(EINVAL);
		}
	} else
#endif
	{
		dev_priv->cp_ring->handle =
			(void *)dev_priv->cp_ring->offset;
		dev_priv->ring_rptr->handle =
			(void *)dev_priv->ring_rptr->offset;
		dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;

		DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
			   dev_priv->cp_ring->handle );
		DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
			   dev_priv->ring_rptr->handle );
		DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
			   dev->agp_buffer_map->handle );
	}

	dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
				& 0xffff ) << 16;

	dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
					( ( dev_priv->front_offset
					  + dev_priv->fb_location ) >> 10 ) );

	dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
				       ( ( dev_priv->back_offset
					 + dev_priv->fb_location ) >> 10 ) );

	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
					( ( dev_priv->depth_offset
					  + dev_priv->fb_location ) >> 10 ) );


	dev_priv->gart_size = init->gart_size;
	dev_priv->gart_vm_start = dev_priv->fb_location
				+ RADEON_READ( RADEON_CONFIG_APER_SIZE );

#if __OS_HAS_AGP
	if (dev_priv->flags & CHIP_IS_AGP)
		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
						- dev->agp->base
						+ dev_priv->gart_vm_start);
	else
#endif
		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
						- dev->sg->handle
						+ dev_priv->gart_vm_start);

	DRM_DEBUG( "dev_priv->gart_size %d\n",
		   dev_priv->gart_size );
	DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
		   dev_priv->gart_vm_start );
	DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
		   dev_priv->gart_buffers_offset );

	dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
	dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
			      + init->ring_size / sizeof(u32));
	dev_priv->ring.size = init->ring_size;
	dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );

	dev_priv->ring.tail_mask =
		(dev_priv->ring.size / sizeof(u32)) - 1;

	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;

#if __OS_HAS_AGP
	if (dev_priv->flags & CHIP_IS_AGP) {
		/* Turn off PCI GART */
		radeon_set_pcigart( dev_priv, 0 );
	} else
#endif
	{
		if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
					    &dev_priv->bus_pci_gart)) {
			DRM_ERROR( "failed to init PCI GART!\n" );
			radeon_do_cleanup_cp(dev);
			return DRM_ERR(ENOMEM);
		}

		/* Turn on PCI GART */
		radeon_set_pcigart( dev_priv, 1 );
	}

	radeon_cp_load_microcode( dev_priv );
	radeon_cp_init_ring_buffer( dev, dev_priv );

	dev_priv->last_buf = 0;

	radeon_do_engine_reset( dev );

	return 0;
}

int radeon_do_cleanup_cp( drm_device_t *dev )
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	DRM_DEBUG( "\n" );

	/* Make sure interrupts are disabled here because the uninstall ioctl
	 * may not have been called from userspace and after dev_private
	 * is freed, it's too late.
	 */
	if ( dev->irq_enabled ) DRM(irq_uninstall)(dev);

#if __OS_HAS_AGP
	if (dev_priv->flags & CHIP_IS_AGP) {
		if ( dev_priv->cp_ring != NULL ) {
			drm_core_ioremapfree( dev_priv->cp_ring, dev );
			dev_priv->cp_ring = NULL;
		}
		if ( dev_priv->ring_rptr != NULL ) {
			drm_core_ioremapfree( dev_priv->ring_rptr, dev );
			dev_priv->ring_rptr = NULL;
		}
		if ( dev->agp_buffer_map != NULL ) {
			drm_core_ioremapfree( dev->agp_buffer_map, dev );
			dev->agp_buffer_map = NULL;
		}
	} else
#endif
	{
		if (!DRM(ati_pcigart_cleanup)( dev,
					       dev_priv->phys_pci_gart,
					       dev_priv->bus_pci_gart ))
			DRM_ERROR( "failed to cleanup PCI GART!\n" );
	}
	/* only clear to the start of flags */
	memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));

	return 0;
}

/* This code will reinit the Radeon CP hardware after a resume from disc.  
 * AFAIK, it would be very difficult to pickle the state at suspend time, so 
 * here we make sure that all Radeon hardware initialisation is re-done without
 * affecting running applications.
 *
 * Charl P. Botha <http://cpbotha.net>
 */
static int radeon_do_resume_cp( drm_device_t *dev )
{
	drm_radeon_private_t *dev_priv = dev->dev_private;

	if ( !dev_priv ) {
		DRM_ERROR( "Called with no initialization\n" );
		return DRM_ERR( EINVAL );
	}

	DRM_DEBUG("Starting radeon_do_resume_cp()\n");

#if __OS_HAS_AGP
	if (dev_priv->flags & CHIP_IS_AGP) {
		/* Turn off PCI GART */
		radeon_set_pcigart( dev_priv, 0 );
	} else
#endif
	{
		/* Turn on PCI GART */
		radeon_set_pcigart( dev_priv, 1 );
	}

	radeon_cp_load_microcode( dev_priv );
	radeon_cp_init_ring_buffer( dev, dev_priv );

	radeon_do_engine_reset( dev );

	DRM_DEBUG("radeon_do_resume_cp() complete\n");

	return 0;
}


int radeon_cp_init( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_radeon_init_t init;

	LOCK_TEST_WITH_RETURN( dev, filp );

	DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );

	switch ( init.func ) {
	case RADEON_INIT_CP:
	case RADEON_INIT_R200_CP:
	case RADEON_INIT_R300_CP:
		return radeon_do_init_cp( dev, &init );
	case RADEON_CLEANUP_CP:
		return radeon_do_cleanup_cp( dev );
	}

	return DRM_ERR(EINVAL);
}

int radeon_cp_start( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_radeon_private_t *dev_priv = dev->dev_private;
	DRM_DEBUG( "\n" );

	LOCK_TEST_WITH_RETURN( dev, filp );

	if ( dev_priv->cp_running ) {
		DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
		return 0;
	}
	if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
		DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
			   __FUNCTION__, dev_priv->cp_mode );
		return 0;
	}

	radeon_do_cp_start( dev_priv );

	return 0;
}

/* Stop the CP.  The engine must have been idled before calling this
 * routine.
 */
int radeon_cp_stop( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_cp_stop_t stop;
	int ret;
	DRM_DEBUG( "\n" );

	LOCK_TEST_WITH_RETURN( dev, filp );

	DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );

	if (!dev_priv->cp_running)
		return 0;

	/* Flush any pending CP commands.  This ensures any outstanding
	 * commands are exectuted by the engine before we turn it off.
	 */
	if ( stop.flush ) {
		radeon_do_cp_flush( dev_priv );
	}

	/* If we fail to make the engine go idle, we return an error
	 * code so that the DRM ioctl wrapper can try again.
	 */
	if ( stop.idle ) {
		ret = radeon_do_cp_idle( dev_priv );
		if ( ret ) return ret;
	}

	/* Finally, we can turn off the CP.  If the engine isn't idle,
	 * we will get some dropped triangles as they won't be fully
	 * rendered before the CP is shut down.
	 */
	radeon_do_cp_stop( dev_priv );

	/* Reset the engine */
	radeon_do_engine_reset( dev );

	return 0;
}


void radeon_do_release( drm_device_t *dev )
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	int i, ret;

	if (dev_priv) {

		if (dev_priv->cp_running) {
			/* Stop the cp */
			while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
				DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
#ifdef __linux__
				schedule();
#else
				tsleep(&ret, PZERO, "rdnrel", 1);
#endif
			}