/* * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sub license, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "drmP.h" #include "via_ds.h" extern unsigned int VIA_DEBUG; set_t *via_setInit(void) { int i; set_t *set; set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER); for (i = 0; i < SET_SIZE; i++) { set->list[i].free_next = i + 1; set->list[i].alloc_next = -1; } set->list[SET_SIZE - 1].free_next = -1; set->free = 0; set->alloc = -1; set->trace = -1; return set; } int via_setAdd(set_t * set, ITEM_TYPE item) { int free = set->free; if (free != -1) { set->list[free].val = item; set->free = set->list[free].free_next; } else { return 0; } set->list[free].alloc_next = set->alloc; set->alloc = free; set->list[free].free_next = -1; return 1; } int via_setDel(set_t * set, ITEM_TYPE item) { int alloc = set->alloc; int prev = -1; while (alloc != -1) { if (set->list[alloc].val == item) { if (prev != -1) set->list[prev].alloc_next = set->list[alloc].alloc_next; else set->alloc = set->list[alloc].alloc_next; break; } prev = alloc; alloc = set->list[alloc].alloc_next; } if (alloc == -1) return 0; set->list[alloc].free_next = set->free; set->free = alloc; set->list[alloc].alloc_next = -1; return 1; } /* setFirst -> setAdd -> setNext is wrong */ int via_setFirst(set_t * set, ITEM_TYPE * item) { if (set->alloc == -1) return 0; *item = set->list[set->alloc].val; set->trace = set->list[set->alloc].alloc_next; return 1; } int via_setNext(set_t * set, ITEM_TYPE * item) { if (set->trace == -1) return 0; *item = set->list[set->trace].val; set->trace = set->list[set->trace].alloc_next; return 1; } int via_setDestroy(set_t * set) { drm_free(set, sizeof(set_t), DRM_MEM_DRIVER); return 1; } #define ISFREE(bptr) ((bptr)->free) #define fprintf(fmt, arg...) do{}while(0) memHeap_t *via_mmInit(int ofs, int size) { PMemBlock blocks; if (size <= 0) return NULL; blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); if (blocks) { blocks->ofs = ofs; blocks->size = size; blocks->free = 1; return (memHeap_t *) blocks; } else return NULL; } static TMemBlock *SliceBlock(TMemBlock * p, int startofs, int size, int reserved, int alignment) { TMemBlock *newblock; /* break left */ if (startofs > p->ofs) { newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); newblock->ofs = startofs; newblock->size = p->size - (startofs - p->ofs); newblock->free = 1; newblock->next = p->next; p->size -= newblock->size; p->next = newblock; p = newblock; } /* break right */ if (size < p->size) { newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); newblock->ofs = startofs + size; newblock->size = p->size - size; newblock->free = 1; newblock->next = p->next; p->size = size; p->next = newblock; } /* p = middle block */ p->align = alignment; p->free = 0; p->reserved = reserved; return p; } PMemBlock via_mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch) { int mask, startofs, endofs; TMemBlock *p; if (!heap || align2 < 0 || size <= 0) return NULL; mask = (1 << align2) - 1; startofs = 0; p = (TMemBlock *) heap; while (p) { if (ISFREE(p)) { startofs = (p->ofs + mask) & ~mask; if (startofs < startSearch) startofs = startSearch; endofs = startofs + size; if (endofs <= (p->ofs + p->size)) break; } p = p->next; } if (!p) return NULL; p = SliceBlock(p, startofs, size, 0, mask + 1); p->heap = heap; return p; } static __inline__ int Join2Blocks(TMemBlock * p) { if (p->free && p->next && p->next->free) { TMemBlock *q = p->next; p->size += q->size; p->next = q->next; drm_free(q, sizeof(TMemBlock), DRM_MEM_DRIVER); return 1; } return 0; } int via_mmFreeMem(PMemBlock b) { TMemBlock *p, *prev; if (!b) return 0; if (!b->heap) { fprintf(stderr, "no heap\n"); return -1; } p = b->heap; prev = NULL; while (p && p != b) { prev = p; p = p->next; } if (!p || p->free || p->reserved) { if (!p) fprintf(stderr, "block not found in heap\n"); else if (p->free) fprintf(stderr, "block already free\n"); else fprintf(stderr, "block is reserved\n"); return -1; } p->free = 1; Join2Blocks(p); if (prev) Join2Blocks(prev); return 0; } ' href='#n85'>85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169
/*
* Copyright (C) 2007 Ben Skeggs.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
NV10_RAMFC_##offset/4, (val))
#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
NV10_RAMFC_##offset/4)
#define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE))
#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
int
nv10_fifo_channel_id(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
NV10_PFIFO_CACHE1_PUSH1_CHID_MASK);
}
int
nv10_fifo_create_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
int ret;
if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0,
NV10_RAMFC__SIZE,
NVOBJ_FLAG_ZERO_ALLOC |
NVOBJ_FLAG_ZERO_FREE,
NULL, &chan->ramfc)))
return ret;
/* Fill entries that are seen filled in dumps of nvidia driver just
* after channel's is put into DMA mode
*/
RAMFC_WR(DMA_PUT , chan->pushbuf_base);
RAMFC_WR(DMA_GET , chan->pushbuf_base);
RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4);
RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACHE1_BIG_ENDIAN |
#endif
0);
/* enable the fifo dma operation */
NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
return 0;
}
void
nv10_fifo_destroy_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
nouveau_gpuobj_ref_del(dev, &chan->ramfc);
}
int
nv10_fifo_load_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t tmp;
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT));
NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT));
tmp = RAMFC_RD(DMA_INSTANCE);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , tmp & 0xFFFF);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , tmp >> 16);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , RAMFC_RD(DMA_FETCH));
NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE));
NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE));
if (dev_priv->chipset >= 0x17) {
NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE,
RAMFC_RD(ACQUIRE_VALUE));
NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP,
RAMFC_RD(ACQUIRE_TIMESTAMP));
NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT,
RAMFC_RD(ACQUIRE_TIMEOUT));
NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE,
RAMFC_RD(SEMAPHORE));
NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE,
RAMFC_RD(DMA_SUBROUTINE));
}
/* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
return 0;
}
int
nv10_fifo_save_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t tmp;
RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
tmp |= (NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
RAMFC_WR(DMA_INSTANCE , tmp);
RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
if (dev_priv->chipset >= 0x17) {
RAMFC_WR(ACQUIRE_VALUE,
NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
RAMFC_WR(ACQUIRE_TIMESTAMP,
NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
RAMFC_WR(ACQUIRE_TIMEOUT,
NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
RAMFC_WR(SEMAPHORE,
NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
RAMFC_WR(DMA_SUBROUTINE,
NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
}
return 0;
}