/* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- */ /* * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Keith Whitwell * Eric Anholt */ #include "drmP.h" #include "drm.h" #include "r128_drm.h" #include "r128_drv.h" u32 r128_get_vblank_counter(struct drm_device *dev, int crtc) { const drm_r128_private_t *dev_priv = dev->dev_private; if (crtc != 0) return 0; return atomic_read(&dev_priv->vbl_received); } irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS) { struct drm_device *dev = (struct drm_device *) arg; drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; int status; status = R128_READ(R128_GEN_INT_STATUS); /* VBLANK interrupt */ if (status & R128_CRTC_VBLANK_INT) { R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); atomic_inc(&dev_priv->vbl_received); drm_handle_vblank(dev, 0); return IRQ_HANDLED; } return IRQ_NONE; } int r128_enable_vblank(struct drm_device *dev, int crtc) { drm_r128_private_t *dev_priv = dev->dev_private; if (crtc != 0) { DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc); return -EINVAL; } R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN); return 0; } void r128_disable_vblank(struct drm_device *dev, int crtc) { if (crtc != 0) DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc); /* * FIXME: implement proper interrupt disable by using the vblank * counter register (if available) * * R128_WRITE(R128_GEN_INT_CNTL, * R128_READ(R128_GEN_INT_CNTL) & ~R128_CRTC_VBLANK_INT_EN); */ } void r128_driver_irq_preinstall(struct drm_device * dev) { drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; /* Disable *all* interrupts */ R128_WRITE(R128_GEN_INT_CNTL, 0); /* Clear vblank bit if it's already high */ R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); } int r128_driver_irq_postinstall(struct drm_device * dev) { return drm_vblank_init(dev, 1); } void r128_driver_irq_uninstall(struct drm_device * dev) { drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; if (!dev_priv) return; /* Disable *all* interrupts */ R128_WRITE(R128_GEN_INT_CNTL, 0); } ='n19' href='#n19'>19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169

/**************************************************************************
 *
 * Copyright (c) 2007 Tungsten Graphics, Inc., Cedar Park, TX., USA,
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 *
 **************************************************************************/
/*
 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
 */

#include "drmP.h"
#include "via_drm.h"
#include "via_drv.h"

/*
 * DRM_FENCE_TYPE_EXE guarantees that all command buffers can be evicted.
 * DRM_VIA_FENCE_TYPE_ACCEL guarantees that all 2D & 3D rendering is complete.
 */

static void via_fence_poll(struct drm_device *dev, uint32_t class,
			   uint32_t waiting_types)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	uint32_t signaled_flush_types = 0;
	uint32_t status;

	if (class != 0)
		return;

	if (unlikely(!dev_priv))
		return;

	spin_lock(&dev_priv->fence_lock);
	if (waiting_types) {

		/*
		 * Take the idlelock. This guarantees that the next time a client tries
		 * to grab the lock, it will stall until the idlelock is released. This
		 * guarantees that eventually, the GPU engines will be idle, but nothing
		 * else. It cannot be used to protect the hardware.
		 */


		if (!dev_priv->have_idlelock) {
			drm_idlelock_take(&dev->lock);
			dev_priv->have_idlelock = 1;
		}

		/*
		 * Check if AGP command reader is idle.
		 */

		if (waiting_types & DRM_FENCE_TYPE_EXE)
			if (VIA_READ(0x41C) & 0x80000000)
				signaled_flush_types |= DRM_FENCE_TYPE_EXE;

		/*
		 * Check VRAM command queue empty and 2D + 3D engines idle.
		 */

		if (waiting_types & DRM_VIA_FENCE_TYPE_ACCEL) {
			status = VIA_READ(VIA_REG_STATUS);
			if ((status & VIA_VR_QUEUE_BUSY) &&
			    !(status & (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)))
				signaled_flush_types |= DRM_VIA_FENCE_TYPE_ACCEL;
		}

		if (signaled_flush_types) {
			waiting_types &= ~signaled_flush_types;
			if (!waiting_types && dev_priv->have_idlelock) {
				drm_idlelock_release(&dev->lock);
				dev_priv->have_idlelock = 0;
			}
			drm_fence_handler(dev, 0, dev_priv->emit_0_sequence,
					  signaled_flush_types, 0);
		}
	}

	spin_unlock(&dev_priv->fence_lock);

	return;
}


/**
 * Emit a fence sequence.
 */

static int via_fence_emit_sequence(struct drm_device * dev, uint32_t class, uint32_t flags,
				   uint32_t * sequence, uint32_t * native_type)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	int ret = 0;

	if (!dev_priv)
		return -EINVAL;

	switch(class) {
	case 0: /* AGP command stream */

		/*
		 * The sequence number isn't really used by the hardware yet.
		 */

		spin_lock(&dev_priv->fence_lock);
		*sequence = ++dev_priv->emit_0_sequence;
		spin_unlock(&dev_priv->fence_lock);

		/*
		 * When drm_fence_handler() is called with flush type 0x01, and a
		 * sequence number, That means that the EXE flag is expired.
		 * Nothing else. No implicit flushing or other engines idle.
		 */

		*native_type = DRM_FENCE_TYPE_EXE;
		break;
	default:
		ret = -EINVAL;
		break;
	}
	return ret;
}

/**
 * No irq fence expirations implemented yet.
 * Although both the HQV engines and PCI dmablit engines signal
 * idle with an IRQ, we haven't implemented this yet.
 * This means that the drm fence manager will always poll for engine idle,
 * unless the caller wanting to wait for a fence object has indicated a lazy wait.
 */

static int via_fence_has_irq(struct drm_device * dev, uint32_t class,
			     uint32_t flags)
{
	return 0;
}

struct drm_fence_driver via_fence_driver = {
	.num_classes = 1,
	.wrap_diff = (1 << 30),
	.flush_diff = (1 << 20),
	.sequence_mask = 0xffffffffU,
	.has_irq = via_fence_has_irq,
	.emit = via_fence_emit_sequence,
	.poll = via_fence_poll,
	.needed_flush = NULL,
	.wait = NULL
};