/*
* Copyright 2005 Stephane Marchesin.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __NOUVEAU_DRV_H__
#define __NOUVEAU_DRV_H__
#define DRIVER_AUTHOR "Stephane Marchesin"
#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
#define DRIVER_NAME "nouveau"
#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
#define DRIVER_DATE "20060213"
#define DRIVER_MAJOR 0
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 10
#define NOUVEAU_FAMILY 0x0000FFFF
#define NOUVEAU_FLAGS 0xFFFF0000
#include "nouveau_drm.h"
#include "nouveau_reg.h"
struct mem_block {
struct mem_block *next;
struct mem_block *prev;
uint64_t start;
uint64_t size;
struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
int flags;
drm_local_map_t *map;
drm_handle_t map_handle;
};
enum nouveau_flags {
NV_NFORCE =0x10000000,
NV_NFORCE2 =0x20000000
};
#define NVOBJ_ENGINE_SW 0
#define NVOBJ_ENGINE_GR 1
#define NVOBJ_ENGINE_INT 0xdeadbeef
#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
#define NVOBJ_FLAG_FAKE (1 << 3)
struct nouveau_gpuobj {
struct list_head list;
int im_channel;
struct mem_block *im_pramin;
struct mem_block *im_backing;
int im_bound;
uint32_t flags;
int refcount;
uint32_t engine;
uint32_t class;
void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
void *priv;
};
struct nouveau_gpuobj_ref {
struct list_head list;
struct nouveau_gpuobj *gpuobj;
uint32_t instance;
int channel;
int handle;
};
struct nouveau_channel
{
struct drm_device *dev;
int id;
/* owner of this fifo */
struct drm_file *file_priv;
/* mapping of the fifo itself */
drm_local_map_t *map;
/* mapping of the regs controling the fifo */
drm_local_map_t *regs;
/* Fencing */
uint32_t next_sequence;
/* DMA push buffer */
struct nouveau_gpuobj_ref *pushbuf;
struct mem_block *pushbuf_mem;
uint32_t pushbuf_base;
/* FIFO user control regs */
uint32_t user, user_size;
uint32_t put;
uint32_t get;
uint32_t ref_cnt;
/* Notifier memory */
struct mem_block *notifier_block;
struct mem_block *notifier_heap;
drm_local_map_t *notifier_map;
/* PFIFO context */
struct nouveau_gpuobj_ref *ramfc;
/* PGRAPH context */
/* XXX may be merge 2 pointers as private data ??? */
struct nouveau_gpuobj_ref *ramin_grctx;
void *pgraph_ctx;
/* NV50 VM */
struct nouveau_gpuobj *vm_pd;
struct nouveau_gpuobj_ref *vm_gart_pt;
/* Objects */
struct nouveau_gpuobj_ref *ramin; /* Private instmem */
struct mem_block *ramin_heap; /* Private PRAMIN heap */
struct nouveau_gpuobj_ref *ramht; /* Hash table */
struct list_head ramht_refs; /* Objects referenced by RAMHT */
};
struct nouveau_drm_channel {
struct nouveau_channel *chan;
/* DMA state */
int max, put, cur, free;
int push_free;
volatile uint32_t *pushbuf;
/* Notifiers */
uint32_t notify0_offset;
/* Buffer moves */
uint32_t m2mf_dma_source;
uint32_t m2mf_dma_destin;
};
struct nouveau_config {
struct {
int location;
int size;
} cmdbuf;
};
struct nouveau_instmem_engine {
void *priv;
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
uint32_t *size);
void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
};
struct nouveau_mc_engine {
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
};
struct nouveau_timer_engine {
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
uint64_t (*read)(struct drm_device *dev);
};
struct nouveau_fb_engine {
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
};
struct nouveau_fifo_engine {
void *priv;
int channels;
int (*init)(struct drm_device *);
void (*takedown)(struct drm_device *);
int (*channel_id)(struct drm_device *);
int (*create_context)(struct nouveau_channel *);
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
int (*save_context)(struct nouveau_channel *);
};
struct nouveau_pgraph_engine {
int (*init)(struct drm_device *);
void (*takedown)(struct drm_device *);
int (*create_context)(struct nouveau_channel *);
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
int (*save_context)(struct nouveau_channel *);
};
struct nouveau_engine {
struct nouveau_instmem_engine instmem;
struct nouveau_mc_engine mc;
struct nouveau_timer_engine timer;
struct nouveau_fb_engine fb;
struct nouveau_pgraph_engine graph;
struct nouveau_fifo_engine fifo;
};
#define NOUVEAU_MAX_CHANNEL_NR 128
struct drm_nouveau_private {
enum {
NOUVEAU_CARD_INIT_DOWN,
NOUVEAU_CARD_INIT_DONE,
NOUVEAU_CARD_INIT_FAILED
} init_state;
int ttm;
/* the card type, takes NV_* as values */
int card_type;
/* exact chipset, derived from NV_PMC_BOOT_0 */
int chipset;
int flags;
drm_local_map_t *mmio;
drm_local_map_t *fb;
drm_local_map_t *ramin; /* NV40 onwards */
int fifo_alloc_count;
struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
struct nouveau_engine Engine;
struct nouveau_drm_channel channel;
/* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
struct nouveau_gpuobj *ramht;
uint32_t ramin_rsvd_vram;
uint32_t ramht_offset;
uint32_t ramht_size;
uint32_t ramht_bits;
uint32_t ramfc_offset;
uint32_t ramfc_size;
uint32_t ramro_offset;
uint32_t ramro_size;
/* base physical adresses */
uint64_t fb_phys;
uint64_t fb_available_size;
struct {
enum {
NOUVEAU_GART_NONE = 0,
NOUVEAU_GART_AGP,
NOUVEAU_GART_SGDMA
} type;
uint64_t aper_base;
uint64_t aper_size;
struct nouveau_gpuobj *sg_ctxdma;
struct page *sg_dummy_page;
dma_addr_t sg_dummy_bus;
/* nottm hack */
struct drm_ttm_backend *sg_be;
unsigned long sg_handle;
} gart_info;
/* the mtrr covering the FB */
int fb_mtrr;
struct mem_block *agp_heap;
struct mem_block *fb_heap;
struct mem_block *fb_nomap_heap;
struct mem_block *ramin_heap;
struct mem_block *pci_heap;
/* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
uint32_t ctx_table_size;
struct nouveau_gpuobj_ref *ctx_table;
struct nouveau_config config;
struct list_head gpuobj_list;
};
#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
struct drm_nouveau_private *nv = dev->dev_private; \
if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
DRM_ERROR("called without init\n"); \
return -EINVAL; \
} \
} while(0)
#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
struct drm_nouveau_private *nv = dev->dev_private; \
if (!nouveau_fifo_owner(dev, (cl), (id))) { \
DRM_ERROR("pid %d doesn't own channel %d\n", \
DRM_CURRENTPID, (id)); \
return -EPERM; \
} \
(ch) = nv->fifos[(id)]; \
} while(0)
/* nouveau_state.c */
extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
extern int nouveau_load(struct drm_device *, unsigned long flags);
extern int nouveau_firstopen(struct drm_device *);
extern void nouveau_lastclose(struct drm_device *);
extern int nouveau_unload(struct drm_device *);
extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
struct drm_file *);
extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
struct drm_file *);
extern void nouveau_wait_for_idle(struct drm_device *);
extern int nouveau_card_init(struct drm_device *);
extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
struct drm_file *);
/* nouveau_mem.c */
extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
uint64_t size);
extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
uint64_t size, int align2,
struct drm_file *);
extern void nouveau_mem_takedown(struct mem_block **heap);
extern void nouveau_mem_free_block(struct mem_block *);
extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
struct drm_file *);
extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
struct drm_file *);
extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
int alignment, uint64_t size,
int flags, struct drm_file *);
extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
extern int nouveau_mem_init(struct drm_device *);
extern int nouveau_mem_init_ttm(struct drm_device *);
extern void nouveau_mem_close(struct drm_device *);
/* nouveau_notifier.c */
extern int nouveau_notifier_init_channel(struct nouveau_channel *);
extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
int cout, uint32_t *offset);
extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
struct drm_file *);
extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
struct drm_file *);
/* nouveau_fifo.c */
extern int nouveau_fifo_init(struct drm_device *);
extern int nouveau_fifo_ctx_size(struct drm_device *);
extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
int channel);
extern int nouveau_fifo_alloc(struct drm_device *dev,
struct nouveau_channel **chan,
struct drm_file *file_priv,
struct mem_block *pushbuf,
uint32_t fb_ctxdma, uint32_t tt_ctxdma);
extern void nouveau_fifo_free(struct nouveau_channel *);
/* nouveau_object.c */
extern int nouveau_gpuobj_early_init(struct drm_device *);
extern int nouveau_gpuobj_init(struct drm_device *);
extern void nouveau_gpuobj_takedown(struct drm_device *);
extern void nouveau_gpuobj_late_takedown(struct drm_device *);
extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
uint32_t vram_h, uint32_t tt_h);
extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
int size, int align, uint32_t flags,
struct nouveau_gpuobj **);
extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
uint32_t handle, struct nouveau_gpuobj *,
struct nouveau_gpuobj_ref **);
extern int nouveau_gpuobj_ref_del(struct drm_device *,
struct nouveau_gpuobj_ref **);
extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
struct nouveau_gpuobj_ref **ref_ret);
extern int nouveau_gpuobj_new_ref(struct drm_device *,
struct nouveau_channel *alloc_chan,
struct nouveau_channel *ref_chan,
uint32_t handle, int size, int align,
uint32_t flags, struct nouveau_gpuobj_ref **);
extern int nouveau_gpuobj_new_fake(struct drm_device *,
uint32_t p_offset, uint32_t b_offset,
uint32_t size, uint32_t flags,
struct nouveau_gpuobj **,
struct nouveau_gpuobj_ref**);
extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
uint64_t offset, uint64_t size, int access,
int target, struct nouveau_gpuobj **);
extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
uint64_t offset, uint64_t size,
int access, struct nouveau_gpuobj **,
uint32_t *o_ret);
extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
struct nouveau_gpuobj **);
extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
struct drm_file *);
extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
struct drm_file *);
/* nouveau_irq.c */
extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
extern void nouveau_irq_preinstall(struct drm_device *);
extern int nouveau_irq_postinstall(struct drm_device *);
extern void nouveau_irq_uninstall(struct drm_device *);
/* nouveau_sgdma.c */
extern int nouveau_sgdma_init(struct drm_device *);
extern void nouveau_sgdma_takedown(struct drm_device *);
extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
uint32_t *page);
extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
/* nouveau_dma.c */
extern int nouveau_dma_channel_init(struct drm_device *);
extern void nouveau_dma_channel_takedown(struct drm_device *);
extern int nouveau_dma_wait(struct drm_device *, int size);
/* nv04_fb.c */
extern int nv04_fb_init(struct drm_device *);
extern void nv04_fb_takedown(struct drm_device *);
/* nv10_fb.c */
extern int nv10_fb_init(struct drm_device *);
extern void nv10_fb_takedown(struct drm_device *);
/* nv40_fb.c */
extern int nv40_fb_init(struct drm_device *);
extern void nv40_fb_takedown(struct drm_device *);
/* nv04_fifo.c */
extern int nv04_fifo_channel_id(struct drm_device *);
extern int nv04_fifo_create_context(struct nouveau_channel *);
extern void nv04_fifo_destroy_context(struct nouveau_channel *);
extern int nv04_fifo_load_context(struct nouveau_channel *);
extern int nv04_fifo_save_context(struct nouveau_channel *);
/* nv10_fifo.c */
extern int nv10_fifo_channel_id(struct drm_device *);
extern int nv10_fifo_create_context(struct nouveau_channel *);
extern void nv10_fifo_destroy_context(struct nouveau_channel *);
extern int nv10_fifo_load_context(struct nouveau_channel *);
extern int nv10_fifo_save_context(struct nouveau_channel *);
/* nv40_fifo.c */
extern int nv40_fifo_init(struct drm_device *);
extern int nv40_fifo_create_context(struct nouveau_channel *);
extern void nv40_fifo_destroy_context(struct nouveau_channel *);
extern int nv40_fifo_load_context(struct nouveau_channel *);
extern int nv40_fifo_save_context(struct nouveau_channel *);
/* nv50_fifo.c */
extern int nv50_fifo_init(struct drm_device *);
extern void nv50_fifo_takedown(struct drm_device *);
extern int nv50_fifo_channel_id(struct drm_device *);
extern int nv50_fifo_create_context(struct nouveau_channel *);
extern void nv50_fifo_destroy_context(struct nouveau_channel *);
extern int nv50_fifo_load_context(struct nouveau_channel *);
extern int nv50_fifo_save_context(struct nouveau_channel *);
/* nv04_graph.c */
extern void nouveau_nv04_context_switch(struct drm_device *);
extern int nv04_graph_init(struct drm_device *);
extern void nv04_graph_takedown(struct drm_device *);
extern int nv04_graph_create_context(struct nouveau_channel *);
extern void nv04_graph_destroy_context(struct nouveau_channel *);
extern int nv04_graph_load_context(struct nouveau_channel *);
extern int nv04_graph_save_context(struct nouveau_channel *);
/* nv10_graph.c */
extern void nouveau_nv10_context_switch(struct drm_device *);
extern int nv10_graph_init(struct drm_device *);
extern void nv10_graph_takedown(struct drm_device *);
extern int nv10_graph_create_context(struct nouveau_channel *);
extern void nv10_graph_destroy_context(struct nouveau_channel *);
extern int nv10_graph_load_context(struct nouveau_channel *);
extern int nv10_graph_save_context(struct nouveau_channel *);
/* nv20_graph.c */
extern int nv20_graph_create_context(struct nouveau_channel *);
extern void nv20_graph_destroy_context(struct nouveau_channel *);
extern int nv20_graph_load_context(struct nouveau_channel *);
extern int nv20_graph_save_context(struct nouveau_channel *);
extern int nv20_graph_init(struct drm_device *);
extern void nv20_graph_takedown(struct drm_device *);
extern int nv30_graph_init(struct drm_device *);
/* nv40_graph.c */
extern int nv40_graph_init(struct drm_device *);
extern void nv40_graph_takedown(struct drm_device *);
extern int nv40_graph_create_context(struct nouveau_channel *);
extern void nv40_graph_destroy_context(struct nouveau_channel *);
extern int nv40_graph_load_context(struct nouveau_channel *);
extern int nv40_graph_save_context(struct nouveau_channel *);
/* nv50_graph.c */
extern int nv50_graph_init(struct drm_device *);
extern void nv50_graph_takedown(struct drm_device *);
extern int nv50_graph_create_context(struct nouveau_channel *);
extern void nv50_graph_destroy_context(struct nouveau_channel *);
extern int nv50_graph_load_context(struct nouveau_channel *);
extern int nv50_graph_save_context(struct nouveau_channel *);
/* nv04_instmem.c */
extern int nv04_instmem_init(struct drm_device *);
extern void nv04_instmem_takedown(struct drm_device *);
extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
uint32_t *size);
extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
/* nv50_instmem.c */
extern int nv50_instmem_init(struct drm_device *);
extern void nv50_instmem_takedown(struct drm_device *);
extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
uint32_t *size);
extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
/* nv04_mc.c */
extern int nv04_mc_init(struct drm_device *);
extern void nv04_mc_takedown(struct drm_device *);
/* nv40_mc.c */
extern int nv40_mc_init(struct drm_device *);
extern void nv40_mc_takedown(struct drm_device *);
/* nv50_mc.c */
extern int nv50_mc_init(struct drm_device *);
extern void nv50_mc_takedown(struct drm_device *);
/* nv04_timer.c */
extern int nv04_timer_init(struct drm_device *);
extern uint64_t nv04_timer_read(struct drm_device *);
extern void nv04_timer_takedown(struct drm_device *);
extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
unsigned long arg);
/* nouveau_buffer.c */
extern struct drm_bo_driver nouveau_bo_driver;
/* nouveau_fence.c */
extern struct drm_fence_driver nouveau_fence_driver;
extern void nouveau_fence_handler(struct drm_device *dev, int channel);
#if defined(__powerpc__)
#define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
#define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
#else
#define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
#define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
#endif
/* PRAMIN access */
#if defined(__powerpc__)
#define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
#define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
#else
#define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
#define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
#endif
#define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
#define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
#endif /* __NOUVEAU_DRV_H__ */
class="hl num">0x94C0, RV610_94C0, RV610)
CHIPSET(0x94C1, RV610_94C1, RV610)
CHIPSET(0x94C3, RV610_94C3, RV610)
CHIPSET(0x94C4, RV610_94C4, RV610)
CHIPSET(0x94C5, RV610_94C5, RV610)
CHIPSET(0x94C6, RV610_94C6, RV610)
CHIPSET(0x94C7, RV610_94C7, RV610)
CHIPSET(0x94C8, RV610_94C8, RV610)
CHIPSET(0x94C9, RV610_94C9, RV610)
CHIPSET(0x94CB, RV610_94CB, RV610)
CHIPSET(0x94CC, RV610_94CC, RV610)
CHIPSET(0x94CD, RV610_94CD, RV610)
CHIPSET(0x9580, RV630_9580, RV630)
CHIPSET(0x9581, RV630_9581, RV630)
CHIPSET(0x9583, RV630_9583, RV630)
CHIPSET(0x9586, RV630_9586, RV630)
CHIPSET(0x9587, RV630_9587, RV630)
CHIPSET(0x9588, RV630_9588, RV630)
CHIPSET(0x9589, RV630_9589, RV630)
CHIPSET(0x958A, RV630_958A, RV630)
CHIPSET(0x958B, RV630_958B, RV630)
CHIPSET(0x958C, RV630_958C, RV630)
CHIPSET(0x958D, RV630_958D, RV630)
CHIPSET(0x958E, RV630_958E, RV630)
CHIPSET(0x958F, RV630_958F, RV630)
CHIPSET(0x9500, RV670_9500, RV670)
CHIPSET(0x9501, RV670_9501, RV670)
CHIPSET(0x9504, RV670_9504, RV670)
CHIPSET(0x9505, RV670_9505, RV670)
CHIPSET(0x9506, RV670_9506, RV670)
CHIPSET(0x9507, RV670_9507, RV670)
CHIPSET(0x9508, RV670_9508, RV670)
CHIPSET(0x9509, RV670_9509, RV670)
CHIPSET(0x950F, RV670_950F, RV670)
CHIPSET(0x9511, RV670_9511, RV670)
CHIPSET(0x9515, RV670_9515, RV670)
CHIPSET(0x9517, RV670_9517, RV670)
CHIPSET(0x9519, RV670_9519, RV670)
CHIPSET(0x95C0, RV620_95C0, RV620)
CHIPSET(0x95C2, RV620_95C2, RV620)
CHIPSET(0x95C4, RV620_95C4, RV620)
CHIPSET(0x95C5, RV620_95C5, RV620)
CHIPSET(0x95C6, RV620_95C6, RV620)
CHIPSET(0x95C7, RV620_95C7, RV620)
CHIPSET(0x95C9, RV620_95C9, RV620)
CHIPSET(0x95CC, RV620_95CC, RV620)
CHIPSET(0x95CD, RV620_95CD, RV620)
CHIPSET(0x95CE, RV620_95CE, RV620)
CHIPSET(0x95CF, RV620_95CF, RV620)
CHIPSET(0x9590, RV635_9590, RV635)
CHIPSET(0x9591, RV635_9591, RV635)
CHIPSET(0x9593, RV635_9593, RV635)
CHIPSET(0x9595, RV635_9595, RV635)
CHIPSET(0x9596, RV635_9596, RV635)
CHIPSET(0x9597, RV635_9597, RV635)
CHIPSET(0x9598, RV635_9598, RV635)
CHIPSET(0x9599, RV635_9599, RV635)
CHIPSET(0x959B, RV635_959B, RV635)
CHIPSET(0x9610, RS780_9610, RS780)
CHIPSET(0x9611, RS780_9611, RS780)
CHIPSET(0x9612, RS780_9612, RS780)
CHIPSET(0x9613, RS780_9613, RS780)
CHIPSET(0x9614, RS780_9614, RS780)
CHIPSET(0x9615, RS780_9615, RS780)
CHIPSET(0x9616, RS780_9616, RS780)
CHIPSET(0x9710, RS880_9710, RS880)
CHIPSET(0x9711, RS880_9711, RS880)
CHIPSET(0x9712, RS880_9712, RS880)
CHIPSET(0x9713, RS880_9713, RS880)
CHIPSET(0x9714, RS880_9714, RS880)
CHIPSET(0x9715, RS880_9715, RS880)
CHIPSET(0x9440, RV770_9440, RV770)
CHIPSET(0x9441, RV770_9441, RV770)
CHIPSET(0x9442, RV770_9442, RV770)
CHIPSET(0x9443, RV770_9443, RV770)
CHIPSET(0x9444, RV770_9444, RV770)
CHIPSET(0x9446, RV770_9446, RV770)
CHIPSET(0x944A, RV770_944A, RV770)
CHIPSET(0x944B, RV770_944B, RV770)
CHIPSET(0x944C, RV770_944C, RV770)
CHIPSET(0x944E, RV770_944E, RV770)
CHIPSET(0x9450, RV770_9450, RV770)
CHIPSET(0x9452, RV770_9452, RV770)
CHIPSET(0x9456, RV770_9456, RV770)
CHIPSET(0x945A, RV770_945A, RV770)
CHIPSET(0x945B, RV770_945B, RV770)
CHIPSET(0x945E, RV770_945E, RV770)
CHIPSET(0x9460, RV790_9460, RV770)
CHIPSET(0x9462, RV790_9462, RV770)
CHIPSET(0x946A, RV770_946A, RV770)
CHIPSET(0x946B, RV770_946B, RV770)
CHIPSET(0x947A, RV770_947A, RV770)
CHIPSET(0x947B, RV770_947B, RV770)
CHIPSET(0x9480, RV730_9480, RV730)
CHIPSET(0x9487, RV730_9487, RV730)
CHIPSET(0x9488, RV730_9488, RV730)
CHIPSET(0x9489, RV730_9489, RV730)
CHIPSET(0x948A, RV730_948A, RV730)
CHIPSET(0x948F, RV730_948F, RV730)
CHIPSET(0x9490, RV730_9490, RV730)
CHIPSET(0x9491, RV730_9491, RV730)
CHIPSET(0x9495, RV730_9495, RV730)
CHIPSET(0x9498, RV730_9498, RV730)
CHIPSET(0x949C, RV730_949C, RV730)
CHIPSET(0x949E, RV730_949E, RV730)
CHIPSET(0x949F, RV730_949F, RV730)
CHIPSET(0x9540, RV710_9540, RV710)
CHIPSET(0x9541, RV710_9541, RV710)
CHIPSET(0x9542, RV710_9542, RV710)
CHIPSET(0x954E, RV710_954E, RV710)
CHIPSET(0x954F, RV710_954F, RV710)
CHIPSET(0x9552, RV710_9552, RV710)
CHIPSET(0x9553, RV710_9553, RV710)
CHIPSET(0x9555, RV710_9555, RV710)
CHIPSET(0x9557, RV710_9557, RV710)
CHIPSET(0x955F, RV710_955F, RV710)
CHIPSET(0x94A0, RV740_94A0, RV740)
CHIPSET(0x94A1, RV740_94A1, RV740)
CHIPSET(0x94A3, RV740_94A3, RV740)
CHIPSET(0x94B1, RV740_94B1, RV740)
CHIPSET(0x94B3, RV740_94B3, RV740)
CHIPSET(0x94B4, RV740_94B4, RV740)
CHIPSET(0x94B5, RV740_94B5, RV740)
CHIPSET(0x94B9, RV740_94B9, RV740)
CHIPSET(0x68E0, CEDAR_68E0, CEDAR)
CHIPSET(0x68E1, CEDAR_68E1, CEDAR)
CHIPSET(0x68E4, CEDAR_68E4, CEDAR)
CHIPSET(0x68E5, CEDAR_68E5, CEDAR)
CHIPSET(0x68E8, CEDAR_68E8, CEDAR)
CHIPSET(0x68E9, CEDAR_68E9, CEDAR)
CHIPSET(0x68F1, CEDAR_68F1, CEDAR)
CHIPSET(0x68F2, CEDAR_68F2, CEDAR)
CHIPSET(0x68F8, CEDAR_68F8, CEDAR)
CHIPSET(0x68F9, CEDAR_68F9, CEDAR)
CHIPSET(0x68FA, CEDAR_68FA, CEDAR)
CHIPSET(0x68FE, CEDAR_68FE, CEDAR)
CHIPSET(0x68C0, REDWOOD_68C0, REDWOOD)
CHIPSET(0x68C1, REDWOOD_68C1, REDWOOD)
CHIPSET(0x68C7, REDWOOD_68C7, REDWOOD)
CHIPSET(0x68C8, REDWOOD_68C8, REDWOOD)
CHIPSET(0x68C9, REDWOOD_68C9, REDWOOD)
CHIPSET(0x68D8, REDWOOD_68D8, REDWOOD)
CHIPSET(0x68D9, REDWOOD_68D9, REDWOOD)
CHIPSET(0x68DA, REDWOOD_68DA, REDWOOD)
CHIPSET(0x68DE, REDWOOD_68DE, REDWOOD)
CHIPSET(0x68A0, JUNIPER_68A0, JUNIPER)
CHIPSET(0x68A1, JUNIPER_68A1, JUNIPER)
CHIPSET(0x68A8, JUNIPER_68A8, JUNIPER)
CHIPSET(0x68A9, JUNIPER_68A9, JUNIPER)
CHIPSET(0x68B0, JUNIPER_68B0, JUNIPER)
CHIPSET(0x68B8, JUNIPER_68B8, JUNIPER)
CHIPSET(0x68B9, JUNIPER_68B9, JUNIPER)
CHIPSET(0x68BA, JUNIPER_68BA, JUNIPER)
CHIPSET(0x68BE, JUNIPER_68BE, JUNIPER)
CHIPSET(0x68BF, JUNIPER_68BF, JUNIPER)
CHIPSET(0x6880, CYPRESS_6880, CYPRESS)
CHIPSET(0x6888, CYPRESS_6888, CYPRESS)
CHIPSET(0x6889, CYPRESS_6889, CYPRESS)
CHIPSET(0x688A, CYPRESS_688A, CYPRESS)
CHIPSET(0x688C, CYPRESS_688C, CYPRESS)
CHIPSET(0x688D, CYPRESS_688D, CYPRESS)
CHIPSET(0x6898, CYPRESS_6898, CYPRESS)
CHIPSET(0x6899, CYPRESS_6899, CYPRESS)
CHIPSET(0x689B, CYPRESS_689B, CYPRESS)
CHIPSET(0x689E, CYPRESS_689E, CYPRESS)
CHIPSET(0x689C, HEMLOCK_689C, HEMLOCK)
CHIPSET(0x689D, HEMLOCK_689D, HEMLOCK)
CHIPSET(0x9802, PALM_9802, PALM)
CHIPSET(0x9803, PALM_9803, PALM)
CHIPSET(0x9804, PALM_9804, PALM)
CHIPSET(0x9805, PALM_9805, PALM)
CHIPSET(0x9806, PALM_9806, PALM)
CHIPSET(0x9807, PALM_9807, PALM)
CHIPSET(0x9808, PALM_9808, PALM)
CHIPSET(0x9809, PALM_9809, PALM)
CHIPSET(0x980A, PALM_980A, PALM)
CHIPSET(0x9640, SUMO_9640, SUMO)
CHIPSET(0x9641, SUMO_9641, SUMO)
CHIPSET(0x9642, SUMO2_9642, SUMO2)
CHIPSET(0x9643, SUMO2_9643, SUMO2)
CHIPSET(0x9644, SUMO2_9644, SUMO2)
CHIPSET(0x9645, SUMO2_9645, SUMO2)
CHIPSET(0x9647, SUMO_9647, SUMO)
CHIPSET(0x9648, SUMO_9648, SUMO)
CHIPSET(0x9649, SUMO2_9649, SUMO2)
CHIPSET(0x964a, SUMO_964A, SUMO)
CHIPSET(0x964b, SUMO_964B, SUMO)
CHIPSET(0x964c, SUMO_964C, SUMO)
CHIPSET(0x964e, SUMO_964E, SUMO)
CHIPSET(0x964f, SUMO_964F, SUMO)
CHIPSET(0x6700, CAYMAN_6700, CAYMAN)
CHIPSET(0x6701, CAYMAN_6701, CAYMAN)
CHIPSET(0x6702, CAYMAN_6702, CAYMAN)
CHIPSET(0x6703, CAYMAN_6703, CAYMAN)
CHIPSET(0x6704, CAYMAN_6704, CAYMAN)
CHIPSET(0x6705, CAYMAN_6705, CAYMAN)
CHIPSET(0x6706, CAYMAN_6706, CAYMAN)
CHIPSET(0x6707, CAYMAN_6707, CAYMAN)
CHIPSET(0x6708, CAYMAN_6708, CAYMAN)
CHIPSET(0x6709, CAYMAN_6709, CAYMAN)
CHIPSET(0x6718, CAYMAN_6718, CAYMAN)
CHIPSET(0x6719, CAYMAN_6719, CAYMAN)
CHIPSET(0x671C, CAYMAN_671C, CAYMAN)
CHIPSET(0x671D, CAYMAN_671D, CAYMAN)
CHIPSET(0x671F, CAYMAN_671F, CAYMAN)
CHIPSET(0x6720, BARTS_6720, BARTS)
CHIPSET(0x6721, BARTS_6721, BARTS)
CHIPSET(0x6722, BARTS_6722, BARTS)
CHIPSET(0x6723, BARTS_6723, BARTS)
CHIPSET(0x6724, BARTS_6724, BARTS)
CHIPSET(0x6725, BARTS_6725, BARTS)
CHIPSET(0x6726, BARTS_6726, BARTS)
CHIPSET(0x6727, BARTS_6727, BARTS)
CHIPSET(0x6728, BARTS_6728, BARTS)
CHIPSET(0x6729, BARTS_6729, BARTS)
CHIPSET(0x6738, BARTS_6738, BARTS)
CHIPSET(0x6739, BARTS_6739, BARTS)
CHIPSET(0x673E, BARTS_673E, BARTS)
CHIPSET(0x6740, TURKS_6740, TURKS)
CHIPSET(0x6741, TURKS_6741, TURKS)
CHIPSET(0x6742, TURKS_6742, TURKS)
CHIPSET(0x6743, TURKS_6743, TURKS)
CHIPSET(0x6744, TURKS_6744, TURKS)
CHIPSET(0x6745, TURKS_6745, TURKS)
CHIPSET(0x6746, TURKS_6746, TURKS)
CHIPSET(0x6747, TURKS_6747, TURKS)
CHIPSET(0x6748, TURKS_6748, TURKS)
CHIPSET(0x6749, TURKS_6749, TURKS)
CHIPSET(0x674A, TURKS_674A, TURKS)
CHIPSET(0x6750, TURKS_6750, TURKS)
CHIPSET(0x6751, TURKS_6751, TURKS)
CHIPSET(0x6758, TURKS_6758, TURKS)
CHIPSET(0x6759, TURKS_6759, TURKS)
CHIPSET(0x675B, TURKS_675B, TURKS)
CHIPSET(0x675D, TURKS_675D, TURKS)
CHIPSET(0x675F, TURKS_675F, TURKS)
CHIPSET(0x6840, TURKS_6840, TURKS)
CHIPSET(0x6841, TURKS_6841, TURKS)
CHIPSET(0x6842, TURKS_6842, TURKS)
CHIPSET(0x6843, TURKS_6843, TURKS)
CHIPSET(0x6849, TURKS_6849, TURKS)
CHIPSET(0x6850, TURKS_6850, TURKS)
CHIPSET(0x6858, TURKS_6858, TURKS)
CHIPSET(0x6859, TURKS_6859, TURKS)
CHIPSET(0x6760, CAICOS_6760, CAICOS)
CHIPSET(0x6761, CAICOS_6761, CAICOS)
CHIPSET(0x6762, CAICOS_6762, CAICOS)
CHIPSET(0x6763, CAICOS_6763, CAICOS)
CHIPSET(0x6764, CAICOS_6764, CAICOS)
CHIPSET(0x6765, CAICOS_6765, CAICOS)
CHIPSET(0x6766, CAICOS_6766, CAICOS)
CHIPSET(0x6767, CAICOS_6767, CAICOS)
CHIPSET(0x6768, CAICOS_6768, CAICOS)
CHIPSET(0x6770, CAICOS_6770, CAICOS)
CHIPSET(0x6771, CAICOS_6771, CAICOS)
CHIPSET(0x6772, CAICOS_6772, CAICOS)
CHIPSET(0x6778, CAICOS_6778, CAICOS)
CHIPSET(0x6779, CAICOS_6779, CAICOS)
CHIPSET(0x677B, CAICOS_677B, CAICOS)
CHIPSET(0x9900, ARUBA_9900, ARUBA)
CHIPSET(0x9901, ARUBA_9901, ARUBA)
CHIPSET(0x9903, ARUBA_9903, ARUBA)
CHIPSET(0x9904, ARUBA_9904, ARUBA)
CHIPSET(0x9905, ARUBA_9905, ARUBA)
CHIPSET(0x9906, ARUBA_9906, ARUBA)
CHIPSET(0x9907, ARUBA_9907, ARUBA)
CHIPSET(0x9908, ARUBA_9908, ARUBA)
CHIPSET(0x9909, ARUBA_9909, ARUBA)
CHIPSET(0x990A, ARUBA_990A, ARUBA)
CHIPSET(0x990B, ARUBA_990B, ARUBA)
CHIPSET(0x990C, ARUBA_990C, ARUBA)
CHIPSET(0x990D, ARUBA_990D, ARUBA)