/* mga_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: Rickard E. (Rik) Faith * Jeff Hartmann * */ #ifndef _MGA_DRV_H_ #define _MGA_DRV_H_ #define MGA_BUF_IN_USE 0 #define MGA_BUF_SWAP_PENDING 1 #define MGA_BUF_FORCE_FIRE 2 #define MGA_BUF_NEEDS_OVERFLOW 3 typedef struct { long buffer_status; /* long req'd for set_bit() --RR */ int num_dwords; int max_dwords; u32 *current_dma_ptr; u32 *head; u32 phys_head; unsigned int prim_age; int sec_used; int idx; } drm_mga_prim_buf_t; typedef struct _drm_mga_freelist { __volatile__ unsigned int age; drm_buf_t *buf; struct _drm_mga_freelist *next; struct _drm_mga_freelist *prev; } drm_mga_freelist_t; #define MGA_IN_DISPATCH 0 #define MGA_IN_FLUSH 1 #define MGA_IN_WAIT 2 #define MGA_IN_GETBUF 3 typedef struct _drm_mga_private { long dispatch_status; /* long req'd for set_bit() --RR */ unsigned int next_prim_age; __volatile__ unsigned int last_prim_age; int reserved_map_idx; int buffer_map_idx; drm_mga_sarea_t *sarea_priv; int primary_size; int warp_ucode_size; int chipset; unsigned int frontOffset; unsigned int backOffset; unsigned int depthOffset; unsigned int textureOffset; unsigned int textureSize; int cpp; unsigned int stride; int sgram; int use_agp; drm_mga_warp_index_t WarpIndex[MGA_MAX_G400_PIPES]; unsigned int WarpPipe; unsigned int vertexsize; atomic_t pending_bufs; void *status_page; unsigned long real_status_page; u8 *ioremap; drm_mga_prim_buf_t **prim_bufs; drm_mga_prim_buf_t *next_prim; drm_mga_prim_buf_t *last_prim; drm_mga_prim_buf_t *current_prim; int current_prim_idx; drm_mga_freelist_t *head; drm_mga_freelist_t *tail; wait_queue_head_t flush_queue; /* Processes waiting until flush */ wait_queue_head_t wait_queue; /* Processes waiting until interrupt */ wait_queue_head_t buf_queue; /* Processes waiting for a free buf */ /* Some validated register values: */ u32 mAccess; } drm_mga_private_t; /* mga_drv.c */ extern int mga_version(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_open(struct inode *inode, struct file *filp); extern int mga_release(struct inode *inode, struct file *filp); extern int mga_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_unlock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); /* mga_dma.c */ extern int mga_dma_schedule(drm_device_t *dev, int locked); extern int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_irq_install(drm_device_t *dev, int irq); extern int mga_irq_uninstall(drm_device_t *dev); extern int mga_control(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_lock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); /* mga_dma_init does init and release */ extern int mga_dma_init(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_dma_cleanup(drm_device_t *dev); extern int mga_flush_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern unsigned int mga_create_sync_tag(drm_device_t *dev); extern drm_buf_t *mga_freelist_get(drm_device_t *dev); extern int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf); extern int mga_advance_primary(drm_device_t *dev); extern void mga_reclaim_buffers(drm_device_t *dev, pid_t pid); /* mga_bufs.c */ extern int mga_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_infobufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_markbufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_freebufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_addmap(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); /* mga_state.c */ extern int mga_clear_bufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_swap_bufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_iload(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_vertex(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_indices(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_blit(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); /* mga_context.c */ extern int mga_resctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_addctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_modctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_getctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_newctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_context_switch(drm_device_t *dev, int old, int new); extern int mga_context_switch_complete(drm_device_t *dev, int new); #define mga_flush_write_combine() mb() typedef enum { TT_GENERAL, TT_BLIT, TT_VECTOR, TT_VERTEX } transferType_t; typedef struct { drm_mga_freelist_t *my_freelist; int discard; int dispatched; } drm_mga_buf_priv_t; #define DWGREG0 0x1c00 #define DWGREG0_END 0x1dff #define DWGREG1 0x2c00 #define DWGREG1_END 0x2dff #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) #define ADRINDEX0(r) (u8)((r - DWGREG0) >> 2) #define ADRINDEX1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) #define ADRINDEX(r) (ISREG0(r) ? ADRINDEX0(r) : ADRINDEX1(r)) #define MGA_VERBOSE 0 #define MGA_NUM_PRIM_BUFS 8 #define PRIMLOCALS u8 tempIndex[4]; u32 *dma_ptr; u32 phys_head; \ int outcount, num_dwords #define PRIM_OVERFLOW(dev, dev_priv, length) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ if( test_bit(MGA_BUF_NEEDS_OVERFLOW, &tmp_buf->buffer_status)) { \ mga_advance_primary(dev); \ mga_dma_schedule(dev, 1); \ tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ } else if( tmp_buf->max_dwords - tmp_buf->num_dwords < length || \ tmp_buf->sec_used > MGA_DMA_BUF_NR/2) { \ set_bit(MGA_BUF_FORCE_FIRE, &tmp_buf->buffer_status); \ mga_advance_primary(dev); \ mga_dma_schedule(dev, 1); \ tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ } \ if(MGA_VERBOSE) \ DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ dma_ptr = tmp_buf->current_dma_ptr; \ num_dwords = tmp_buf->num_dwords; \ phys_head = tmp_buf->phys_head; \ outcount = 0; \ } while(0) #define PRIMGETPTR(dev_priv) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ if(MGA_VERBOSE) \ DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ dma_ptr = tmp_buf->current_dma_ptr; \ num_dwords = tmp_buf->num_dwords; \ phys_head = tmp_buf->phys_head; \ outcount = 0; \ } while(0) #define PRIMPTR(prim_buf) do { \ if(MGA_VERBOSE) \ DRM_DEBUG("PRIMPTR in %s\n", __FUNCTION__); \ dma_ptr = prim_buf->current_dma_ptr; \ num_dwords = prim_buf->num_dwords; \ phys_head = prim_buf->phys_head; \ outcount = 0; \ } while(0) #define PRIMFINISH(prim_buf) do { \ if (MGA_VERBOSE) { \ DRM_DEBUG( "PRIMFINISH in %s\n", __FUNCTION__); \ if (outcount & 3) \ DRM_DEBUG(" --- truncation\n"); \ } \ prim_buf->num_dwords = num_dwords; \ prim_buf->current_dma_ptr = dma_ptr; \ } while(0) #define PRIMADVANCE(dev_priv) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ if (MGA_VERBOSE) { \ DRM_DEBUG("PRIMADVANCE in %s\n", __FUNCTION__); \ if (outcount & 3) \ DRM_DEBUG(" --- truncation\n"); \ } \ tmp_buf->num_dwords = num_dwords; \ tmp_buf->current_dma_ptr = dma_ptr; \ } while (0) #define PRIMUPDATE(dev_priv) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ tmp_buf->sec_used++; \ } while (0) #define AGEBUF(dev_priv, buf_priv) do { \ drm_mga_prim_buf_t *tmp_buf = \ dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ buf_priv->my_freelist->age = tmp_buf->prim_age; \ } while (0) #define PRIMOUTREG(reg, val) do { \ tempIndex[outcount]=ADRINDEX(reg); \ dma_ptr[1+outcount] = val; \ if (MGA_VERBOSE) \ DRM_DEBUG(" PRIMOUT %d: 0x%x -- 0x%x\n", \ num_dwords + 1 + outcount, ADRINDEX(reg), val); \ if( ++outcount == 4) { \ outcount = 0; \ dma_ptr[0] = *(unsigned long *)tempIndex; \ dma_ptr+=5; \ num_dwords += 5; \ } \ }while (0) /* A reduced set of the mga registers. */ #define MGAREG_MGA_EXEC 0x0100 #define MGAREG_ALPHACTRL 0x2c7c #define MGAREG_AR0 0x1c60 #define MGAREG_AR1 0x1c64 #define MGAREG_AR2 0x1c68 #define MGAREG_AR3 0x1c6c #define MGAREG_AR4 0x1c70 #define MGAREG_AR5 0x1c74 #define MGAREG_AR6 0x1c78 #define MGAREG_CXBNDRY 0x1c80 #define MGAREG_CXLEFT 0x1ca0 #define MGAREG_CXRIGHT 0x1ca4 #define MGAREG_DMAPAD 0x1c54 #define MGAREG_DSTORG 0x2cb8 #define MGAREG_DWGCTL 0x1c00 #define MGAREG_DWGSYNC 0x2c4c #define MGAREG_FCOL 0x1c24 #define MGAREG_FIFOSTATUS 0x1e10 #define MGAREG_FOGCOL 0x1cf4 #define MGAREG_FXBNDRY 0x1c84 #define MGAREG_FXLEFT 0x1ca8 #define MGAREG_FXRIGHT 0x1cac #define MGAREG_ICLEAR 0x1e18 #define MGAREG_IEN 0x1e1c #define MGAREG_LEN 0x1c5c #define MGAREG_MACCESS 0x1c04 #define MGAREG_PITCH 0x1c8c #define MGAREG_PLNWT 0x1c1c #define MGAREG_PRIMADDRESS 0x1e58 #define MGAREG_PRIMEND 0x1e5c #define MGAREG_PRIMPTR 0x1e50 #define MGAREG_SECADDRESS 0x2c40 #define MGAREG_SECEND 0x2c44 #define MGAREG_SETUPADDRESS 0x2cd0 #define MGAREG_SETUPEND 0x2cd4 #define MGAREG_SGN 0x1c58 #define MGAREG_SOFTRAP 0x2c48 #define MGAREG_SRCORG 0x2cb4 #define MGAREG_STATUS 0x1e14 #define MGAREG_STENCIL 0x2cc8 #define MGAREG_STENCILCTL 0x2ccc #define MGAREG_TDUALSTAGE0 0x2cf8 #define MGAREG_TDUALSTAGE1 0x2cfc #define MGAREG_TEXBORDERCOL 0x2c5c #define MGAREG_TEXCTL 0x2c30 #define MGAREG_TEXCTL2 0x2c3c #define MGAREG_TEXFILTER 0x2c58 #define MGAREG_TEXHEIGHT 0x2c2c #define MGAREG_TEXORG 0x2c24 #define MGAREG_TEXORG1 0x2ca4 #define MGAREG_TEXORG2 0x2ca8 #define MGAREG_TEXORG3 0x2cac #define MGAREG_TEXORG4 0x2cb0 #define MGAREG_TEXTRANS 0x2c34 #define MGAREG_TEXTRANSHIGH 0x2c38 #define MGAREG_TEXWIDTH 0x2c28 #define MGAREG_WACCEPTSEQ 0x1dd4 #define MGAREG_WCODEADDR 0x1e6c #define MGAREG_WFLAG 0x1dc4 #define MGAREG_WFLAG1 0x1de0 #define MGAREG_WFLAGNB 0x1e64 #define MGAREG_WFLAGNB1 0x1e08 #define MGAREG_WGETMSB 0x1dc8 #define MGAREG_WIADDR 0x1dc0 #define MGAREG_WIADDR2 0x1dd8 #define MGAREG_WMISC 0x1e70 #define MGAREG_WVRTXSZ 0x1dcc #define MGAREG_YBOT 0x1c9c #define MGAREG_YDST 0x1c90 #define MGAREG_YDSTLEN 0x1c88 #define MGAREG_YDSTORG 0x1c94 #define MGAREG_YTOP 0x1c98 #define MGAREG_ZORG 0x1c0c /* Warp registers */ #define MGAREG_WR0 0x2d00 #define MGAREG_WR1 0x2d04 #define MGAREG_WR2 0x2d08 #define MGAREG_WR3 0x2d0c #define MGAREG_WR4 0x2d10 #define MGAREG_WR5 0x2d14 #define MGAREG_WR6 0x2d18 #define MGAREG_WR7 0x2d1c #define MGAREG_WR8 0x2d20 #define MGAREG_WR9 0x2d24 #define MGAREG_WR10 0x2d28 #define MGAREG_WR11 0x2d2c #define MGAREG_WR12 0x2d30 #define MGAREG_WR13 0x2d34 #define MGAREG_WR14 0x2d38 #define MGAREG_WR15 0x2d3c #define MGAREG_WR16 0x2d40 #define MGAREG_WR17 0x2d44 #define MGAREG_WR18 0x2d48 #define MGAREG_WR19 0x2d4c #define MGAREG_WR20 0x2d50 #define MGAREG_WR21 0x2d54 #define MGAREG_WR22 0x2d58 #define MGAREG_WR23 0x2d5c #define MGAREG_WR24 0x2d60 #define MGAREG_WR25 0x2d64 #define MGAREG_WR26 0x2d68 #define MGAREG_WR27 0x2d6c #define MGAREG_WR28 0x2d70 #define MGAREG_WR29 0x2d74 #define MGAREG_WR30 0x2d78 #define MGAREG_WR31 0x2d7c #define MGAREG_WR32 0x2d80 #define MGAREG_WR33 0x2d84 #define MGAREG_WR34 0x2d88 #define MGAREG_WR35 0x2d8c #define MGAREG_WR36 0x2d90 #define MGAREG_WR37 0x2d94 #define MGAREG_WR38 0x2d98 #define MGAREG_WR39 0x2d9c #define MGAREG_WR40 0x2da0 #define MGAREG_WR41 0x2da4 #define MGAREG_WR42 0x2da8 #define MGAREG_WR43 0x2dac #define MGAREG_WR44 0x2db0 #define MGAREG_WR45 0x2db4 #define MGAREG_WR46 0x2db8 #define MGAREG_WR47 0x2dbc #define MGAREG_WR48 0x2dc0 #define MGAREG_WR49 0x2dc4 #define MGAREG_WR50 0x2dc8 #define MGAREG_WR51 0x2dcc #define MGAREG_WR52 0x2dd0 #define MGAREG_WR53 0x2dd4 #define MGAREG_WR54 0x2dd8 #define MGAREG_WR55 0x2ddc #define MGAREG_WR56 0x2de0 #define MGAREG_WR57 0x2de4 #define MGAREG_WR58 0x2de8 #define MGAREG_WR59 0x2dec #define MGAREG_WR60 0x2df0 #define MGAREG_WR61 0x2df4 #define MGAREG_WR62 0x2df8 #define MGAREG_WR63 0x2dfc #define PDEA_pagpxfer_enable 0x2 #define WIA_wmode_suspend 0x0 #define WIA_wmode_start 0x3 #define WIA_wagp_agp 0x4 #define DC_opcod_line_open 0x0 #define DC_opcod_autoline_open 0x1 #define DC_opcod_line_close 0x2 #define DC_opcod_autoline_close 0x3 #define DC_opcod_trap 0x4 #define DC_opcod_texture_trap 0x6 #define DC_opcod_bitblt 0x8 #define DC_opcod_iload 0x9 #define DC_atype_rpl 0x0 #define DC_atype_rstr 0x10 #define DC_atype_zi 0x30 #define DC_atype_blk 0x40 #define DC_atype_i 0x70 #define DC_linear_xy 0x0 #define DC_linear_linear 0x80 #define DC_zmode_nozcmp 0x0 #define DC_zmode_ze 0x200 #define DC_zmode_zne 0x300 #define DC_zmode_zlt 0x400 #define DC_zmode_zlte 0x500 #define DC_zmode_zgt 0x600 #define DC_zmode_zgte 0x700 #define DC_solid_disable 0x0 #define DC_solid_enable 0x800 #define DC_arzero_disable 0x0 #define DC_arzero_enable 0x1000 #define DC_sgnzero_disable 0x0 #define DC_sgnzero_enable 0x2000 #define DC_shftzero_disable 0x0 #define DC_shftzero_enable 0x4000 #define DC_bop_SHIFT 16 #define DC_trans_SHIFT 20 #define DC_bltmod_bmonolef 0x0 #define DC_bltmod_bmonowf 0x8000000 #define DC_bltmod_bplan 0x2000000 #define DC_bltmod_bfcol 0x4000000 #define DC_bltmod_bu32bgr 0x6000000 #define DC_bltmod_bu32rgb 0xe000000 #define DC_bltmod_bu24bgr 0x16000000 #define DC_bltmod_bu24rgb 0x1e000000 #define DC_pattern_disable 0x0 #define DC_pattern_enable 0x20000000 #define DC_transc_disable 0x0 #define DC_transc_enable 0x40000000 #define DC_clipdis_disable 0x0 #define DC_clipdis_enable 0x80000000 #define SO_srcacc_pci 0x0 #define SO_srcacc_agp 0x2 #define SO_srcmap_fb 0x0 #define SO_srcmap_sys 0x1 #define SETADD_mode_vertlist 0x0 #define MGA_CLEAR_CMD (DC_opcod_trap | DC_arzero_enable | \ DC_sgnzero_enable | DC_shftzero_enable | \ (0xC << DC_bop_SHIFT) | DC_clipdis_enable | \ DC_solid_enable | DC_transc_enable) #define MGA_COPY_CMD (DC_opcod_bitblt | DC_atype_rpl | DC_linear_xy | \ DC_solid_disable | DC_arzero_disable | \ DC_sgnzero_enable | DC_shftzero_enable | \ (0xC << DC_bop_SHIFT) | DC_bltmod_bfcol | \ DC_pattern_disable | DC_transc_disable | \ DC_clipdis_enable) \ #define MGA_FLUSH_CMD (DC_opcod_texture_trap | (0xF << DC_trans_SHIFT) |\ DC_arzero_enable | DC_sgnzero_enable | \ DC_atype_i) #endif 00'>500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 
#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"

/*
 * NV20
 * -----
 * There are 3 families :
 * NV20 is 0x10de:0x020*
 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
 * NV2A is 0x10de:0x02A0
 *
 * NV30
 * -----
 * There are 3 families :
 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
 * NV34 is 0x10de:0x032*
 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
 *
 * Not seen in the wild, no dumps (probably NV35) :
 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
 *
 */

#define NV20_GRCTX_SIZE (3580*4)
#define NV25_GRCTX_SIZE (3529*4)
#define NV2A_GRCTX_SIZE (3500*4)

#define NV30_31_GRCTX_SIZE (24392)
#define NV34_GRCTX_SIZE    (18140)
#define NV35_36_GRCTX_SIZE (22396)

static void nv20_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;
/*
write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements:
+0x00740adc: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bfc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

+0x00740c1c: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740c3c: 00000000 00000000 00000000 44400000 00000000 00000000 00000000 00000000
+0x00740c5c: 00000000 00000000 00000000 00000000 00000000 00000000 00030303 00030303
+0x00740c7c: 00030303 00030303 00000000 00000000 00000000 00000000 00080000 00080000
+0x00740c9c: 00080000 00080000 00000000 00000000 01012000 01012000 01012000 01012000
+0x00740cbc: 000105b8 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008
+0x00740cdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740cfc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740d1c: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740d3c: 00000000 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000

+0x00740d5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d9c: 00000001 00000000 00004000 00000000 00000000 00000001 00000000 00040000
+0x00740dbc: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740ddc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
*/
	INSTANCE_WR(ctx, (0x33c/4)+0, 0xffff0000);
	INSTANCE_WR(ctx, (0x33c/4)+25, 0x0fff0000);
	INSTANCE_WR(ctx, (0x33c/4)+26, 0x0fff0000);
	INSTANCE_WR(ctx, (0x33c/4)+80, 0x00000101);
	INSTANCE_WR(ctx, (0x33c/4)+85, 0x00000111);
	INSTANCE_WR(ctx, (0x33c/4)+91, 0x44400000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+102+i, 0x00030303);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+110+i, 0x00080000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+116+i, 0x01012000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+120+i, 0x000105b8);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008);
	for (i = 0; i < 16; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000);
	INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7fffff);
	INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001);
	INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000);
	INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001);
	INSTANCE_WR(ctx, (0x33c/4)+183, 0x00040000);
	INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000);

/*
...
+0x0074239c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x007423bc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x007423dc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x007423fc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
...
+0x00742bdc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742bfc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742c1c: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742c3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
*/
	for (i = 0; i < 0x880; i += 0x10) {
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+0, 0x10700ff9);
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+1, 0x0436086c);
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+2, 0x000c001b);
	}

/*
write32 #1 block at +0x00742fbc NV_PRAMIN+0x42fbc of 4 (0x4) elements:
+0x00742fbc: 3f800000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x281c/4), 0x3f800000);

/*
write32 #1 block at +0x00742ffc NV_PRAMIN+0x42ffc of 12 (0xc) elements:
+0x00742ffc: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
+0x0074301c: 00000000 bf800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x285c/4)+0, 0x40000000);
	INSTANCE_WR(ctx, (0x285c/4)+1, 0x3f800000);
	INSTANCE_WR(ctx, (0x285c/4)+2, 0x3f000000);
	INSTANCE_WR(ctx, (0x285c/4)+4, 0x40000000);
	INSTANCE_WR(ctx, (0x285c/4)+5, 0x3f800000);
	INSTANCE_WR(ctx, (0x285c/4)+7, 0xbf800000);
	INSTANCE_WR(ctx, (0x285c/4)+9, 0xbf800000);

/*
write32 #1 block at +0x00742fcc NV_PRAMIN+0x42fcc of 4 (0x4) elements:
+0x00742fcc: 00000000 3f800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x282c/4)+1, 0x3f800000);

/*
write32 #1 block at +0x0074302c NV_PRAMIN+0x4302c of 4 (0x4) elements:
+0x0074302c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743c9c NV_PRAMIN+0x43c9c of 4 (0x4) elements:
+0x00743c9c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743c3c NV_PRAMIN+0x43c3c of 8 (0x8) elements:
+0x00743c3c: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x349c/4)+2, 0x000fe000);

/*
write32 #1 block at +0x00743c6c NV_PRAMIN+0x43c6c of 4 (0x4) elements:
+0x00743c6c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743ccc NV_PRAMIN+0x43ccc of 4 (0x4) elements:
+0x00743ccc: 00000000 000003f8 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x352c/4)+1, 0x000003f8);

/* write32 #1 NV_PRAMIN+0x43ce0 <- 0x002fe000 */
	INSTANCE_WR(ctx, 0x3540/4, 0x002fe000);

/*
write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements:
+0x00743cfc: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
*/
	for (i = 0; i < 8; ++i)
		INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c);
}

static void nv2a_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	INSTANCE_WR(ctx, 0x33c/4, 0xffff0000);
	for(i = 0x3a0; i< 0x3a8; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0fff0000);
	INSTANCE_WR(ctx, 0x47c/4, 0x00000101);
	INSTANCE_WR(ctx, 0x490/4, 0x00000111);
	INSTANCE_WR(ctx, 0x4a8/4, 0x44400000);
	for(i = 0x4d4; i< 0x4e4; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00030303);
	for(i = 0x4f4; i< 0x504; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080000);
	for(i = 0x50c; i< 0x51c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x01012000);
	for(i = 0x51c; i< 0x52c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x000105b8);
	for(i = 0x52c; i< 0x53c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080008);
	for(i = 0x55c; i< 0x59c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x07ff0000);
	INSTANCE_WR(ctx, 0x5a4/4, 0x4b7fffff);
	INSTANCE_WR(ctx, 0x5fc/4, 0x00000001);
	INSTANCE_WR(ctx, 0x604/4, 0x00004000);
	INSTANCE_WR(ctx, 0x610/4, 0x00000001);
	INSTANCE_WR(ctx, 0x618/4, 0x00040000);
	INSTANCE_WR(ctx, 0x61c/4, 0x00010000);

	for (i=0x1a9c; i <= 0x22fc/4; i += 32) {
		INSTANCE_WR(ctx, i/4    , 0x10700ff9);
		INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
		INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
	}

	INSTANCE_WR(ctx, 0x269c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26b0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26dc/4, 0x40000000);
	INSTANCE_WR(ctx, 0x26e0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26e4/4, 0x3f000000);
	INSTANCE_WR(ctx, 0x26ec/4, 0x40000000);
	INSTANCE_WR(ctx, 0x26f0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26f8/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x2700/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x3024/4, 0x000fe000);
	INSTANCE_WR(ctx, 0x30a0/4, 0x000003f8);
	INSTANCE_WR(ctx, 0x33fc/4, 0x002fe000);
	for(i = 0x341c; i< 0x343c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x001c527c);
}

static void nv25_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;
/*
write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements:
+0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000
+0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000
+0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303
+0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000
+0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8

+0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000
+0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000
+0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000
+0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d1c: 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000);
	INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000);
	INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000);
	INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101);
	INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111);
	INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080);
	INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000);
	INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001);
	INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000);
	INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000);
	INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000);
	INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000);
	INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000);
	INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000);
	INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8);
	INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8);
	INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8);
	INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8);
	INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008);
	INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008);
	INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008);
	INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008);
	for (i=0; i<16; ++i)
		INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000);
	INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7fffff);

/*
write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements:
+0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0
+0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000
+0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000
+0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
+0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
...
+0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000
+0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080);
	INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000);
	INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040);
	INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080);
	INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0);
	INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001);
	INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000);
	INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001);
	INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000);
	INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000);
	for (i=0; i < 0x880/4; i+=4) {
		INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9);
		INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c);
		INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b);
	}

/*
write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements:
+0x00742e24: 3f800000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x2704/4), 0x3f800000);

/*
write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements:
+0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
+0x00742e84: 00000000 bf800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000);
	INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000);
	INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000);
	INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000);
	INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000);
	INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000);
	INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000);

/*
write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements:
+0x00742e34: 00000000 3f800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000);

/*
write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements:
+0x00742e94: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements:
+0x00743804: 00000000 00000000 00000000 00000000
write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements:
+0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000);

/*
write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements:
+0x007437d4: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements:
+0x00743824: 00000000 000003f8 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8);

/* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */
	INSTANCE_WR(ctx, 0x3468/4, 0x002fe000);

/*
write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements:
+0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
*/
	for (i=0; i<8; ++i)
		INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c);
}

static void nv30_31_graph_context_init(struct drm_device *dev,
                                       struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	INSTANCE_WR(ctx, 0x410/4, 0x00000101);
	INSTANCE_WR(ctx, 0x424/4, 0x00000111);
	INSTANCE_WR(ctx, 0x428/4, 0x00000060);
	INSTANCE_WR(ctx, 0x444/4, 0x00000080);
	INSTANCE_WR(ctx, 0x448/4, 0xffff0000);
	INSTANCE_WR(ctx, 0x44c/4, 0x00000001);
	INSTANCE_WR(ctx, 0x460/4, 0x44400000);
	INSTANCE_WR(ctx, 0x48c/4, 0xffff0000);
	for(i = 0x4e0; i< 0x4e8; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0fff0000);
	INSTANCE_WR(ctx, 0x4ec/4, 0x00011100);
	for(i = 0x508; i< 0x548; i += 4)
		INSTANCE_WR(ctx, i/4, 0x07ff0000);
	INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff);
	INSTANCE_WR(ctx, 0x58c/4, 0x00000080);
	INSTANCE_WR(ctx, 0x590/4, 0x30201000);
	INSTANCE_WR(ctx, 0x594/4, 0x70605040);
	INSTANCE_WR(ctx, 0x598/4, 0xb8a89888);
	INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8);
	INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000);
	for(i = 0x600; i< 0x640; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00010588);
	for(i = 0x640; i< 0x680; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00030303);
	for(i = 0x6c0; i< 0x700; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0008aae4);
	for(i = 0x700; i< 0x740; i += 4)
		INSTANCE_WR(ctx, i/4, 0x01012000);
	for(i = 0x740; i< 0x780; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080008);
	INSTANCE_WR(ctx, 0x85c/4, 0x00040000);
	INSTANCE_WR(ctx, 0x860/4, 0x00010000);
	for(i = 0x864; i< 0x874; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00040004);
	for(i = 0x1f18; i<= 0x3088 ; i+= 16) {
		INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
		INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
		INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);