/* i830_dma.c -- DMA support for the I830 -*- linux-c -*- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: Rickard E. (Rik) Faith * Jeff Hartmann * Keith Whitwell * Abraham vd Merwe * */ #include "i830.h" #include "drmP.h" #include "drm.h" #include "i830_drm.h" #include "i830_drv.h" #include /* For task queue support */ #include /* For FASTCALL on unlock_page() */ #include #include #ifdef DO_MUNMAP_4_ARGS #define DO_MUNMAP(m, a, l) do_munmap(m, a, l, 1) #else #define DO_MUNMAP(m, a, l) do_munmap(m, a, l) #endif #define I830_BUF_FREE 2 #define I830_BUF_CLIENT 1 #define I830_BUF_HARDWARE 0 #define I830_BUF_UNMAPPED 0 #define I830_BUF_MAPPED 1 static inline void i830_print_status_page(drm_device_t *dev) { drm_device_dma_t *dma = dev->dma; drm_i830_private_t *dev_priv = dev->dev_private; u32 *temp = dev_priv->hw_status_page; int i; DRM_DEBUG( "hw_status: Interrupt Status : %x\n", temp[0]); DRM_DEBUG( "hw_status: LpRing Head ptr : %x\n", temp[1]); DRM_DEBUG( "hw_status: IRing Head ptr : %x\n", temp[2]); DRM_DEBUG( "hw_status: Reserved : %x\n", temp[3]); DRM_DEBUG( "hw_status: Driver Counter : %d\n", temp[5]); for(i = 9; i < dma->buf_count + 9; i++) { DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 9, temp[i]); } } static drm_buf_t *i830_freelist_get(drm_device_t *dev) { drm_device_dma_t *dma = dev->dma; int i; int used; /* Linear search might not be the best solution */ for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i830_buf_priv_t *buf_priv = buf->dev_private; /* In use is already a pointer */ used = cmpxchg(buf_priv->in_use, I830_BUF_FREE, I830_BUF_CLIENT); if(used == I830_BUF_FREE) { return buf; } } return NULL; } /* This should only be called if the buffer is not sent to the hardware * yet, the hardware updates in use for us once its on the ring buffer. */ static int i830_freelist_put(drm_device_t *dev, drm_buf_t *buf) { drm_i830_buf_priv_t *buf_priv = buf->dev_private; int used; /* In use is already a pointer */ used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); if(used != I830_BUF_CLIENT) { DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); return -EINVAL; } return 0; } static struct file_operations i830_buffer_fops = { .open = DRM(open), .flush = DRM(flush), .release = DRM(release), .ioctl = DRM(ioctl), .mmap = i830_mmap_buffers, .fasync = DRM(fasync), }; int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma) { drm_file_t *priv = filp->private_data; drm_device_t *dev; drm_i830_private_t *dev_priv; drm_buf_t *buf; drm_i830_buf_priv_t *buf_priv; lock_kernel(); dev = priv->dev; dev_priv = dev->dev_private; buf = dev_priv->mmap_buffer; buf_priv = buf->dev_private; vma->vm_flags |= (VM_IO | VM_DONTCOPY); vma->vm_file = filp; buf_priv->currently_mapped = I830_BUF_MAPPED; unlock_kernel(); if (remap_page_range(DRM_RPR_ARG(vma) vma->vm_start, VM_OFFSET(vma), vma->vm_end - vma->vm_start, vma->vm_page_prot)) return -EAGAIN; return 0; } static int i830_map_buffer(drm_buf_t *buf, struct file *filp) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i830_buf_priv_t *buf_priv = buf->dev_private; drm_i830_private_t *dev_priv = dev->dev_private; struct file_operations *old_fops; unsigned long virtual; int retcode = 0; if(buf_priv->currently_mapped == I830_BUF_MAPPED) return -EINVAL; down_write( ¤t->mm->mmap_sem ); old_fops = filp->f_op; filp->f_op = &i830_buffer_fops; dev_priv->mmap_buffer = buf; virtual = do_mmap(filp, 0, buf->total, PROT_READ|PROT_WRITE, MAP_SHARED, buf->bus_address); dev_priv->mmap_buffer = NULL; filp->f_op = old_fops; if (IS_ERR((void *)virtual)) { /* ugh */ /* Real error */ DRM_ERROR("mmap error\n"); retcode = virtual; buf_priv->virtual = NULL; } else { buf_priv->virtual = (void __user *)virtual; } up_write( ¤t->mm->mmap_sem ); return retcode; } static int i830_unmap_buffer(drm_buf_t *buf) { drm_i830_buf_priv_t *buf_priv = buf->dev_private; int retcode = 0; if(buf_priv->currently_mapped != I830_BUF_MAPPED) return -EINVAL; down_write(¤t->mm->mmap_sem); retcode = DO_MUNMAP(current->mm, (unsigned long)buf_priv->virtual, (size_t) buf->total); up_write(¤t->mm->mmap_sem); buf_priv->currently_mapped = I830_BUF_UNMAPPED; buf_priv->virtual = NULL; return retcode; } static int i830_dma_get_buffer(drm_device_t *dev, drm_i830_dma_t *d, struct file *filp) { drm_buf_t *buf; drm_i830_buf_priv_t *buf_priv; int retcode = 0; buf = i830_freelist_get(dev); if (!buf) { retcode = -ENOMEM; DRM_DEBUG("retcode=%d\n", retcode); return retcode; } retcode = i830_map_buffer(buf, filp); if(retcode) { i830_freelist_put(dev, buf); DRM_ERROR("mapbuf failed, retcode %d\n", retcode); return retcode; } buf->filp = filp; buf_priv = buf->dev_private; d->granted = 1; d->request_idx = buf->idx; d->request_size = buf->total; d->virtual = buf_priv->virtual; return retcode; } int i830_dma_cleanup(drm_device_t *dev) { drm_device_dma_t *dma = dev->dma; /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ if (dev->irq_enabled) DRM(irq_uninstall)(dev); if (dev->dev_private) { int i; drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; if (dev_priv->ring.virtual_start) { DRM(ioremapfree)((void *) dev_priv->ring.virtual_start, dev_priv->ring.Size, dev); } if (dev_priv->hw_status_page) { pci_free_consistent(dev->pdev, PAGE_SIZE, dev_priv->hw_status_page, dev_priv->dma_status_page); /* Need to rewrite hardware status page */ I830_WRITE(0x02080, 0x1ffff000); } DRM(free)(dev->dev_private, sizeof(drm_i830_private_t), DRM_MEM_DRIVER); dev->dev_private = NULL; for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i830_buf_priv_t *buf_priv = buf->dev_private; if ( buf_priv->kernel_virtual && buf->total ) DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total, dev); } } return 0; } int i830_wait_ring(drm_device_t *dev, int n, const char *caller) { drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_ring_buffer_t *ring = &(dev_priv->ring); int iters = 0; unsigned long end; unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; end = jiffies + (HZ*3); while (ring->space < n) { ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; ring->space = ring->head - (ring->tail+8); if (ring->space < 0) ring->space += ring->Size; if (ring->head != last_head) { end = jiffies + (HZ*3); last_head = ring->head; } iters++; if(time_before(end, jiffies)) { DRM_ERROR("space: %d wanted %d\n", ring->space, n); DRM_ERROR("lockup\n"); goto out_wait_ring; } udelay(1); dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; } out_wait_ring: return iters; } static void i830_kernel_lost_context(drm_device_t *dev) { drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_ring_buffer_t *ring = &(dev_priv->ring); ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR; ring->space = ring->head - (ring->tail+8); if (ring->space < 0) ring->space += ring->Size; if (ring->head == ring->tail) dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY; } static int i830_freelist_init(drm_device_t *dev, drm_i830_private_t *dev_priv) { drm_device_dma_t *dma = dev->dma; int my_idx = 36; u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); int i; if(dma->buf_count > 1019) { /* Not enough space in the status page for the freelist */ return -EINVAL; } for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i830_buf_priv_t *buf_priv = buf->dev_private; buf_priv->in_use = hw_status++; buf_priv->my_use_idx = my_idx; my_idx += 4; *buf_priv->in_use = I830_BUF_FREE; buf_priv->kernel_virtual = DRM(ioremap)(buf->bus_address, buf->total, dev); } return 0; } static int i830_dma_initialize(drm_device_t *dev, drm_i830_private_t *dev_priv, drm_i830_init_t *init) { struct list_head *list; memset(dev_priv, 0, sizeof(drm_i830_private_t)); list_for_each(list, &dev->maplist->head) { drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); if( r_list->map && r_list->map->type == _DRM_SHM && r_list->map->flags & _DRM_CONTAINS_LOCK ) { dev_priv->sarea_map = r_list->map; break; } } if(!dev_priv->sarea_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find sarea!\n"); return -EINVAL; } dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); if(!dev_priv->mmio_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find mmio map!\n"); return -EINVAL; } dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); if(!dev->agp_buffer_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find dma buffer map!\n"); return -EINVAL; } dev_priv->sarea_priv = (drm_i830_sarea_t *) ((u8 *)dev_priv->sarea_map->handle + init->sarea_priv_offset); dev_priv->ring.Start = init->ring_start; dev_priv->ring.End = init->ring_end; dev_priv->ring.Size = init->ring_size; dev_priv->ring.virtual_start = DRM(ioremap)(dev->agp->base + init->ring_start, init->ring_size, dev); if (dev_priv->ring.virtual_start == NULL) { dev->dev_private = (void *) dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); return -ENOMEM; } dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; dev_priv->w = init->w; dev_priv->h = init->h; dev_priv->pitch = init->pitch; dev_priv->back_offset = init->back_offset; dev_priv->depth_offset = init->depth_offset; dev_priv->front_offset = init->front_offset; dev_priv->front_di1 = init->front_offset | init->pitch_bits; dev_priv->back_di1 = init->back_offset | init->pitch_bits; dev_priv->zi1 = init->depth_offset | init->pitch_bits; DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1); DRM_DEBUG("back_offset %x\n", dev_priv->back_offset); DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1); DRM_DEBUG("pitch_bits %x\n", init->pitch_bits); dev_priv->cpp = init->cpp; /* We are using separate values as placeholders for mechanisms for * private backbuffer/depthbuffer usage. */ dev_priv->back_pitch = init->back_pitch; dev_priv->depth_pitch = init->depth_pitch; dev_priv->do_boxes = 0; dev_priv->use_mi_batchbuffer_start = 0; /* Program Hardware Status Page */ dev_priv->hw_status_page = pci_alloc_consistent(dev->pdev, PAGE_SIZE, &dev_priv->dma_status_page); if (!dev_priv->hw_status_page) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("Can not allocate hardware status page\n"); return -ENOMEM; } memset(dev_priv->hw_status_page, 0, PAGE_SIZE); DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); I830_WRITE(0x02080, dev_priv->dma_status_page); DRM_DEBUG("Enabled hardware status page\n"); /* Now we need to init our freelist */ if(i830_freelist_init(dev, dev_priv) != 0) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("Not enough space in the status page for" " the freelist\n"); return -ENOMEM; } dev->dev_private = (void *)dev_priv; return 0; } int i830_dma_init(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv; drm_i830_init_t init; int retcode = 0; if (copy_from_user(&init, (void * __user) arg, sizeof(init))) return -EFAULT; switch(init.func) { case I830_INIT_DMA: dev_priv = DRM(alloc)(sizeof(drm_i830_private_t), DRM_MEM_DRIVER); if(dev_priv == NULL) return -ENOMEM; retcode = i830_dma_initialize(dev, dev_priv, &init); break; case I830_CLEANUP_DMA: retcode = i830_dma_cleanup(dev); break; default: retcode = -EINVAL; break; } return retcode; } #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) #define ST1_ENABLE (1<<16) #define ST1_MASK (0xffff) /* Most efficient way to verify state for the i830 is as it is * emitted. Non-conformant state is silently dropped. */ static void i830EmitContextVerified( drm_device_t *dev, unsigned int *code ) { drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; BEGIN_LP_RING( I830_CTX_SETUP_SIZE + 4 ); for ( i = 0 ; i < I830_CTXREG_BLENDCOLR0 ; i++ ) { tmp = code[i]; if ((tmp & (7<<29)) == CMD_3D && (tmp & (0x1f<<24)) < (0x1d<<24)) { OUT_RING( tmp ); j++; } else { DRM_ERROR("Skipping %d\n", i); } } OUT_RING( STATE3D_CONST_BLEND_COLOR_CMD ); OUT_RING( code[I830_CTXREG_BLENDCOLR] ); j += 2; for ( i = I830_CTXREG_VF ; i < I830_CTXREG_MCSB0 ; i++ ) { tmp = code[i]; if ((tmp & (7<<29)) == CMD_3D && (tmp & (0x1f<<24)) < (0x1d<<24)) { OUT_RING( tmp ); j++; } else { DRM_ERROR("Skipping %d\n", i); } } OUT_RING( STATE3D_MAP_COORD_SETBIND_CMD ); OUT_RING( code[I830_CTXREG_MCSB1] ); j += 2; if (j & 1) OUT_RING( 0 ); ADVANCE_LP_RING(); } static void i830EmitTexVerified( drm_device_t *dev, unsigned int *code ) { drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO || (code[I830_TEXREG_MI0] & ~(0xf*LOAD_TEXTURE_MAP0)) == (STATE3D_LOAD_STATE_IMMEDIATE_2|4)) { BEGIN_LP_RING( I830_TEX_SETUP_SIZE ); OUT_RING( code[I830_TEXREG_MI0] ); /* TM0LI */ OUT_RING( code[I830_TEXREG_MI1] ); /* TM0S0 */ OUT_RING( code[I830_TEXREG_MI2] ); /* TM0S1 */ OUT_RING( code[I830_TEXREG_MI3] ); /* TM0S2 */ OUT_RING( code[I830_TEXREG_MI4] ); /* TM0S3 */ OUT_RING( code[I830_TEXREG_MI5] ); /* TM0S4 */ for ( i = 6 ; i < I830_TEX_SETUP_SIZE ; i++ ) { tmp = code[i]; OUT_RING( tmp ); j++; } if (j & 1) OUT_RING( 0 ); ADVANCE_LP_RING(); } else printk("rejected packet %x\n", code[0]); } static void i830EmitTexBlendVerified( drm_device_t *dev, unsigned int *code, unsigned int num) { drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; if (!num) return; BEGIN_LP_RING( num + 1 ); for ( i = 0 ; i < num ; i++ ) { tmp = code[i]; OUT_RING( tmp ); j++; } if (j & 1) OUT_RING( 0 ); ADVANCE_LP_RING(); } static void i830EmitTexPalette( drm_device_t *dev, unsigned int *palette, int number, int is_shared ) { drm_i830_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; return; BEGIN_LP_RING( 258 ); if(is_shared == 1) { OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH); } else { OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number)); } for(i = 0; i < 256; i++) { OUT_RING(palette[i]); } OUT_RING(0); /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop! */ } /* Need to do some additional checking when setting the dest buffer. */ static void i830EmitDestVerified( drm_device_t *dev, unsigned int *code ) { drm_i830_private_t *dev_priv = dev->dev_private; unsigned int tmp; RING_LOCALS; BEGIN_LP_RING( I830_DEST_SETUP_SIZE + 10 ); tmp = code[I830_DESTREG_CBUFADDR]; if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { if (((int)outring) & 8) { OUT_RING(0); OUT_RING(0); } OUT_RING( CMD_OP_DESTBUFFER_INFO ); OUT_RING( BUF_3D_ID_COLOR_BACK | BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) | BUF_3D_USE_FENCE); OUT_RING( tmp ); OUT_RING( 0 ); OUT_RING( CMD_OP_DESTBUFFER_INFO ); OUT_RING( BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE | BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp)); OUT_RING( dev_priv->zi1 ); OUT_RING( 0 ); } else { DRM_ERROR("bad di1 %x (allow %x or %x)\n", tmp, dev_priv->front_di1, dev_priv->back_di1); } /* invarient: */ OUT_RING( GFX_OP_DESTBUFFER_VARS ); OUT_RING( code[I830_DESTREG_DV1] ); OUT_RING( GFX_OP_DRAWRECT_INFO ); OUT_RING( code[I830_DESTREG_DR1] ); OUT_RING( code[I830_DESTREG_DR2] ); OUT_RING( code[I830_DESTREG_DR3] ); OUT_RING( code[I830_DESTREG_DR4] ); /* Need to verify this */ tmp = code[I830_DESTREG_SENABLE]; if((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) { OUT_RING( tmp ); } else { DRM_ERROR("bad scissor enable\n"); OUT_RING( 0 ); } OUT_RING( GFX_OP_SCISSOR_RECT ); OUT_RING( code[I830_DESTREG_SR1] ); OUT_RING( code[I830_DESTREG_SR2] ); OUT_RING( 0 ); ADVANCE_LP_RING(); } static void i830EmitStippleVerified( drm_device_t *dev, unsigned int *code ) { drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; BEGIN_LP_RING( 2 ); OUT_RING( GFX_OP_STIPPLE ); OUT_RING( code[1] ); ADVANCE_LP_RING(); } static void i830EmitState( drm_device_t *dev ) { drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); if (dirty & I830_UPLOAD_BUFFERS) { i830EmitDestVerified( dev, sarea_priv->BufferState ); sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS; } if (dirty & I830_UPLOAD_CTX) { i830EmitContextVerified( dev, sarea_priv->ContextState ); sarea_priv->dirty &= ~I830_UPLOAD_CTX; } if (dirty & I830_UPLOAD_TEX0) { i830EmitTexVerified( dev, sarea_priv->TexState[0] ); sarea_priv->dirty &= ~I830_UPLOAD_TEX0; } if (dirty & I830_UPLOAD_TEX1) { i830EmitTexVerified( dev, sarea_priv->TexState[1] ); sarea_priv->dirty &= ~I830_UPLOAD_TEX1; } if (dirty & I830_UPLOAD_TEXBLEND0) { i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[0], sarea_priv->TexBlendStateWordsUsed[0]); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0; } if (dirty & I830_UPLOAD_TEXBLEND1) { i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[1], sarea_priv->TexBlendStateWordsUsed[1]); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1; } if (dirty & I830_UPLOAD_TEX_PALETTE_SHARED) { i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1); } else { if (dirty & I830_UPLOAD_TEX_PALETTE_N(0)) { i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0); sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0); } if (dirty & I830_UPLOAD_TEX_PALETTE_N(1)) { i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0); sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1); } /* 1.3: */ #if 0 if (dirty & I830_UPLOAD_TEX_PALETTE_N(2)) { i830EmitTexPalette(dev, sarea_priv->Palette2[0], 0, 0); sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2); } if (dirty & I830_UPLOAD_TEX_PALETTE_N(3)) { i830EmitTexPalette(dev, sarea_priv->Palette2[1], 1, 0); sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2); } #endif } /* 1.3: */ if (dirty & I830_UPLOAD_STIPPLE) { i830EmitStippleVerified( dev, sarea_priv->StippleState); sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE; } if (dirty & I830_UPLOAD_TEX2) { i830EmitTexVerified( dev, sarea_priv->TexState2 ); sarea_priv->dirty &= ~I830_UPLOAD_TEX2; } if (dirty & I830_UPLOAD_TEX3) { i830EmitTexVerified( dev, sarea_priv->TexState3 ); sarea_priv->dirty &= ~I830_UPLOAD_TEX3; } if (dirty & I830_UPLOAD_TEXBLEND2) { i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState2, sarea_priv->TexBlendStateWordsUsed2); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2; } if (dirty & I830_UPLOAD_TEXBLEND3) { i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState3, sarea_priv->TexBlendStateWordsUsed3); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3; } } /* ================================================================ * Performance monitoring functions */ static void i830_fill_box( drm_device_t *dev, int x, int y, int w, int h, int r, int g, int b ) { drm_i830_private_t *dev_priv = dev->dev_private; u32 color; unsigned int BR13, CMD; RING_LOCALS; BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1<<24); CMD = XY_COLOR_BLT_CMD; x += dev_priv->sarea_priv->boxes[0].x1; y += dev_priv->sarea_priv->boxes[0].y1; if (dev_priv->cpp == 4) { BR13 |= (1<<25); CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); color = (((0xff) << 24) | (r << 16) | (g << 8) | b); } else { color = (((r & 0xf8) << 8) | ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); } BEGIN_LP_RING( 6 ); OUT_RING( CMD ); OUT_RING( BR13 ); OUT_RING( (y << 16) | x ); OUT_RING( ((y+h) << 16) | (x+w) ); if ( dev_priv->current_page == 1 ) { OUT_RING( dev_priv->front_offset ); } else { OUT_RING( dev_priv->back_offset ); } OUT_RING( color ); ADVANCE_LP_RING(); } static void i830_cp_performance_boxes( drm_device_t *dev ) { drm_i830_private_t *dev_priv = dev->dev_private; /* Purple box for page flipping */ if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP ) i830_fill_box( dev, 4, 4, 8, 8, 255, 0, 255 ); /* Red box if we have to wait for idle at any point */ if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT ) i830_fill_box( dev, 16, 4, 8, 8, 255, 0, 0 ); /* Blue box: lost context? */ if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT ) i830_fill_box( dev, 28, 4, 8, 8, 0, 0, 255 ); /* Yellow box for texture swaps */ if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD ) i830_fill_box( dev, 40, 4, 8, 8, 255, 255, 0 ); /* Green box if hardware never idles (as far as we can tell) */ if ( !(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY) ) i830_fill_box( dev, 64, 4, 8, 8, 0, 255, 0 ); /* Draw bars indicating number of buffers allocated * (not a great measure, easily confused) */ if (dev_priv->dma_used) { int bar = dev_priv->dma_used / 10240; if (bar > 100) bar = 100; if (bar < 1) bar = 1; i830_fill_box( dev, 4, 16, bar, 4, 196, 128, 128 ); dev_priv->dma_used = 0; } dev_priv->sarea_priv->perf_boxes = 0; } static void i830_dma_dispatch_clear( drm_device_t *dev, int flags, unsigned int clear_color, unsigned int clear_zval, unsigned int clear_depthmask) { drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; int cpp = dev_priv->cpp; int i; unsigned int BR13, CMD, D_CMD; RING_LOCALS; if ( dev_priv->current_page == 1 ) { unsigned int tmp = flags; flags &= ~(I830_FRONT | I830_BACK); if ( tmp & I830_FRONT ) flags |= I830_BACK; if ( tmp & I830_BACK ) flags |= I830_FRONT; } i830_kernel_lost_context(dev); switch(cpp) { case 2: BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); D_CMD = CMD = XY_COLOR_BLT_CMD; break; case 4: BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24) | (1<<25); CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); D_CMD = XY_COLOR_BLT_CMD; if(clear_depthmask & 0x00ffffff) D_CMD |= XY_COLOR_BLT_WRITE_RGB; if(clear_depthmask & 0xff000000) D_CMD |= XY_COLOR_BLT_WRITE_ALPHA; break; default: BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); D_CMD = CMD = XY_COLOR_BLT_CMD; break; } if (nbox > I830_NR_SAREA_CLIPRECTS) nbox = I830_NR_SAREA_CLIPRECTS; for (i = 0 ; i < nbox ; i++, pbox++) { if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; if ( flags & I830_FRONT ) { DRM_DEBUG("clear front\n"); BEGIN_LP_RING( 6 ); OUT_RING( CMD ); OUT_RING( BR13 ); OUT_RING( (pbox->y1 << 16) | pbox->x1 ); OUT_RING( (pbox->y2 << 16) | pbox->x2 ); OUT_RING( dev_priv->front_offset ); OUT_RING( clear_color ); ADVANCE_LP_RING(); } if ( flags & I830_BACK ) { DRM_DEBUG("clear back\n"); BEGIN_LP_RING( 6 ); OUT_RING( CMD ); OUT_RING( BR13 ); OUT_RING( (pbox->y1 << 16) | pbox->x1 ); OUT_RING( (pbox->y2 << 16) | pbox->x2 ); OUT_RING( dev_priv->back_offset ); OUT_RING( clear_color ); ADVANCE_LP_RING(); } if ( flags & I830_DEPTH ) { DRM_DEBUG("clear depth\n"); BEGIN_LP_RING( 6 ); OUT_RING( D_CMD ); OUT_RING( BR13 ); OUT_RING( (pbox->y1 << 16) | pbox->x1 ); OUT_RING( (pbox->y2 << 16) | pbox->x2 ); OUT_RING( dev_priv->depth_offset ); OUT_RING( clear_zval ); ADVANCE_LP_RING(); } } } static void i830_dma_dispatch_swap( drm_device_t *dev ) { drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; int cpp = dev_priv->cpp; int i; unsigned int CMD, BR13; RING_LOCALS; DRM_DEBUG("swapbuffers\n"); i830_kernel_lost_context(dev); if (dev_priv->do_boxes) i830_cp_performance_boxes( dev ); switch(cpp) { case 2: BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); CMD = XY_SRC_COPY_BLT_CMD; break; case 4: BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24) | (1<<25); CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB); break; default: BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); CMD = XY_SRC_COPY_BLT_CMD; break; } if (nbox > I830_NR_SAREA_CLIPRECTS) nbox = I830_NR_SAREA_CLIPRECTS; for (i = 0 ; i < nbox; i++, pbox++) { if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n", pbox->x1, pbox->y1, pbox->x2, pbox->y2); BEGIN_LP_RING( 8 ); OUT_RING( CMD ); OUT_RING( BR13 ); OUT_RING( (pbox->y1 << 16) | pbox->x1 ); OUT_RING( (pbox->y2 << 16) | pbox->x2 ); if (dev_priv->current_page == 0) OUT_RING( dev_priv->front_offset ); else OUT_RING( dev_priv->back_offset ); OUT_RING( (pbox->y1 << 16) | pbox->x1 ); OUT_RING( BR13 & 0xffff ); if (dev_priv->current_page == 0) OUT_RING( dev_priv->back_offset ); else OUT_RING( dev_priv->front_offset ); ADVANCE_LP_RING(); } } static void i830_dma_dispatch_flip( drm_device_t *dev ) { drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", __FUNCTION__, dev_priv->current_page, dev_priv->sarea_priv->pf_current_page); i830_kernel_lost_context(dev); if (dev_priv->do_boxes) { dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP; i830_cp_performance_boxes( dev ); } BEGIN_LP_RING( 2 ); OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); OUT_RING( 0 ); ADVANCE_LP_RING(); BEGIN_LP_RING( 6 ); OUT_RING( CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP ); OUT_RING( 0 ); if ( dev_priv->current_page == 0 ) { OUT_RING( dev_priv->back_offset ); dev_priv->current_page = 1; } else { OUT_RING( dev_priv->front_offset ); dev_priv->current_page = 0; } OUT_RING(0); ADVANCE_LP_RING(); BEGIN_LP_RING( 2 ); OUT_RING( MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP ); OUT_RING( 0 ); ADVANCE_LP_RING(); dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; } static void i830_dma_dispatch_vertex(drm_device_t *dev, drm_buf_t *buf, int discard, int used) { drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_buf_priv_t *buf_priv = buf->dev_private; drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_clip_rect_t *box = sarea_priv->boxes; int nbox = sarea_priv->nbox; unsigned long address = (unsigned long)buf->bus_address; unsigned long start = address - dev->agp->base; int i = 0, u; RING_LOCALS; i830_kernel_lost_context(dev); if (nbox > I830_NR_SAREA_CLIPRECTS) nbox = I830_NR_SAREA_CLIPRECTS; if (discard) { u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_HARDWARE); if(u != I830_BUF_CLIENT) { DRM_DEBUG("xxxx 2\n"); } } if (used > 4*1023) used = 0; if (sarea_priv->dirty) i830EmitState( dev ); DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", address, used, nbox); dev_priv->counter++; DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter); DRM_DEBUG( "i830_dma_dispatch\n"); DRM_DEBUG( "start : %lx\n", start); DRM_DEBUG( "used : %d\n", used); DRM_DEBUG( "start + used - 4 : %ld\n", start + used - 4); if (buf_priv->currently_mapped == I830_BUF_MAPPED) { u32 *vp = buf_priv->kernel_virtual; vp[0] = (GFX_OP_PRIMITIVE | sarea_priv->vertex_prim | ((used/4)-2)); if (dev_priv->use_mi_batchbuffer_start) { vp[used/4] = MI_BATCH_BUFFER_END; used += 4; } if (used & 4) { vp[used/4] = 0; used += 4; } i830_unmap_buffer(buf); } if (used) { do { if (i < nbox) { BEGIN_LP_RING(6); OUT_RING( GFX_OP_DRAWRECT_INFO ); OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR1] ); OUT_RING( box[i].x1 | (box[i].y1<<16) ); OUT_RING( box[i].x2 | (box[i].y2<<16) ); OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR4] ); OUT_RING( 0 ); ADVANCE_LP_RING(); } if (dev_priv->use_mi_batchbuffer_start) { BEGIN_LP_RING(2); OUT_RING( MI_BATCH_BUFFER_START | (2<<6) ); OUT_RING( start | MI_BATCH_NON_SECURE ); ADVANCE_LP_RING(); } else { BEGIN_LP_RING(4); OUT_RING( MI_BATCH_BUFFER ); OUT_RING( start | MI_BATCH_NON_SECURE ); OUT_RING( start + used - 4 ); OUT_RING( 0 ); ADVANCE_LP_RING(); } } while (++i < nbox); } if (discard) { dev_priv->counter++; (void) cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_HARDWARE); BEGIN_LP_RING(8); OUT_RING( CMD_STORE_DWORD_IDX ); OUT_RING( 20 ); OUT_RING( dev_priv->counter ); OUT_RING( CMD_STORE_DWORD_IDX ); OUT_RING( buf_priv->my_use_idx ); OUT_RING( I830_BUF_FREE ); OUT_RING( CMD_REPORT_HEAD ); OUT_RING( 0 ); ADVANCE_LP_RING(); } } void i830_dma_quiescent(drm_device_t *dev) { drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; i830_kernel_lost_context(dev); BEGIN_LP_RING(4); OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); OUT_RING( CMD_REPORT_HEAD ); OUT_RING( 0 ); OUT_RING( 0 ); ADVANCE_LP_RING(); i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); } static int i830_flush_queue(drm_device_t *dev) { drm_i830_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; int i, ret = 0; RING_LOCALS; i830_kernel_lost_context(dev); BEGIN_LP_RING(2); OUT_RING( CMD_REPORT_HEAD ); OUT_RING( 0 ); ADVANCE_LP_RING(); i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i830_buf_priv_t *buf_priv = buf->dev_private; int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE, I830_BUF_FREE); if (used == I830_BUF_HARDWARE) DRM_DEBUG("reclaimed from HARDWARE\n"); if (used == I830_BUF_CLIENT) DRM_DEBUG("still on client\n"); } return ret; } /* Must be called with the lock held */ void i830_reclaim_buffers( drm_device_t *dev, struct file *filp ) { drm_device_dma_t *dma = dev->dma; int i; if (!dma) return; if (!dev->dev_private) return; if (!dma->buflist) return; i830_flush_queue(dev); for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i830_buf_priv_t *buf_priv = buf->dev_private; if (buf->filp == filp && buf_priv) { int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); if (used == I830_BUF_CLIENT) DRM_DEBUG("reclaimed from client\n"); if(buf_priv->currently_mapped == I830_BUF_MAPPED) buf_priv->currently_mapped = I830_BUF_UNMAPPED; } } } int i830_flush_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_flush_ioctl called without lock held\n"); return -EINVAL; } i830_flush_queue(dev); return 0; } int i830_dma_vertex(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; u32 *hw_status = dev_priv->hw_status_page; drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) dev_priv->sarea_priv; drm_i830_vertex_t vertex; if (copy_from_user(&vertex, (drm_i830_vertex_t __user *)arg, sizeof(vertex))) return -EFAULT; if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_dma_vertex called without lock held\n"); return -EINVAL; } DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n", vertex.idx, vertex.used, vertex.discard); if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; i830_dma_dispatch_vertex( dev, dma->buflist[ vertex.idx ], vertex.discard, vertex.used ); sarea_priv->last_enqueue = dev_priv->counter-1; sarea_priv->last_dispatch = (int) hw_status[5]; return 0; } int i830_clear_bufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i830_clear_t clear; if (copy_from_user(&clear, (drm_i830_clear_t __user *)arg, sizeof(clear))) return -EFAULT; if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_clear_bufs called without lock held\n"); return -EINVAL; } /* GH: Someone's doing nasty things... */ if (!dev->dev_private) { return -EINVAL; } i830_dma_dispatch_clear( dev, clear.flags, clear.clear_color, clear.clear_depth, clear.clear_depthmask); return 0; } int i830_swap_bufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; DRM_DEBUG("i830_swap_bufs\n"); if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_swap_buf called without lock held\n"); return -EINVAL; } i830_dma_dispatch_swap( dev ); return 0; } /* Not sure why this isn't set all the time: */ static void i830_do_init_pageflip( drm_device_t *dev ) { drm_i830_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); dev_priv->page_flipping = 1; dev_priv->current_page = 0; dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; } int i830_do_cleanup_pageflip( drm_device_t *dev ) { drm_i830_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); if (dev_priv->current_page != 0) i830_dma_dispatch_flip( dev ); dev_priv->page_flipping = 0; return 0; } int i830_flip_bufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_flip_buf called without lock held\n"); return -EINVAL; } if (!dev_priv->page_flipping) i830_do_init_pageflip( dev ); i830_dma_dispatch_flip( dev ); return 0; } int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; u32 *hw_status = dev_priv->hw_status_page; drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) dev_priv->sarea_priv; sarea_priv->last_dispatch = (int) hw_status[5]; return 0; } int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; int retcode = 0; drm_i830_dma_t d; drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; u32 *hw_status = dev_priv->hw_status_page; drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) dev_priv->sarea_priv; DRM_DEBUG("getbuf\n"); if (copy_from_user(&d, (drm_i830_dma_t __user *)arg, sizeof(d))) return -EFAULT; if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_dma called without lock held\n"); return -EINVAL; } d.granted = 0; retcode = i830_dma_get_buffer(dev, &d, filp); DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n", current->pid, retcode, d.granted); if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) return -EFAULT; sarea_priv->last_dispatch = (int) hw_status[5]; return retcode; } int i830_copybuf(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { /* Never copy - 2.4.x doesn't need it */ return 0; } int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { return 0; } int i830_getparam( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_getparam_t param; int value; if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); return -EINVAL; } if (copy_from_user(¶m, (drm_i830_getparam_t __user *)arg, sizeof(param) )) return -EFAULT; switch( param.param ) { case I830_PARAM_IRQ_ACTIVE: value = dev->irq_enabled; break; default: return -EINVAL; } if ( copy_to_user( param.value, &value, sizeof(int) ) ) { DRM_ERROR( "copy_to_user\n" ); return -EFAULT; } return 0; } int i830_setparam( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_setparam_t param; if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); return -EINVAL; } if (copy_from_user(¶m, (drm_i830_setparam_t __user *)arg, sizeof(param) )) return -EFAULT; switch( param.param ) { case I830_SETPARAM_USE_MI_BATCHBUFFER_START: dev_priv->use_mi_batchbuffer_start = param.value; break; default: return -EINVAL; } return 0; } static void i830_driver_pretakedown(drm_device_t *dev) { i830_dma_cleanup( dev ); } static void i830_driver_release(drm_device_t *dev, struct file *filp) { i830_reclaim_buffers(dev, filp); } static int i830_driver_dma_quiescent(drm_device_t *dev) { i830_dma_quiescent( dev ); return 0; } void i830_driver_register_fns(drm_device_t *dev) { dev->driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE; #if USE_IRQS dev->driver_features |= DRIVER_HAVE_IRQ | DRIVER_SHARED_IRQ; #endif dev->dev_priv_size = sizeof(drm_i830_buf_priv_t); dev->fn_tbl.pretakedown = i830_driver_pretakedown; dev->fn_tbl.release = i830_driver_release; dev->fn_tbl.dma_quiescent = i830_driver_dma_quiescent; dev->fn_tbl.reclaim_buffers = i830_reclaim_buffers; #if USE_IRQS dev->fn_tbl.irq_preinstall = i830_driver_irq_preinstall; dev->fn_tbl.irq_postinstall = i830_driver_irq_postinstall; dev->fn_tbl.irq_uninstall = i830_driver_irq_uninstall; dev->fn_tbl.irq_handler = i830_driver_irq_handler; #endif dev->counters += 4; dev->types[6] = _DRM_STAT_IRQ; dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; } /a> 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 
/*
 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_drv.h"

/* old legacy ATI BIOS routines */

/* COMBIOS table offsets */
enum radeon_combios_table_offset
{
	/* absolute offset tables */
	COMBIOS_ASIC_INIT_1_TABLE,
	COMBIOS_BIOS_SUPPORT_TABLE,
	COMBIOS_DAC_PROGRAMMING_TABLE,
	COMBIOS_MAX_COLOR_DEPTH_TABLE,
	COMBIOS_CRTC_INFO_TABLE,
	COMBIOS_PLL_INFO_TABLE,
	COMBIOS_TV_INFO_TABLE,
	COMBIOS_DFP_INFO_TABLE,
	COMBIOS_HW_CONFIG_INFO_TABLE,
	COMBIOS_MULTIMEDIA_INFO_TABLE,
	COMBIOS_TV_STD_PATCH_TABLE,
	COMBIOS_LCD_INFO_TABLE,
	COMBIOS_MOBILE_INFO_TABLE,
	COMBIOS_PLL_INIT_TABLE,
	COMBIOS_MEM_CONFIG_TABLE,
	COMBIOS_SAVE_MASK_TABLE,
	COMBIOS_HARDCODED_EDID_TABLE,
	COMBIOS_ASIC_INIT_2_TABLE,
	COMBIOS_CONNECTOR_INFO_TABLE,
	COMBIOS_DYN_CLK_1_TABLE,
	COMBIOS_RESERVED_MEM_TABLE,
	COMBIOS_EXT_TMDS_INFO_TABLE,
	COMBIOS_MEM_CLK_INFO_TABLE,
	COMBIOS_EXT_DAC_INFO_TABLE,
	COMBIOS_MISC_INFO_TABLE,
	COMBIOS_CRT_INFO_TABLE,
	COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
	COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
	COMBIOS_FAN_SPEED_INFO_TABLE,
	COMBIOS_OVERDRIVE_INFO_TABLE,
	COMBIOS_OEM_INFO_TABLE,
	COMBIOS_DYN_CLK_2_TABLE,
	COMBIOS_POWER_CONNECTOR_INFO_TABLE,
	COMBIOS_I2C_INFO_TABLE,
	/* relative offset tables */
	COMBIOS_ASIC_INIT_3_TABLE,	/* offset from misc info */
	COMBIOS_ASIC_INIT_4_TABLE,	/* offset from misc info */
	COMBIOS_ASIC_INIT_5_TABLE,	/* offset from misc info */
	COMBIOS_RAM_RESET_TABLE,	/* offset from mem config */
	COMBIOS_POWERPLAY_TABLE,	/* offset from mobile info */
	COMBIOS_GPIO_INFO_TABLE,	/* offset from mobile info */
	COMBIOS_LCD_DDC_INFO_TABLE,	/* offset from mobile info */
	COMBIOS_TMDS_POWER_TABLE,	/* offset from mobile info */
	COMBIOS_TMDS_POWER_ON_TABLE,	/* offset from tmds power */
	COMBIOS_TMDS_POWER_OFF_TABLE,	/* offset from tmds power */
};

enum radeon_combios_ddc
{
    DDC_NONE_DETECTED,
    DDC_MONID,
    DDC_DVI,
    DDC_VGA,
    DDC_CRT2,
    DDC_LCD,
    DDC_GPIO,
};

enum radeon_combios_connector
{
    CONNECTOR_NONE_LEGACY,
    CONNECTOR_PROPRIETARY_LEGACY,
    CONNECTOR_CRT_LEGACY,
    CONNECTOR_DVI_I_LEGACY,
    CONNECTOR_DVI_D_LEGACY,
    CONNECTOR_CTV_LEGACY,
    CONNECTOR_STV_LEGACY,
    CONNECTOR_UNSUPPORTED_LEGACY
};

static uint16_t combios_get_table_offset(struct drm_device *dev, enum radeon_combios_table_offset table)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	int rev;
	uint16_t offset = 0, check_offset;

	switch (table) {
	/* absolute offset tables */
	case COMBIOS_ASIC_INIT_1_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0xc);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_BIOS_SUPPORT_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x14);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_DAC_PROGRAMMING_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2a);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MAX_COLOR_DEPTH_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2c);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_CRTC_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_PLL_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x30);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_TV_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x32);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_DFP_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_HW_CONFIG_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x36);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MULTIMEDIA_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x38);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_TV_STD_PATCH_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x3e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_LCD_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x40);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MOBILE_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x42);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_PLL_INIT_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x46);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MEM_CONFIG_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x48);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_SAVE_MASK_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4a);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_HARDCODED_EDID_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4c);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_ASIC_INIT_2_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_CONNECTOR_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x50);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_DYN_CLK_1_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x52);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_RESERVED_MEM_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x54);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_EXT_TMDS_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x58);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MEM_CLK_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5a);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_EXT_DAC_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5c);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_MISC_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_CRT_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x60);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x62);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x64);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_FAN_SPEED_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x66);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_OVERDRIVE_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x68);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_OEM_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6a);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_DYN_CLK_2_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6c);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6e);
		if (check_offset)
			offset = check_offset;
		break;
	case COMBIOS_I2C_INFO_TABLE:
		check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x70);
		if (check_offset)
			offset = check_offset;
		break;
	/* relative offset tables */
	case COMBIOS_ASIC_INIT_3_TABLE:	/* offset from misc info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = radeon_bios8(dev_priv, check_offset);
			if (rev > 0) {
				check_offset = radeon_bios16(dev_priv, check_offset + 0x3);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_ASIC_INIT_4_TABLE:	/* offset from misc info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = radeon_bios8(dev_priv, check_offset);
			if (rev > 0) {
				check_offset = radeon_bios16(dev_priv, check_offset + 0x5);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_ASIC_INIT_5_TABLE:	/* offset from misc info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = radeon_bios8(dev_priv, check_offset);
			if (rev == 2) {
				check_offset = radeon_bios16(dev_priv, check_offset + 0x9);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_RAM_RESET_TABLE:	/* offset from mem config */
		check_offset = combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		if (check_offset) {
			while (radeon_bios8(dev_priv, check_offset++));
			check_offset += 2;
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_POWERPLAY_TABLE:	/* offset from mobile info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x11);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_GPIO_INFO_TABLE:	/* offset from mobile info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x13);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_LCD_DDC_INFO_TABLE:	/* offset from mobile info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x15);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_TMDS_POWER_TABLE:	        /* offset from mobile info */
		check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x17);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_TMDS_POWER_ON_TABLE:	/* offset from tmds power */
		check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x2);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_TMDS_POWER_OFF_TABLE:	/* offset from tmds power */
		check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		if (check_offset) {
			check_offset = radeon_bios16(dev_priv, check_offset + 0x4);
			if (check_offset)
				offset = check_offset;
		}
		break;
	default:
		break;
	}

	return offset;

}

struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
{
	struct radeon_i2c_bus_rec i2c;

	i2c.mask_clk_mask = RADEON_GPIO_EN_1;
	i2c.mask_data_mask = RADEON_GPIO_EN_0;
	i2c.a_clk_mask = RADEON_GPIO_A_1;
	i2c.a_data_mask = RADEON_GPIO_A_0;
	i2c.put_clk_mask = RADEON_GPIO_EN_1;
	i2c.put_data_mask = RADEON_GPIO_EN_0;
	i2c.get_clk_mask = RADEON_GPIO_Y_1;
	i2c.get_data_mask = RADEON_GPIO_Y_0;
	if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
	    (ddc_line == RADEON_MDGPIO_EN_REG)) {
		i2c.mask_clk_reg = ddc_line;
		i2c.mask_data_reg = ddc_line;
		i2c.a_clk_reg = ddc_line;
		i2c.a_data_reg = ddc_line;
		i2c.put_clk_reg = ddc_line;
		i2c.put_data_reg = ddc_line;
		i2c.get_clk_reg = ddc_line + 4;
		i2c.get_data_reg = ddc_line + 4;
	} else {
		i2c.mask_clk_reg = ddc_line;
		i2c.mask_data_reg = ddc_line;
		i2c.a_clk_reg = ddc_line;
		i2c.a_data_reg = ddc_line;
		i2c.put_clk_reg = ddc_line;
		i2c.put_data_reg = ddc_line;
		i2c.get_clk_reg = ddc_line;
		i2c.get_data_reg = ddc_line;
	}

	if (ddc_line)
		i2c.valid = true;
	else
		i2c.valid = false;

	return i2c;
}

bool radeon_combios_get_clock_info(struct drm_device *dev)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct radeon_mode_info *mode_info = &dev_priv->mode_info;
	uint16_t pll_info;
	struct radeon_pll *pll = &mode_info->pll;
	int8_t rev;

	pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
	if (pll_info) {
		rev = radeon_bios8(dev_priv, pll_info);

		pll->reference_freq = radeon_bios16(dev_priv, pll_info + 0xe);
		pll->reference_div = radeon_bios16(dev_priv, pll_info + 0x10);
		pll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x12);
		pll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x16);

		if (rev > 9) {
			pll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x36);
			pll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x3a);
		} else {
			pll->pll_in_min = 40;
			pll->pll_in_max = 500;
		}

		pll->xclk = radeon_bios16(dev_priv, pll_info + 0x08);

		// sclk/mclk use fixed point
		//sclk = radeon_bios16(pll_info + 8) / 100.0;
		//mclk = radeon_bios16(pll_info + 10) / 100.0;
		//if (sclk == 0) sclk = 200;
		//if (mclk == 0) mclk = 200;

		return true;
	}
	return false;
}

bool radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint16_t dac_info;
	uint8_t rev, bg, dac;

	/* check CRT table */
	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
	if (dac_info) {
		rev = radeon_bios8(dev_priv, dac_info) & 0x3;
		if (rev < 2) {
			bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0x2) >> 4) & 0xf;
			encoder->ps2_pdac_adj = (bg << 8) | (dac);

			return true;
		} else {
			bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
			encoder->ps2_pdac_adj = (bg << 8) | (dac);

			return true;
		}

	}

	return false;
}

bool radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint16_t dac_info;
	uint8_t rev, bg, dac;

	/* first check TV table */
	dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
	if (dac_info) {
		rev = radeon_bios8(dev_priv, dac_info + 0x3);
		if (rev > 4) {
			bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
			encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);

			bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0xf) & 0xf;
			encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);

			bg = radeon_bios8(dev_priv, dac_info + 0x10) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0x11) & 0xf;
			encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);

			return true;
		} else if (rev > 1) {
			bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0xc) >> 4) & 0xf;
			encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);

			bg = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0xd) >> 4) & 0xf;
			encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);

			bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0xe) >> 4) & 0xf;
			encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);

			return true;
		}
	}

	/* then check CRT table */
	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
	if (dac_info) {
		rev = radeon_bios8(dev_priv, dac_info) & 0x3;
		if (rev < 2) {
			bg = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
			dac = (radeon_bios8(dev_priv, dac_info + 0x3) >> 4) & 0xf;
			encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
			encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
			encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;

			return true;
		} else {
			bg = radeon_bios8(dev_priv, dac_info + 0x4) & 0xf;
			dac = radeon_bios8(dev_priv, dac_info + 0x5) & 0xf;
			encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
			encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
			encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;

			return true;
		}

	}

	return false;
}

bool radeon_combios_get_tv_info(struct radeon_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint16_t tv_info;

	tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
	if (tv_info) {
		if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
			switch (radeon_bios8(dev_priv, tv_info + 7) & 0xf) {
			case 1:
				encoder->tv_std = TV_STD_NTSC;
				DRM_INFO("Default TV standard: NTSC\n");
				break;
			case 2:
				encoder->tv_std = TV_STD_PAL;
				DRM_INFO("Default TV standard: PAL\n");
				break;
			case 3:
				encoder->tv_std = TV_STD_PAL_M;
				DRM_INFO("Default TV standard: PAL-M\n");
				break;
			case 4:
				encoder->tv_std = TV_STD_PAL_60;
				DRM_INFO("Default TV standard: PAL-60\n");
				break;
			case 5:
				encoder->tv_std = TV_STD_NTSC_J;
				DRM_INFO("Default TV standard: NTSC-J\n");
				break;
			case 6:
				encoder->tv_std = TV_STD_SCART_PAL;
				DRM_INFO("Default TV standard: SCART-PAL\n");
				break;
			default:
				encoder->tv_std = TV_STD_NTSC;
				DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
				break;
			}

			switch ((radeon_bios8(dev_priv, tv_info + 9) >> 2) & 0x3) {
			case 0:
				DRM_INFO("29.498928713 MHz TV ref clk\n");
				break;
			case 1:
				DRM_INFO("28.636360000 MHz TV ref clk\n");
				break;
			case 2:
				DRM_INFO("14.318180000 MHz TV ref clk\n");
				break;
			case 3:
				DRM_INFO("27.000000000 MHz TV ref clk\n");
				break;
			default:
				break;
			}
			return true;
		}
	}
	return false;
}

bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint16_t lcd_info;
	uint32_t panel_setup;
	char stmp[30];
	int tmp, i;

	lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);

	if (lcd_info) {
		for (i = 0; i < 24; i++)
			stmp[i] = radeon_bios8(dev_priv, lcd_info + i + 1);
		stmp[24] = 0;

		DRM_INFO("Panel ID String: %s\n", stmp);

		encoder->panel_xres = radeon_bios16(dev_priv, lcd_info + 25);
		encoder->panel_yres = radeon_bios16(dev_priv, lcd_info + 27);

		DRM_INFO("Panel Size %dx%d\n", encoder->panel_xres, encoder->panel_yres);

		encoder->panel_vcc_delay = radeon_bios16(dev_priv, lcd_info + 44);
		if (encoder->panel_vcc_delay > 2000 || encoder->panel_vcc_delay < 0)
			encoder->panel_vcc_delay = 2000;

		encoder->panel_pwr_delay = radeon_bios16(dev_priv, lcd_info + 0x24);
		encoder->panel_digon_delay = radeon_bios16(dev_priv, lcd_info + 0x38) & 0xf;
		encoder->panel_blon_delay = (radeon_bios16(dev_priv, lcd_info + 0x38) >> 4) & 0xf;

		encoder->panel_ref_divider = radeon_bios16(dev_priv, lcd_info + 46);
		encoder->panel_post_divider = radeon_bios8(dev_priv, lcd_info + 48);
		encoder->panel_fb_divider = radeon_bios16(dev_priv, lcd_info + 49);
		if ((encoder->panel_ref_divider != 0) &&
		    (encoder->panel_fb_divider > 3))
			encoder->use_bios_dividers = true;

		panel_setup = radeon_bios32(dev_priv, lcd_info + 0x39);
		encoder->lvds_gen_cntl = 0xff00;
		if (panel_setup & 0x1)
			encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;

		if ((panel_setup >> 4) & 0x1)
			encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;

		switch ((panel_setup >> 8) & 0x7) {
		case 0:
			encoder->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
			break;
		case 1:
			encoder->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
			break;
		case 2:
			encoder->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
			break;
		default:
			break;
		}

		if ((panel_setup >> 16) & 0x1)
			encoder->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;

		if ((panel_setup >> 17) & 0x1)
			encoder->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;

		if ((panel_setup >> 18) & 0x1)
			encoder->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;

		if ((panel_setup >> 23) & 0x1)
			encoder->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;

		encoder->lvds_gen_cntl |= (panel_setup & 0xf0000000);


		for (i = 0; i < 32; i++) {
			tmp = radeon_bios16(dev_priv, lcd_info + 64 + i * 2);
			if (tmp == 0) break;

			if ((radeon_bios16(dev_priv, tmp) == encoder->panel_xres) &&
			    (radeon_bios16(dev_priv, tmp + 2) == encoder->panel_yres)) {
				encoder->hblank = (radeon_bios16(dev_priv, tmp + 17) -
						   radeon_bios16(dev_priv, tmp + 19)) * 8;
				encoder->hoverplus = (radeon_bios16(dev_priv, tmp + 21) -
						      radeon_bios16(dev_priv, tmp + 19) - 1) * 8;
				encoder->hsync_width = radeon_bios8(dev_priv, tmp + 23) * 8;

				encoder->vblank = (radeon_bios16(dev_priv, tmp + 24) -
						   radeon_bios16(dev_priv, tmp + 26));
				encoder->voverplus = ((radeon_bios16(dev_priv, tmp + 28) & 0x7fff) -
						      radeon_bios16(dev_priv, tmp + 26));
				encoder->vsync_width = ((radeon_bios16(dev_priv, tmp + 28) & 0xf800) >> 11);
				encoder->dotclock = radeon_bios16(dev_priv, tmp + 9) * 10;
				encoder->flags = 0;
			}
		}
		return true;
	}
	DRM_INFO("No panel info found in BIOS\n");
	return false;

}

bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint16_t tmds_info;
	int i, n;
	uint8_t ver;

	tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);

	if (tmds_info) {
		ver = radeon_bios8(dev_priv, tmds_info);
		DRM_INFO("DFP table revision: %d\n", ver);
		if (ver == 3) {
			n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
			if (n > 4)
				n = 4;
			for (i = 0; i < n; i++) {
				encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + i * 10 + 0x08);
				encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + i * 10 + 0x10);
			}
			return true;
		} else if (ver == 4) {
			int stride = 0;
			n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
			if (n > 4)
				n = 4;
			for (i = 0; i < n; i++) {
				encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + stride + 0x08);
				encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + stride + 0x10);
				if (i == 0)
					stride += 10;
				else
					stride += 6;
			}
			return true;
		}
	}

	DRM_INFO("No TMDS info found in BIOS\n");
	return false;
}

bool radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint16_t ext_tmds_info;
	uint8_t ver;

	ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
	if (ext_tmds_info) {
		ver = radeon_bios8(dev_priv, ext_tmds_info);
		DRM_INFO("External TMDS Table revision: %d\n", ver);
		// TODO
	}
}

static void radeon_apply_legacy_quirks(struct drm_device *dev, int bios_index)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct radeon_mode_info *mode_info = &dev_priv->mode_info;

	/* XPRESS DDC quirks */
	if ((dev_priv->chip_family == CHIP_RS400 ||
	     dev_priv->chip_family == CHIP_RS480) &&
	    mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
		mode_info->bios_connector[bios_index].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
	} else if ((dev_priv->chip_family == CHIP_RS400 ||
		    dev_priv->chip_family == CHIP_RS480) &&
		   mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) {
		mode_info->bios_connector[bios_index].ddc_i2c.valid = true;
		mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_mask = (0x20 << 8);
		mode_info->bios_connector[bios_index].ddc_i2c.mask_data_mask = 0x80;
		mode_info->bios_connector[bios_index].ddc_i2c.a_clk_mask = (0x20 << 8);
		mode_info->bios_connector[bios_index].ddc_i2c.a_data_mask = 0x80;
		mode_info->bios_connector[bios_index].ddc_i2c.put_clk_mask = (0x20 << 8);
		mode_info->bios_connector[bios_index].ddc_i2c.put_data_mask = 0x80;
		mode_info->bios_connector[bios_index].ddc_i2c.get_clk_mask = (0x20 << 8);
		mode_info->bios_connector[bios_index].ddc_i2c.get_data_mask = 0x80;
		mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
		mode_info->bios_connector[bios_index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
		mode_info->bios_connector[bios_index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A;
		mode_info->bios_connector[bios_index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A;
		mode_info->bios_connector[bios_index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN;
		mode_info->bios_connector[bios_index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN;
		mode_info->bios_connector[bios_index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG;
		mode_info->bios_connector[bios_index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG;
	}

	/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
	   one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
	if (dev->pdev->device == 0x515e &&
	    dev->pdev->subsystem_vendor == 0x1014) {
		if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_VGA &&
		    mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
			mode_info->bios_connector[bios_index].valid = false;
		}
	}

	/* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
	if (dev->pdev->device == 0x5159 &&
	    dev->pdev->subsystem_vendor == 0x1002 &&
	    dev->pdev->subsystem_device == 0x013a) {
		if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
			mode_info->bios_connector[bios_index].connector_type = CONNECTOR_VGA;

	}

	/* X300 card with extra non-existent DVI port */
	if (dev->pdev->device == 0x5B60 &&
	    dev->pdev->subsystem_vendor == 0x17af &&
	    dev->pdev->subsystem_device == 0x201e &&
	    bios_index == 2) {
		if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
			mode_info->bios_connector[bios_index].valid = false;
	}

}

bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct radeon_mode_info *mode_info = &dev_priv->mode_info;
	uint32_t conn_info, entry;
	uint16_t tmp;
	enum radeon_combios_ddc ddc_type;
	enum radeon_combios_connector connector_type;
	int i;

	DRM_DEBUG("\n");
	conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
	if (conn_info) {
		for (i = 0; i < 4; i++) {
			entry = conn_info + 2 + i * 2;

			if (!radeon_bios16(dev_priv, entry))
				    break;

			mode_info->bios_connector[i].valid = true;

			tmp = radeon_bios16(dev_priv, entry);

			connector_type = (tmp >> 12) & 0xf;
			mode_info->bios_connector[i].connector_type = connector_type;

			switch(connector_type) {
			case CONNECTOR_PROPRIETARY_LEGACY:
				mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
				break;
			case CONNECTOR_CRT_LEGACY:
				mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
				break;
			case CONNECTOR_DVI_I_LEGACY:
				mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_I;
				break;
			case CONNECTOR_DVI_D_LEGACY:
				mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
				break;
			case CONNECTOR_CTV_LEGACY:
				mode_info->bios_connector[i].connector_type = CONNECTOR_CTV;
				break;
			case CONNECTOR_STV_LEGACY:
				mode_info->bios_connector[i].connector_type = CONNECTOR_STV;
				break;
			default:
				DRM_ERROR("Unknown connector type: %d\n", connector_type);
				mode_info->bios_connector[i].valid = false;
				break;
			}

			mode_info->bios_connector[i].ddc_i2c.valid = false;

			ddc_type = (tmp >> 8) & 0xf;
			switch (ddc_type) {
			case DDC_MONID:
				mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
				break;
			case DDC_DVI:
				mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
				break;
			case DDC_VGA:
				mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
				break;
			case DDC_CRT2:
				mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
				break;
			default:
				break;
			}

			if (tmp & 0x1)
				mode_info->bios_connector[i].dac_type = DAC_TVDAC;
			else
				mode_info->bios_connector[i].dac_type = DAC_PRIMARY;

			if ((dev_priv->chip_family == CHIP_RS300) ||
			    (dev_priv->chip_family == CHIP_RS400) ||
			    (dev_priv->chip_family == CHIP_RS480))
				mode_info->bios_connector[i].dac_type = DAC_TVDAC;

			if ((tmp >> 4) & 0x1)
				mode_info->bios_connector[i].tmds_type = TMDS_EXT;
			else
				mode_info->bios_connector[i].tmds_type = TMDS_INT;

			radeon_apply_legacy_quirks(dev, i);
		}
	} else {
		uint16_t tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		if (tmds_info) {
			DRM_DEBUG("Found DFP table, assuming DVI connector\n");

			mode_info->bios_connector[0].valid = true;
			mode_info->bios_connector[0].connector_type = CONNECTOR_DVI_I;
			mode_info->bios_connector[0].dac_type = DAC_PRIMARY;
			mode_info->bios_connector[0].tmds_type = TMDS_INT;
			mode_info->bios_connector[0].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		} else {
			DRM_DEBUG("No connector info found\n");
			return false;
		}
	}

	if (dev_priv->flags & RADEON_IS_MOBILITY ||
	    dev_priv->chip_family == CHIP_RS400 ||
	    dev_priv->chip_family == CHIP_RS480) {
		uint16_t lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		if (lcd_info) {
			uint16_t lcd_ddc_info = combios_get_table_offset(dev, COMBIOS_LCD_DDC_INFO_TABLE);

			mode_info->bios_connector[4].valid = true;
			mode_info->bios_connector[4].connector_type = CONNECTOR_LVDS;
			mode_info->bios_connector[4].dac_type = DAC_NONE;
			mode_info->bios_connector[4].tmds_type = TMDS_NONE;
			mode_info->bios_connector[4].ddc_i2c.valid = false;

			if (lcd_ddc_info) {
				ddc_type = radeon_bios8(dev_priv, lcd_ddc_info + 2);
				switch(ddc_type) {
				case DDC_MONID:
					mode_info->bios_connector[4].ddc_i2c =
						combios_setup_i2c_bus(RADEON_GPIO_MONID);
					break;
				case DDC_DVI:
					mode_info->bios_connector[4].ddc_i2c =
						combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
					break;
				case DDC_VGA:
					mode_info->bios_connector[4].ddc_i2c =
						combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
					break;
				case DDC_CRT2:
					mode_info->bios_connector[4].ddc_i2c =
						combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
					break;
				case DDC_LCD:
					mode_info->bios_connector[4].ddc_i2c =
						combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
					mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 3);
					mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 7);
					mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 3);
					mode_info->bios_connector[4].ddc_i2c.a_data_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 7);
					mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 3);
					mode_info->bios_connector[4].ddc_i2c.put_data_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 7);
					mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 3);
					mode_info->bios_connector[4].ddc_i2c.get_data_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 7);
					break;
				case DDC_GPIO:
					mode_info->bios_connector[4].ddc_i2c =
						combios_setup_i2c_bus(RADEON_MDGPIO_EN_REG);
					mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 3);
					mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 7);
					mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 3);
					mode_info->bios_connector[4].ddc_i2c.a_data_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 7);
					mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 3);
					mode_info->bios_connector[4].ddc_i2c.put_data_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 7);
					mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 3);
					mode_info->bios_connector[4].ddc_i2c.get_data_mask =
						radeon_bios32(dev_priv, lcd_ddc_info + 7);
					break;
				default:
					break;
				}
				DRM_DEBUG("LCD DDC Info Table found!\n");
			}
		} else
			mode_info->bios_connector[4].ddc_i2c.valid = false;
	}

	/* check TV table */
	if (dev_priv->chip_family != CHIP_R100 &&
	    dev_priv->chip_family != CHIP_R200) {
		uint32_t tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		if (tv_info) {
			if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
				mode_info->bios_connector[5].valid = true;
				mode_info->bios_connector[5].connector_type = CONNECTOR_DIN;
				mode_info->bios_connector[5].dac_type = DAC_TVDAC;
				mode_info->bios_connector[5].tmds_type = TMDS_NONE;
				mode_info->bios_connector[5].ddc_i2c.valid = false;
			}
		}
	}


	DRM_DEBUG("BIOS Connector table\n");
	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		if (!mode_info->bios_connector[i].valid)
			continue;

		DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
			  i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
			  mode_info->bios_connector[i].dac_type,
			  mode_info->bios_connector[i].tmds_type,
			  mode_info->bios_connector[i].connector_type,
			  mode_info->bios_connector[i].hpd_mask);
	}

	return true;
}

static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;

	if (offset) {
		while (radeon_bios16(dev_priv, offset)) {
			uint16_t cmd  = ((radeon_bios16(dev_priv, offset) & 0xe000) >> 13);
			uint32_t addr = (radeon_bios16(dev_priv, offset) & 0x1fff);
			uint32_t val, and_mask, or_mask;
			uint32_t tmp;

			offset += 2;
			switch (cmd) {
			case 0:
				val = radeon_bios32(dev_priv, offset);
				offset += 4;
				RADEON_WRITE(addr, val);
				break;
			case 1:
				val = radeon_bios32(dev_priv, offset);
				offset += 4;
				RADEON_WRITE(addr, val);
				break;
			case 2:
				and_mask = radeon_bios32(dev_priv, offset);
				offset += 4;
				or_mask = radeon_bios32(dev_priv, offset);
				offset += 4;
				tmp = RADEON_READ(addr);
				tmp &= and_mask;
				tmp |= or_mask;
				RADEON_WRITE(addr, tmp);
				break;
			case 3:
				and_mask = radeon_bios32(dev_priv, offset);
				offset += 4;
				or_mask = radeon_bios32(dev_priv, offset);
				offset += 4;
				tmp = RADEON_READ(addr);
				tmp &= and_mask;
				tmp |= or_mask;
				RADEON_WRITE(addr, tmp);
				break;
			case 4:
				val = radeon_bios16(dev_priv, offset);
				offset += 2;
				udelay(val);
				break;
			case 5:
				val = radeon_bios16(dev_priv, offset);
				offset += 2;
				switch (addr) {
				case 8:
					while (val--) {
						if (!(RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
						      RADEON_MC_BUSY))
							break;
					}
					break;
				case 9:
					while (val--) {
						if ((RADEON_READ(RADEON_MC_STATUS) &
						      RADEON_MC_IDLE))
							break;
					}
					break;
				default:
					break;
				}
				break;
			default:
				break;
			}
		}
	}
}

static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;

	if (offset) {
		while (radeon_bios8(dev_priv, offset)) {
			uint8_t cmd  = ((radeon_bios8(dev_priv, offset) & 0xc0) >> 6);
			uint8_t addr = (radeon_bios8(dev_priv, offset) & 0x3f);
			uint32_t val, shift, tmp;
			uint32_t and_mask, or_mask;

			offset++;
			switch (cmd) {
			case 0:
				val = radeon_bios32(dev_priv, offset);
				offset += 4;
				RADEON_WRITE_PLL(dev_priv, addr, val);
				break;
			case 1:
				shift = radeon_bios8(dev_priv, offset) * 8;
				offset++;
				and_mask = radeon_bios8(dev_priv, offset) << shift;
				and_mask |= ~(0xff << shift);
				offset++;
				or_mask = radeon_bios8(dev_priv, offset) << shift;
				offset++;
				tmp = RADEON_READ_PLL(dev_priv, addr);
				tmp &= and_mask;
				tmp |= or_mask;
				RADEON_WRITE_PLL(dev_priv, addr, tmp);
				break;
			case 2:
			case 3:
				tmp = 1000;
				switch (addr) {
				case 1:
					udelay(150);
					break;
				case 2:
					udelay(1000);
					break;
				case 3:
					while (tmp--) {
						if (!(RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
						      RADEON_MC_BUSY))
							break;
					}
					break;
				case 4:
					while (tmp--) {
						if (RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
						    RADEON_DLL_READY)
							break;
					}
					break;
				case 5:
					tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL);
					if (tmp & RADEON_CG_NO1_DEBUG_0) {
#if 0
						uint32_t mclk_cntl = RADEON_READ_PLL(RADEON_MCLK_CNTL);
						mclk_cntl &= 0xffff0000;
						//mclk_cntl |= 0x00001111; /* ??? */
						RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, mclk_cntl);
						udelay(10000);
#endif
						RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL,
								 tmp & ~RADEON_CG_NO1_DEBUG_0);
						udelay(10000);
					}
					break;
				default:
					break;
				}
				break;
			default:
				break;
			}
		}
	}
}

static void combios_parse_ram_reset_table(struct drm_device *dev, uint16_t offset)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	if (offset) {
		uint8_t val = radeon_bios8(dev_priv, offset);
		while (val != 0xff) {
			offset++;

			if (val == 0x0f) {
				uint32_t channel_complete_mask;

				if (radeon_is_r300(dev_priv))
					channel_complete_mask = R300_MEM_PWRUP_COMPLETE;
				else
					channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE;
				tmp = 20000;
				while (tmp--) {
					if ((RADEON_READ(RADEON_MEM_STR_CNTL) &
					     channel_complete_mask) ==
					    channel_complete_mask)
						break;
				}
			} else {
				uint32_t or_mask = radeon_bios16(dev_priv, offset);
				offset += 2;

				tmp = RADEON_READ(RADEON_MEM_SDRAM_MODE_REG);
				tmp &= RADEON_SDRAM_MODE_MASK;
				tmp |= or_mask;
				RADEON_WRITE(RADEON_MEM_SDRAM_MODE_REG, tmp);

				or_mask = val << 24;
				tmp = RADEON_READ(RADEON_MEM_SDRAM_MODE_REG);
				tmp &= RADEON_B3MEM_RESET_MASK;
				tmp |= or_mask;
				RADEON_WRITE(RADEON_MEM_SDRAM_MODE_REG, tmp);
			}
			val = radeon_bios8(dev_priv, offset);
		}
	}
}

void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
{
	uint16_t dyn_clk_info = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);

	if (dyn_clk_info)
		combios_parse_pll_table(dev, dyn_clk_info);
}