/* $Id$ * ffb_context.c: Creator/Creator3D DRI/DRM context switching. * * Copyright (C) 2000 David S. Miller (davem@redhat.com) * * Almost entirely stolen from tdfx_context.c, see there * for authors. */ #include #include #include "ffb.h" #include "drmP.h" #include "ffb_drv.h" static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int i; for (i = 0; i < FFB_MAX_CTXS; i++) { if (fpriv->hw_state[i] == NULL) break; } if (i == FFB_MAX_CTXS) return -1; fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL); if (fpriv->hw_state[i] == NULL) return -1; fpriv->hw_state[i]->is_2d_only = is_2d_only; /* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */ return i + 1; } static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) { ffb_fbcPtr ffb = fpriv->regs; struct ffb_hw_context *ctx; int i; ctx = fpriv->hw_state[idx - 1]; if (idx == 0 || ctx == NULL) return; if (ctx->is_2d_only) { /* 2D applications only care about certain pieces * of state. */ ctx->drawop = upa_readl(&ffb->drawop); ctx->ppc = upa_readl(&ffb->ppc); ctx->wid = upa_readl(&ffb->wid); ctx->fg = upa_readl(&ffb->fg); ctx->bg = upa_readl(&ffb->bg); ctx->xclip = upa_readl(&ffb->xclip); ctx->fbc = upa_readl(&ffb->fbc); ctx->rop = upa_readl(&ffb->rop); ctx->cmp = upa_readl(&ffb->cmp); ctx->matchab = upa_readl(&ffb->matchab); ctx->magnab = upa_readl(&ffb->magnab); ctx->pmask = upa_readl(&ffb->pmask); ctx->xpmask = upa_readl(&ffb->xpmask); ctx->lpat = upa_readl(&ffb->lpat); ctx->fontxy = upa_readl(&ffb->fontxy); ctx->fontw = upa_readl(&ffb->fontw); ctx->fontinc = upa_readl(&ffb->fontinc); /* stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. */ if (fpriv->ffb_type == ffb2_vertical_plus || fpriv->ffb_type == ffb2_horizontal_plus) { ctx->stencil = upa_readl(&ffb->stencil); ctx->stencilctl = upa_readl(&ffb->stencilctl); } for (i = 0; i < 32; i++) ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]); ctx->ucsr = upa_readl(&ffb->ucsr); return; } /* Fetch drawop. */ ctx->drawop = upa_readl(&ffb->drawop); /* If we were saving the vertex registers, this is where * we would do it. We would save 32 32-bit words starting * at ffb->suvtx. */ /* Capture rendering attributes. */ ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ ctx->wid = upa_readl(&ffb->wid); /* Current WID */ ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */ ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */ ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */ ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */ ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */ ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */ ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */ ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ /* Auxiliary Clips. */ ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min); ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max); ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min); ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max); ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min); ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max); ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min); ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max); ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */ /* These registers/features only exist on FFB2 and later chips. */ if (fpriv->ffb_type >= ffb2_prototype) { ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */ ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */ ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */ ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ /* And stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. */ if (fpriv->ffb_type == ffb2_vertical_plus || fpriv->ffb_type == ffb2_horizontal_plus) { ctx->stencil = upa_readl(&ffb->stencil); ctx->stencilctl = upa_readl(&ffb->stencilctl); } } /* Save the 32x32 area pattern. */ for (i = 0; i < 32; i++) ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]); /* Finally, stash away the User Constol/Status Register. */ ctx->ucsr = upa_readl(&ffb->ucsr); } static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) { ffb_fbcPtr ffb = fpriv->regs; struct ffb_hw_context *ctx; int i; ctx = fpriv->hw_state[idx - 1]; if (idx == 0 || ctx == NULL) return; if (ctx->is_2d_only) { /* 2D applications only care about certain pieces * of state. */ upa_writel(ctx->drawop, &ffb->drawop); /* If we were restoring the vertex registers, this is where * we would do it. We would restore 32 32-bit words starting * at ffb->suvtx. */ upa_writel(ctx->ppc, &ffb->ppc); upa_writel(ctx->wid, &ffb->wid); upa_writel(ctx->fg, &ffb->fg); upa_writel(ctx->bg, &ffb->bg); upa_writel(ctx->xclip, &ffb->xclip); upa_writel(ctx->fbc, &ffb->fbc); upa_writel(ctx->rop, &ffb->rop); upa_writel(ctx->cmp, &ffb->cmp); upa_writel(ctx->matchab, &ffb->matchab); upa_writel(ctx->magnab, &ffb->magnab); upa_writel(ctx->pmask, &ffb->pmask); upa_writel(ctx->xpmask, &ffb->xpmask); upa_writel(ctx->lpat, &ffb->lpat); upa_writel(ctx->fontxy, &ffb->fontxy); upa_writel(ctx->fontw, &ffb->fontw); upa_writel(ctx->fontinc, &ffb->fontinc); /* stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. */ if (fpriv->ffb_type == ffb2_vertical_plus || fpriv->ffb_type == ffb2_horizontal_plus) { upa_writel(ctx->stencil, &ffb->stencil); upa_writel(ctx->stencilctl, &ffb->stencilctl); upa_writel(0x80000000, &ffb->fbc); upa_writel((ctx->stencilctl | 0x80000), &ffb->rawstencilctl); upa_writel(ctx->fbc, &ffb->fbc); } for (i = 0; i < 32; i++) upa_writel(ctx->area_pattern[i], &ffb->pattern[i]); upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr); return; } /* Restore drawop. */ upa_writel(ctx->drawop, &ffb->drawop); /* If we were restoring the vertex registers, this is where * we would do it. We would restore 32 32-bit words starting * at ffb->suvtx. */ /* Restore rendering attributes. */ upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ upa_writel(ctx->wid, &ffb->wid); /* Current WID */ upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */ upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */ upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */ upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */ upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */ upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */ upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */ upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ /* Auxiliary Clips. */ upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min); upa_writel(ctx->auxclip0max, &ffb->auxclip[0].max); upa_writel(ctx->auxclip1min, &ffb->auxclip[1].min); upa_writel(ctx->auxclip1max, &ffb->auxclip[1].max); upa_writel(ctx->auxclip2min, &ffb->auxclip[2].min); upa_writel(ctx->auxclip2max, &ffb->auxclip[2].max); upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min); upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max); upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */ /* These registers/features only exist on FFB2 and later chips. */ if (fpriv->ffb_type >= ffb2_prototype) { upa_writel(ctx->dcss1, &ffb->dcss1); /* Depth Cue Scale Slope 1 */ upa_writel(ctx->dcss2, &ffb->dcss2); /* Depth Cue Scale Slope 2 */ upa_writel(ctx->dcss3, &ffb->dcss2); /* Depth Cue Scale Slope 3 */ upa_writel(ctx->dcs2, &ffb->dcs2); /* Depth Cue Scale 2 */ upa_writel(ctx->dcs3, &ffb->dcs3); /* Depth Cue Scale 3 */ upa_writel(ctx->dcs4, &ffb->dcs4); /* Depth Cue Scale 4 */ upa_writel(ctx->dcd2, &ffb->dcd2); /* Depth Cue Depth 2 */ upa_writel(ctx->dcd3, &ffb->dcd3); /* Depth Cue Depth 3 */ upa_writel(ctx->dcd4, &ffb->dcd4); /* Depth Cue Depth 4 */ /* And stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. */ if (fpriv->ffb_type == ffb2_vertical_plus || fpriv->ffb_type == ffb2_horizontal_plus) { /* Unfortunately, there is a hardware bug on * the FFB2+ chips which prevents a normal write * to the stencil control register from working * as it should. * * The state controlled by the FFB stencilctl register * really gets transferred to the per-buffer instances * of the stencilctl register in the 3DRAM chips. * * The bug is that FFB does not update buffer C correctly, * so we have to do it by hand for them. */ /* This will update buffers A and B. */ upa_writel(ctx->stencil, &ffb->stencil); upa_writel(ctx->stencilctl, &ffb->stencilctl); /* Force FFB to use buffer C 3dram regs. */ upa_writel(0x80000000, &ffb->fbc); upa_writel((ctx->stencilctl | 0x80000), &ffb->rawstencilctl); /* Now restore the correct FBC controls. */ upa_writel(ctx->fbc, &ffb->fbc); } } /* Restore the 32x32 area pattern. */ for (i = 0; i < 32; i++) upa_writel(ctx->area_pattern[i], &ffb->pattern[i]); /* Finally, stash away the User Constol/Status Register. * The only state we really preserve here is the picking * control. */ upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr); } #define FFB_UCSR_FB_BUSY 0x01000000 #define FFB_UCSR_RP_BUSY 0x02000000 #define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY) static void FFBWait(ffb_fbcPtr ffb) { int limit = 100000; do { u32 regval = upa_readl(&ffb->ucsr); if ((regval & FFB_UCSR_ALL_BUSY) == 0) break; } while (--limit); } int DRM(context_switch)(drm_device_t *dev, int old, int new) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; #if DRM_DMA_HISTOGRAM dev->ctx_start = get_cycles(); #endif DRM_DEBUG("Context switch from %d to %d\n", old, new); if (new == dev->last_context || dev->last_context == 0) { dev->last_context = new; return 0; } FFBWait(fpriv->regs); ffb_save_context(fpriv, old); ffb_restore_context(fpriv, old, new); FFBWait(fpriv->regs); dev->last_context = new; return 0; } int DRM(resctx)(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_ctx_res_t res; drm_ctx_t ctx; int i; DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); if (copy_from_user(&res, (drm_ctx_res_t __user *)arg, sizeof(res))) return -EFAULT; if (res.count >= DRM_RESERVED_CONTEXTS) { memset(&ctx, 0, sizeof(ctx)); for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { ctx.handle = i; if (copy_to_user(&res.contexts[i], &i, sizeof(i))) return -EFAULT; } } res.count = DRM_RESERVED_CONTEXTS; if (copy_to_user((drm_ctx_res_t __user *)arg, &res, sizeof(res))) return -EFAULT; return 0; } int DRM(addctx)(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_ctx_t ctx; int idx; if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) return -EFAULT; idx = DRM(alloc_queue)(dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); if (idx < 0) return -ENFILE; DRM_DEBUG("%d\n", ctx.handle); ctx.handle = idx; if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) return -EFAULT; return 0; } int DRM(modctx)(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; struct ffb_hw_context *hwctx; drm_ctx_t ctx; int idx; if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) return -EFAULT; idx = ctx.handle; if (idx <= 0 || idx >= FFB_MAX_CTXS) return -EINVAL; hwctx = fpriv->hw_state[idx - 1]; if (hwctx == NULL) return -EINVAL; if ((ctx.flags & _DRM_CONTEXT_2DONLY) == 0) hwctx->is_2d_only = 0; else hwctx->is_2d_only = 1; return 0; } int DRM(getctx)(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; struct ffb_hw_context *hwctx; drm_ctx_t ctx; int idx; if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) return -EFAULT; idx = ctx.handle; if (idx <= 0 || idx >= FFB_MAX_CTXS) return -EINVAL; hwctx = fpriv->hw_state[idx - 1]; if (hwctx == NULL) return -EINVAL; if (hwctx->is_2d_only != 0) ctx.flags = _DRM_CONTEXT_2DONLY; else ctx.flags = 0; if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) return -EFAULT; return 0; } int DRM(switchctx)(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_ctx_t ctx; if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); return DRM(context_switch)(dev, dev->last_context, ctx.handle); } int DRM(newctx)(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_ctx_t ctx; if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); return 0; } int DRM(rmctx)(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_ctx_t ctx; drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int idx; if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); idx = ctx.handle - 1; if (idx < 0 || idx >= FFB_MAX_CTXS) return -EINVAL; if (fpriv->hw_state[idx] != NULL) { kfree(fpriv->hw_state[idx]); fpriv->hw_state[idx] = NULL; } return 0; } static void ffb_driver_release(drm_device_t *dev) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock); int idx; idx = context - 1; if (fpriv && context != DRM_KERNEL_CONTEXT && fpriv->hw_state[idx] != NULL) { kfree(fpriv->hw_state[idx]); fpriv->hw_state[idx] = NULL; } } static int ffb_driver_presetup(drm_device_t *dev) { int ret; ret = ffb_presetup(dev); if (_ret != 0) return ret; } static void ffb_driver_pretakedown(drm_device_t *dev) { if (dev->dev_private) kfree(dev->dev_private); } static void ffb_driver_postcleanup(drm_device_t *dev) { if (ffb_position != NULL) kfree(ffb_position); } static int ffb_driver_kernel_context_switch_unlock(struct drm_device *dev) { dev->lock.filp = 0; { __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock; unsigned int old, new, prev, ctx; ctx = lock.context; do { old = *plock; new = ctx; prev = cmpxchg(plock, old, new); } while (prev != old); } wake_up_interruptible(&dev->lock.lock_queue); } static unsigned long ffb_driver_get_map_ofs(drm_map_t *map) { return (map->offset & 0xffffffff); } static unsigned long ffb_driver_get_reg_ofs(drm_device_t *dev) { ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; if (ffb_priv) return ffb_priv->card_phys_base; return 0; } static void ffb_driver_register_fns(drm_device_t *dev) { DRM(fops).get_unmapped_area = ffb_get_unmapped_area; dev->fn_tbl.release = ffb_driver_release; dev->fn_tbl.presetup = ffb_driver_presetup; dev->fn_tbl.pretakedown = ffb_driver_pretakedown; dev->fn_tbl.postcleanup = ffb_driver_postcleanup; dev->fn_tbl.kernel_context_switch = ffb_context_switch; dev->fn_tbl.kernel_context_switch_unlock = ffb_driver_kernel_context_switch_unlock; dev->fn_tbl.get_map_ofs = ffb_driver_get_map_ofs; dev->fn_tbl.get_reg_ofs = ffb_driver_get_reg_ofs; } 'n494' href='#n494'>494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 
/*
 * Copyright 2007 Nouveau Project
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
#include <stdint.h>
#include <stdlib.h>
#include <errno.h>
#include <assert.h>

#include <sys/mman.h>

#include "nouveau_private.h"

int
nouveau_bo_init(struct nouveau_device *dev)
{
	return 0;
}

void
nouveau_bo_takedown(struct nouveau_device *dev)
{
}

static int
nouveau_bo_info(struct nouveau_bo_priv *nvbo, struct drm_nouveau_gem_info *arg)
{
	nvbo->handle = nvbo->base.handle = arg->handle;
	nvbo->domain = arg->domain;
	nvbo->size = arg->size;
	nvbo->offset = arg->offset;
	nvbo->map_handle = arg->map_handle;
	nvbo->base.tile_mode = arg->tile_mode;
	/* XXX - flag inverted for backwards compatibility */
	nvbo->base.tile_flags = arg->tile_flags ^ NOUVEAU_GEM_TILE_NONCONTIG;
	return 0;
}

static int
nouveau_bo_allocated(struct nouveau_bo_priv *nvbo)
{
	if (nvbo->sysmem || nvbo->handle)
		return 1;
	return 0;
}

static int
nouveau_bo_ualloc(struct nouveau_bo_priv *nvbo)
{
	if (nvbo->user || nvbo->sysmem) {
		assert(nvbo->sysmem);
		return 0;
	}

	nvbo->sysmem = malloc(nvbo->size);
	if (!nvbo->sysmem)
		return -ENOMEM;

	return 0;
}

static void
nouveau_bo_ufree(struct nouveau_bo_priv *nvbo)
{
	if (nvbo->sysmem) {
		if (!nvbo->user)
			free(nvbo->sysmem);
		nvbo->sysmem = NULL;
	}
}

static void
nouveau_bo_kfree(struct nouveau_bo_priv *nvbo)
{
	struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);
	struct drm_gem_close req;

	if (!nvbo->handle)
		return;

	if (nvbo->map) {
		munmap(nvbo->map, nvbo->size);
		nvbo->map = NULL;
	}

	req.handle = nvbo->handle;
	nvbo->handle = 0;
	drmIoctl(nvdev->fd, DRM_IOCTL_GEM_CLOSE, &req);
}

static int
nouveau_bo_kalloc(struct nouveau_bo_priv *nvbo, struct nouveau_channel *chan)
{
	struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);
	struct drm_nouveau_gem_new req;
	struct drm_nouveau_gem_info *info = &req.info;
	int ret;

	if (nvbo->handle)
		return 0;

	req.channel_hint = chan ? chan->id : 0;
	req.align = nvbo->align;


	info->size = nvbo->size;
	info->domain = 0;

	if (nvbo->flags & NOUVEAU_BO_VRAM)
		info->domain |= NOUVEAU_GEM_DOMAIN_VRAM;
	if (nvbo->flags & NOUVEAU_BO_GART)
		info->domain |= NOUVEAU_GEM_DOMAIN_GART;
	if (!info->domain) {
		info->domain |= (NOUVEAU_GEM_DOMAIN_VRAM |
				 NOUVEAU_GEM_DOMAIN_GART);
	}

	if (nvbo->flags & NOUVEAU_BO_MAP)
		info->domain |= NOUVEAU_GEM_DOMAIN_MAPPABLE;

	info->tile_mode = nvbo->base.tile_mode;
	info->tile_flags = nvbo->base.tile_flags;
	/* XXX - flag inverted for backwards compatibility */
	info->tile_flags ^= NOUVEAU_GEM_TILE_NONCONTIG;
	if (!nvdev->has_bo_usage)
		info->tile_flags &= NOUVEAU_GEM_TILE_LAYOUT_MASK;

	ret = drmCommandWriteRead(nvdev->fd, DRM_NOUVEAU_GEM_NEW,
				  &req, sizeof(req));
	if (ret)
		return ret;

	nouveau_bo_info(nvbo, &req.info);
	return 0;
}

static int
nouveau_bo_kmap(struct nouveau_bo_priv *nvbo)
{
	struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);

	if (nvbo->map)
		return 0;

	if (!nvbo->map_handle)
		return -EINVAL;

	nvbo->map = mmap(0, nvbo->size, PROT_READ | PROT_WRITE,
			 MAP_SHARED, nvdev->fd, nvbo->map_handle);
	if (nvbo->map == MAP_FAILED) {
		nvbo->map = NULL;
		return -errno;
	}

	return 0;
}

int
nouveau_bo_new_tile(struct nouveau_device *dev, uint32_t flags, int align,
		    int size, uint32_t tile_mode, uint32_t tile_flags,
		    struct nouveau_bo **bo)
{
	struct nouveau_bo_priv *nvbo;
	int ret;

	if (!dev || !bo || *bo)
		return -EINVAL;

	nvbo = calloc(1, sizeof(struct nouveau_bo_priv));
	if (!nvbo)
		return -ENOMEM;
	nvbo->base.device = dev;
	nvbo->base.size = size;
	nvbo->base.tile_mode = tile_mode;
	nvbo->base.tile_flags = tile_flags;

	nvbo->refcount = 1;
	nvbo->flags = flags;
	nvbo->size = size;
	nvbo->align = align;

	if (flags & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART)) {
		ret = nouveau_bo_kalloc(nvbo, NULL);
		if (ret) {
			nouveau_bo_ref(NULL, (void *)&nvbo);
			return ret;
		}
	}

	*bo = &nvbo->base;
	return 0;
}

int
nouveau_bo_new(struct nouveau_device *dev, uint32_t flags, int align,
	       int size, struct nouveau_bo **bo)
{
	return nouveau_bo_new_tile(dev, flags, align, size, 0, 0, bo);
}

int
nouveau_bo_user(struct nouveau_device *dev, void *ptr, int size,
		struct nouveau_bo **bo)
{
	struct nouveau_bo_priv *nvbo;
	int ret;

	ret = nouveau_bo_new(dev, NOUVEAU_BO_MAP, 0, size, bo);
	if (ret)
		return ret;
	nvbo = nouveau_bo(*bo);

	nvbo->sysmem = ptr;
	nvbo->user = 1;
	return 0;
}

int
nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle,
		struct nouveau_bo **bo)
{
	struct nouveau_device_priv *nvdev = nouveau_device(dev);
	struct drm_nouveau_gem_info req;
	struct nouveau_bo_priv *nvbo;
	int ret;

	ret = nouveau_bo_new(dev, 0, 0, 0, bo);
	if (ret)
		return ret;
	nvbo = nouveau_bo(*bo);

	req.handle = handle;
	ret = drmCommandWriteRead(nvdev->fd, DRM_NOUVEAU_GEM_INFO,
				  &req, sizeof(req));
	if (ret) {
		nouveau_bo_ref(NULL, bo);
		return ret;
	}

	nouveau_bo_info(nvbo, &req);
	nvbo->base.size = nvbo->size;
	return 0;
}

int
nouveau_bo_handle_get(struct nouveau_bo *bo, uint32_t *handle)
{
	struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
	struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
	int ret;
 
	if (!bo || !handle)
		return -EINVAL;

	if (!nvbo->global_handle) {
		struct drm_gem_flink req;
 
		ret = nouveau_bo_kalloc(nvbo, NULL);
		if (ret)
			return ret;

		req.handle = nvbo->handle;
		ret = drmIoctl(nvdev->fd, DRM_IOCTL_GEM_FLINK, &req);
		if (ret) {
			nouveau_bo_kfree(nvbo);
			return ret;
		}

		nvbo->global_handle = req.name;
	}
 
	*handle = nvbo->global_handle;
	return 0;
}
 
int
nouveau_bo_handle_ref(struct nouveau_device *dev, uint32_t handle,
		      struct nouveau_bo **bo)
{
	struct nouveau_device_priv *nvdev = nouveau_device(dev);
	struct nouveau_bo_priv *nvbo;
	struct drm_gem_open req;
	int ret;

	req.name = handle;
	ret = drmIoctl(nvdev->fd, DRM_IOCTL_GEM_OPEN, &req);
	if (ret) {
		nouveau_bo_ref(NULL, bo);
		return ret;
	}

	ret = nouveau_bo_wrap(dev, req.handle, bo);
	if (ret) {
		nouveau_bo_ref(NULL, bo);
		return ret;
	}

	nvbo = nouveau_bo(*bo);
	nvbo->base.handle = nvbo->handle;
	return 0;
} 

static void
nouveau_bo_del(struct nouveau_bo **bo)
{
	struct nouveau_bo_priv *nvbo;

	if (!bo || !*bo)
		return;
	nvbo = nouveau_bo(*bo);
	*bo = NULL;

	if (--nvbo->refcount)
		return;

	if (nvbo->pending) {
		nvbo->pending = NULL;
		nouveau_pushbuf_flush(nvbo->pending_channel, 0);
	}

	nouveau_bo_ufree(nvbo);
	nouveau_bo_kfree(nvbo);
	free(nvbo);
}

int
nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pbo)
{
	if (!pbo)
		return -EINVAL;

	if (ref)
		nouveau_bo(ref)->refcount++;

	if (*pbo)
		nouveau_bo_del(pbo);

	*pbo = ref;
	return 0;
}

static int
nouveau_bo_wait(struct nouveau_bo *bo, int cpu_write, int no_wait, int no_block)
{
	struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
	struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
	struct drm_nouveau_gem_cpu_prep req;
	int ret;

	if (!nvbo->global_handle && !nvbo->write_marker && !cpu_write)
		return 0;

	if (nvbo->pending &&
	    (nvbo->pending->write_domains || cpu_write)) {
		nvbo->pending = NULL;
		nouveau_pushbuf_flush(nvbo->pending_channel, 0);
	}

	req.handle = nvbo->handle;
	req.flags = 0;
	if (cpu_write)
		req.flags |= NOUVEAU_GEM_CPU_PREP_WRITE;
	if (no_wait)
		req.flags |= NOUVEAU_GEM_CPU_PREP_NOWAIT;
	if (no_block)
		req.flags |= NOUVEAU_GEM_CPU_PREP_NOBLOCK;

	do {
		ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_CPU_PREP,
				      &req, sizeof(req));
	} while (ret == -EAGAIN);
	if (ret)
		return ret;

	if (ret == 0)
		nvbo->write_marker = 0;
	return 0;
}

int
nouveau_bo_map_range(struct nouveau_bo *bo, uint32_t delta, uint32_t size,
		     uint32_t flags)
{
	struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
	int ret;

	if (!nvbo || bo->map)
		return -EINVAL;

	if (!nouveau_bo_allocated(nvbo)) {
		if (nvbo->flags & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART)) {
			ret = nouveau_bo_kalloc(nvbo, NULL);
			if (ret)
				return ret;
		}

		if (!nouveau_bo_allocated(nvbo)) {
			ret = nouveau_bo_ualloc(nvbo);
			if (ret)
				return ret;
		}
	}

	if (nvbo->sysmem) {
		bo->map = (char *)nvbo->sysmem + delta;
	} else {
		ret = nouveau_bo_kmap(nvbo);
		if (ret)
			return ret;

		if (!(flags & NOUVEAU_BO_NOSYNC)) {
			ret = nouveau_bo_wait(bo, (flags & NOUVEAU_BO_WR),
					      (flags & NOUVEAU_BO_NOWAIT), 0);
			if (ret)
				return ret;

			nvbo->map_refcnt++;
		}

		bo->map = (char *)nvbo->map + delta;
	}

	return 0;
}

void
nouveau_bo_map_flush(struct nouveau_bo *bo, uint32_t delta, uint32_t size)
{
}

int
nouveau_bo_map(struct nouveau_bo *bo, uint32_t flags)
{
	return nouveau_bo_map_range(bo, 0, bo->size, flags);
}

void
nouveau_bo_unmap(struct nouveau_bo *bo)
{
	struct nouveau_bo_priv *nvbo = nouveau_bo(bo);

	if (bo->map && !nvbo->sysmem && nvbo->map_refcnt) {
		struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
		struct drm_nouveau_gem_cpu_fini req;

		req.handle = nvbo->handle;
		drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_CPU_FINI,
				&req, sizeof(req));
		nvbo->map_refcnt--;
	}

	bo->map = NULL;
}

int
nouveau_bo_busy(struct nouveau_bo *bo, uint32_t access)
{
	return nouveau_bo_wait(bo, (access & NOUVEAU_BO_WR), 1, 1);
}

uint32_t
nouveau_bo_pending(struct nouveau_bo *bo)
{
	struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
	uint32_t flags;

	if (!nvbo->pending)
		return 0;

	flags = 0;
	if (nvbo->pending->read_domains)
		flags |= NOUVEAU_BO_RD;
	if (nvbo->pending->write_domains)
		flags |= NOUVEAU_BO_WR;

	return flags;
}

struct drm_nouveau_gem_pushbuf_bo *
nouveau_bo_emit_buffer(struct nouveau_channel *chan, struct nouveau_bo *bo)
{