/* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro * * Copyright 2005 Thomas Hellstrom. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sub license, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Thomas Hellstrom. * Register info from Digeo Inc. */ #ifndef _VIA_DMABLIT_H #define _VIA_DMABLIT_H #include #define VIA_NUM_BLIT_ENGINES 2 #define VIA_NUM_BLIT_SLOTS 8 struct _drm_via_descriptor; typedef struct _drm_via_sg_info { struct page **pages; unsigned long num_pages; struct _drm_via_descriptor **desc_pages; int num_desc_pages; int num_desc; enum dma_data_direction direction; unsigned char *bounce_buffer; dma_addr_t chain_start; uint32_t free_on_sequence; unsigned int descriptors_per_page; int aborted; enum { dr_via_device_mapped, dr_via_desc_pages_alloc, dr_via_pages_locked, dr_via_pages_alloc, dr_via_sg_init } state; } drm_via_sg_info_t; typedef struct _drm_via_blitq { struct drm_device *dev; uint32_t cur_blit_handle; uint32_t done_blit_handle; unsigned serviced; unsigned head; unsigned cur; unsigned num_free; unsigned num_outstanding; unsigned long end; int aborting; int is_active; drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS]; spinlock_t blit_lock; wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS]; wait_queue_head_t busy_queue; struct work_struct wq; struct timer_list poll_timer; } drm_via_blitq_t; /* * PCI DMA Registers * Channels 2 & 3 don't seem to be implemented in hardware. */ #define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ #define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ #define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ #define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ #define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ #define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ #define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ #define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ #define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ #define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ #define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ #define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ #define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ #define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ #define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ #define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ #define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ #define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ #define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ #define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ #define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ #define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ #define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ #define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ /* Define for DMA engine */ /* DPR */ #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ #define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ #define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */ /* MR */ #define VIA_DMA_MR_CM (1<<0) /* chaining mode */ #define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */ #define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ /* CSR */ #define VIA_DMA_CSR_DE (1<<0) /* DMA enable */ #define VIA_DMA_CSR_TS (1<<1) /* transfer start */ #define VIA_DMA_CSR_TA (1<<2) /* transfer abort */ #define VIA_DMA_CSR_TD (1<<3) /* transfer done */ #define VIA_DMA_CSR_DD (1<<4) /* descriptor done */ #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ #endif 9'>79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 
/**************************************************************************
 *
 * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/
/*
 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
 */

#include "drmP.h"

static void drm_ttm_ipi_handler(void *null)
{
	flush_agp_cache();
}

static void drm_ttm_cache_flush(void)
{
	if (on_each_cpu(drm_ttm_ipi_handler, NULL, 1, 1) != 0)
		DRM_ERROR("Timed out waiting for drm cache flush.\n");
}

/*
 * Use kmalloc if possible. Otherwise fall back to vmalloc.
 */

static void ttm_alloc_pages(drm_ttm_t * ttm)
{
	unsigned long size = ttm->num_pages * sizeof(*ttm->pages);
	ttm->pages = NULL;

	if (drm_alloc_memctl(size))
		return;

	if (size <= PAGE_SIZE) {
		ttm->pages = drm_calloc(1, size, DRM_MEM_TTM);
	}
	if (!ttm->pages) {
		ttm->pages = vmalloc_user(size);
		if (ttm->pages)
			ttm->page_flags |= DRM_TTM_PAGE_VMALLOC;
	}
	if (!ttm->pages) {
		drm_free_memctl(size);
	}
}

static void ttm_free_pages(drm_ttm_t * ttm)
{
	unsigned long size = ttm->num_pages * sizeof(*ttm->pages);

	if (ttm->page_flags & DRM_TTM_PAGE_VMALLOC) {
		vfree(ttm->pages);
		ttm->page_flags &= ~DRM_TTM_PAGE_VMALLOC;
	} else {
		drm_free(ttm->pages, size, DRM_MEM_TTM);
	}
	drm_free_memctl(size);
	ttm->pages = NULL;
}

static struct page *drm_ttm_alloc_page(void)
{
	struct page *page;

	if (drm_alloc_memctl(PAGE_SIZE)) {
		return NULL;
	}
	page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
	if (!page) {
		drm_free_memctl(PAGE_SIZE);
		return NULL;
	}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15))
	SetPageLocked(page);
#else
	SetPageReserved(page);
#endif
	return page;
}

/*
 * Change caching policy for the linear kernel map
 * for range of pages in a ttm.
 */

static int drm_set_caching(drm_ttm_t * ttm, int noncached)
{
	int i;
	struct page **cur_page;
	int do_tlbflush = 0;

	if ((ttm->page_flags & DRM_TTM_PAGE_UNCACHED) == noncached)
		return 0;

	if (noncached)
		drm_ttm_cache_flush();

	for (i = 0; i < ttm->num_pages; ++i) {
		cur_page = ttm->pages + i;
		if (*cur_page) {
			if (!PageHighMem(*cur_page)) {
				if (noncached) {
					map_page_into_agp(*cur_page);
				} else {
					unmap_page_from_agp(*cur_page);
				}
				do_tlbflush = 1;
			}
		}
	}
	if (do_tlbflush)
		flush_agp_mappings();

	DRM_FLAG_MASKED(ttm->page_flags, noncached, DRM_TTM_PAGE_UNCACHED);

	return 0;
}

/*
 * Free all resources associated with a ttm.
 */

int drm_destroy_ttm(drm_ttm_t * ttm)
{

	int i;
	struct page **cur_page;
	drm_ttm_backend_t *be;

	if (!ttm)
		return 0;

	be = ttm->be;
	if (be) {
		be->func->destroy(be);
		ttm->be = NULL;
	}

	if (ttm->pages) {
		drm_buffer_manager_t *bm = &ttm->dev->bm;
		if (ttm->page_flags & DRM_TTM_PAGE_UNCACHED)
			drm_set_caching(ttm, 0);

		for (i = 0; i < ttm->num_pages; ++i) {
			cur_page = ttm->pages + i;
			if (*cur_page) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15))
				unlock_page(*cur_page);
#else
				ClearPageReserved(*cur_page);
#endif
				if (page_count(*cur_page) != 1) {
					DRM_ERROR("Erroneous page count. "
						  "Leaking pages.\n");
				}
				if (page_mapped(*cur_page)) {
					DRM_ERROR("Erroneous map count. "
						  "Leaking page mappings.\n");
				}
				__free_page(*cur_page);
				drm_free_memctl(PAGE_SIZE);
				--bm->cur_pages;
			}
		}
		ttm_free_pages(ttm);
	}

	drm_ctl_free(ttm, sizeof(*ttm), DRM_MEM_TTM);
	return 0;
}

struct page *drm_ttm_get_page(drm_ttm_t * ttm, int index)
{
	struct page *p;
	drm_buffer_manager_t *bm = &ttm->dev->bm;

	p = ttm->pages[index];
	if (!p) {
		p = drm_ttm_alloc_page();
		if (!p)
			return NULL;
		ttm->pages[index] = p;
		++bm->cur_pages;
	}
	return p;
}

static int drm_ttm_populate(drm_ttm_t * ttm)
{
	struct page *page;
	unsigned long i;
	drm_ttm_backend_t *be;

	if (ttm->state != ttm_unpopulated)
		return 0;

	be = ttm->be;
	for (i = 0; i < ttm->num_pages; ++i) {
		page = drm_ttm_get_page(ttm, i);
		if (!page)
			return -ENOMEM;
	}
	be->func->populate(be, ttm->num_pages, ttm->pages);
	ttm->state = ttm_unbound;
	return 0;
}

/*
 * Initialize a ttm.
 */

drm_ttm_t *drm_ttm_init(struct drm_device * dev, unsigned long size)
{
	drm_bo_driver_t *bo_driver = dev->driver->bo_driver;
	drm_ttm_t *ttm;

	if (!bo_driver)
		return NULL;

	ttm = drm_ctl_calloc(1, sizeof(*ttm), DRM_MEM_TTM);
	if (!ttm)
		return NULL;

	ttm->dev = dev;
	atomic_set(&ttm->vma_count, 0);

	ttm->destroy = 0;
	ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;

	ttm->page_flags = 0;

	/*
	 * Account also for AGP module memory usage.
	 */

	ttm_alloc_pages(ttm);
	if (!ttm->pages) {
		drm_destroy_ttm(ttm);
		DRM_ERROR("Failed allocating page table\n");
		return NULL;
	}
	ttm->be = bo_driver->create_ttm_backend_entry(dev);
	if (!ttm->be) {
		drm_destroy_ttm(ttm);
		DRM_ERROR("Failed creating ttm backend entry\n");
		return NULL;
	}
	ttm->state = ttm_unpopulated;
	return ttm;
}

/*
 * Unbind a ttm region from the aperture.
 */

void drm_ttm_evict(drm_ttm_t * ttm)
{
	drm_ttm_backend_t *be = ttm->be;
	int ret;

	if (ttm->state == ttm_bound) {
		ret = be->func->unbind(be);
		BUG_ON(ret);
	}

	ttm->state = ttm_evicted;
}

void drm_ttm_fixup_caching(drm_ttm_t * ttm)
{

	if (ttm->state == ttm_evicted) {
		drm_ttm_backend_t *be = ttm->be;
		if (be->func->needs_ub_cache_adjust(be)) {
			drm_set_caching(ttm, 0);
		}
		ttm->state = ttm_unbound;
	}
}

void drm_ttm_unbind(drm_ttm_t * ttm)
{
	if (ttm->state == ttm_bound)
		drm_ttm_evict(ttm);

	drm_ttm_fixup_caching(ttm);
}

int drm_bind_ttm(drm_ttm_t * ttm, int cached, unsigned long aper_offset)
{

	int ret = 0;
	drm_ttm_backend_t *be;

	if (!ttm)
		return -EINVAL;
	if (ttm->state == ttm_bound)
		return 0;

	be = ttm->be;

	ret = drm_ttm_populate(ttm);
	if (ret)
		return ret;

	if (ttm->state == ttm_unbound && !cached) {
		drm_set_caching(ttm, DRM_TTM_PAGE_UNCACHED);