/* * Copyright (C) 2008 Maarten Maathuis. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include #include #include #include #include #include #include "nv50_fbcon.h" static int nv50_fbcon_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) { struct nv50_fbcon_par *par = info->par; struct drm_device *dev = par->dev; struct drm_framebuffer *drm_fb; list_for_each_entry(drm_fb, &dev->mode_config.fb_kernel_list, filp_head) { if (regno > 255) return 1; /* TODO: 8 bit support */ if (regno < 16) { switch (drm_fb->depth) { case 15: drm_fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); break; case 16: drm_fb->pseudo_palette[regno] = (red & 0xf800) | ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); break; case 24: case 32: drm_fb->pseudo_palette[regno] = ((red & 0xff00) << 8) | (green & 0xff00) | ((blue & 0xff00) >> 8); break; } } } return 0; } static int nv50_fbcon_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { struct nv50_fbcon_par *par = info->par; struct drm_framebuffer *drm_fb = par->fb; int depth; NV50_DEBUG("\n"); if (!var || !drm_fb || !info) { DRM_ERROR("No var, drm_fb or info\n"); } par->use_preferred_mode = false; if (var->pixclock == -1 || !var->pixclock) { DRM_INFO("Using preferred mode.\n"); par->use_preferred_mode = true; } /* Need to resize the fb object !!! */ if (var->xres > drm_fb->width || var->yres > drm_fb->height) { DRM_ERROR("Requested width/height is greater than current fb object %dx%d > %dx%d\n", var->xres,var->yres, drm_fb->width, drm_fb->height); DRM_ERROR("Need resizing code.\n"); return -EINVAL; } switch (var->bits_per_pixel) { case 16: depth = (var->green.length == 6) ? 16 : 15; break; case 32: depth = (var->transp.length > 0) ? 32 : 24; break; default: depth = var->bits_per_pixel; break; } switch (depth) { case 15: var->red.offset = 10; var->green.offset = 5; var->blue.offset = 0; var->red.length = 5; var->green.length = 5; var->blue.length = 5; var->transp.length = 1; var->transp.offset = 15; break; case 16: var->red.offset = 11; var->green.offset = 5; var->blue.offset = 0; var->red.length = 5; var->green.length = 6; var->blue.length = 5; var->transp.length = 0; var->transp.offset = 0; break; case 24: var->red.offset = 16; var->green.offset = 8; var->blue.offset = 0; var->red.length = 8; var->green.length = 8; var->blue.length = 8; var->transp.length = 0; var->transp.offset = 0; break; case 32: var->red.offset = 16; var->green.offset = 8; var->blue.offset = 0; var->red.length = 8; var->green.length = 8; var->blue.length = 8; var->transp.length = 8; var->transp.offset = 24; break; default: DRM_ERROR("Invalid depth %d\n", depth); return -EINVAL; } return 0; } static int nv50_fbcon_set_par(struct fb_info *info) { struct nv50_fbcon_par *par; struct drm_framebuffer *drm_fb; struct drm_connector *drm_connector; struct drm_crtc *drm_crtc; struct fb_var_screeninfo *var; struct drm_display_mode *drm_mode = NULL, *t; struct drm_device *dev; int rval; bool crtc_used[2] = {false, false}; NV50_DEBUG("\n"); if (!info) { DRM_ERROR("No fb_info\n"); return -EINVAL; } par = info->par; if (!par) { DRM_ERROR("No nv50_fbcon_par\n"); return -EINVAL; } drm_fb = par->fb; var = &info->var; dev = par->dev; if (!drm_fb || !var || !dev) { DRM_ERROR("No drm_fb, var or dev\n"); return -EINVAL; } par->use_preferred_mode = false; if (var->pixclock == -1 || !var->pixclock) { DRM_INFO("Using preferred mode.\n"); par->use_preferred_mode = true; } /* FB setup */ switch (var->bits_per_pixel) { case 16: drm_fb->depth = (var->green.length == 6) ? 16 : 15; break; case 32: drm_fb->depth = (var->transp.length > 0) ? 32 : 24; break; default: drm_fb->depth = var->bits_per_pixel; break; } drm_fb->bits_per_pixel = var->bits_per_pixel; info->fix.line_length = drm_fb->pitch; info->fix.smem_len = info->fix.line_length * drm_fb->height; /* ignoring 8bpp for the moment */ info->fix.visual = FB_VISUAL_TRUECOLOR; info->screen_size = info->fix.smem_len; /* ??? */ /* create a drm mode */ if (!par->use_preferred_mode) { drm_mode = drm_mode_create(dev); drm_mode->hdisplay = var->xres; drm_mode->hsync_start = drm_mode->hdisplay + var->right_margin; drm_mode->hsync_end = drm_mode->hsync_start + var->hsync_len; drm_mode->htotal = drm_mode->hsync_end + var->left_margin; drm_mode->vdisplay = var->yres; drm_mode->vsync_start = drm_mode->vdisplay + var->lower_margin; drm_mode->vsync_end = drm_mode->vsync_start + var->vsync_len; drm_mode->vtotal = drm_mode->vsync_end + var->upper_margin; drm_mode->clock = PICOS2KHZ(var->pixclock); drm_mode->vrefresh = drm_mode_vrefresh(drm_mode); drm_mode->flags = 0; drm_mode->flags |= var->sync & FB_SYNC_HOR_HIGH_ACT ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; drm_mode->flags |= var->sync & FB_SYNC_VERT_HIGH_ACT ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; drm_mode_set_name(drm_mode); drm_mode_set_crtcinfo(drm_mode, CRTC_INTERLACE_HALVE_V); } /* hook up crtc's */ list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) { enum drm_connector_status status; struct drm_mode_set mode_set; int crtc_count = 0; status = drm_connector->funcs->detect(drm_connector); if (status != connector_status_connected) continue; memset(&mode_set, 0, sizeof(struct drm_mode_set)); /* set connector */ mode_set.num_connectors = 1; mode_set.connectors = kzalloc(sizeof(struct drm_connector *), GFP_KERNEL); if (!mode_set.connectors) { rval = -ENOMEM; goto out; } mode_set.connectors[0] = drm_connector; /* set fb */ list_for_each_entry(drm_fb, &dev->mode_config.fb_kernel_list, filp_head) { break; /* first entry is the only entry */ } mode_set.fb = drm_fb; /* set mode */ if (par->use_preferred_mode) { /* find preferred mode */ list_for_each_entry_safe(drm_mode, t, &drm_connector->modes, head) { if (drm_mode->type & DRM_MODE_TYPE_PREFERRED) break; } } mode_set.mode = drm_mode; /* choose crtc it already has, if possible */ if (drm_connector->encoder) { struct drm_encoder *drm_encoder = drm_connector->encoder; if (drm_encoder->crtc) { list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { if (drm_crtc == drm_encoder->crtc) { if (!crtc_used[crtc_count]) /* still available? */ mode_set.crtc = drm_crtc; break; } crtc_count++; } } } /* proceed as planned */ if (mode_set.crtc) { mode_set.crtc->funcs->set_config(&mode_set); crtc_used[crtc_count] = true; } if (!mode_set.crtc) { crtc_count = 0; /* reset */ /* choose a "random" crtc */ list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { if (crtc_used[crtc_count]) { crtc_count++; continue; } /* found a crtc */ mode_set.crtc = drm_crtc; break; } /* proceed as planned */ if (mode_set.crtc) { mode_set.crtc->funcs->set_config(&mode_set); crtc_used[crtc_count] = true; } } kfree(mode_set.connectors); } return 0; out: return rval; } static struct fb_ops nv50_fb_ops = { .owner = THIS_MODULE, //.fb_open = nv50_fb_open, //.fb_read = nv50_fb_read, //.fb_write = nv50_fb_write, //.fb_release = nv50_fb_release, //.fb_ioctl = nv50_fb_ioctl, .fb_check_var = nv50_fbcon_check_var, .fb_set_par = nv50_fbcon_set_par, .fb_setcolreg = nv50_fbcon_setcolreg, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, //.fb_pan_display = nv50_fb_pan_display, }; static int nv50_fbcon_initial_config(struct drm_device *dev) { struct drm_connector *drm_connector; struct drm_framebuffer *drm_fb = NULL; struct drm_mode_fb_cmd drm_fb_cmd; enum drm_connector_status status; uint32_t max_width = 0, max_height = 0, pitch = 0; struct mem_block *block; struct drm_file *file_priv; uint32_t flags; int rval = 0; list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) { status = drm_connector->funcs->detect(drm_connector); /* find the framebuffer size */ if (status == connector_status_connected) { struct drm_display_mode *mode, *t; list_for_each_entry_safe(mode, t, &drm_connector->modes, head) { if (mode->type & DRM_MODE_TYPE_PREFERRED) { if (mode->hdisplay > max_width) max_width = mode->hdisplay; if (mode->vdisplay > max_height) max_height = mode->vdisplay; } } } } /* allocate framebuffer */ file_priv = kzalloc(sizeof(struct drm_file), GFP_KERNEL); if (!file_priv) { rval = -ENOMEM; goto out; } pitch = (max_width + 63) & ~63; pitch *= 4; /* TODO */ flags = NOUVEAU_MEM_FB | NOUVEAU_MEM_MAPPED; /* Any file_priv should do as it's pointer is used as identification. */ block = nouveau_mem_alloc(dev, 0, pitch * max_height, flags, file_priv); if (!block) { rval = -ENOMEM; goto out; } memset(&drm_fb_cmd, 0, sizeof(struct drm_mode_fb_cmd)); drm_fb_cmd.width = max_width; drm_fb_cmd.height = max_height; drm_fb_cmd.pitch = pitch; drm_fb_cmd.bpp = 32; /* TODO */ drm_fb_cmd.handle = block->map_handle; drm_fb_cmd.depth = 24; /* TODO */ drm_fb = dev->mode_config.funcs->fb_create(dev, file_priv, &drm_fb_cmd); if (!drm_fb) { rval = -EINVAL; goto out; } list_add(&drm_fb->filp_head, &dev->mode_config.fb_kernel_list); return 0; out: if (file_priv) kfree(file_priv); if (drm_fb) drm_fb->funcs->destroy(drm_fb); return rval; } /* * Single framebuffer, ideally operating in clone mode across various connectors. */ int nv50_fbcon_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct fb_info *info; struct nv50_fbcon_par *par; struct device *device = &dev->pdev->dev; struct drm_framebuffer *drm_fb; struct mem_block *block; void __iomem *fb = NULL; int rval; rval = nv50_fbcon_initial_config(dev); if (rval != 0) { DRM_ERROR("nv50_fbcon_initial_config failed\n"); return rval; } list_for_each_entry(drm_fb, &dev->mode_config.fb_kernel_list, filp_head) { break; /* first entry is the only entry */ } if (!drm_fb) { DRM_ERROR("no drm_fb found\n"); return -EINVAL; } block = find_block_by_handle(dev_priv->fb_heap, drm_fb->mm_handle); if (!block) { DRM_ERROR("can't find mem_block\n"); return -EINVAL; } info = framebuffer_alloc(sizeof(struct nv50_fbcon_par), device); if (!info) { DRM_ERROR("framebuffer_alloc failed\n"); return -EINVAL; } par = info->par; strcpy(info->fix.id, "nv50drmfb"); info->fix.type = FB_TYPE_PACKED_PIXELS; info->fix.visual = FB_VISUAL_TRUECOLOR; info->fix.type_aux = 0; info->fix.xpanstep = 0; /* 1 is doing it in hw */ info->fix.ypanstep = 0; info->fix.ywrapstep = 0; info->fix.accel = FB_ACCEL_NONE; info->fix.type_aux = 0; info->flags = FBINFO_DEFAULT; info->fbops = &nv50_fb_ops; info->fix.line_length = drm_fb->pitch; info->fix.smem_start = dev_priv->fb_phys + block->start; info->fix.smem_len = info->fix.line_length * drm_fb->height; info->flags = FBINFO_DEFAULT; fb = ioremap(dev_priv->fb_phys + block->start, block->size); if (!fb) { DRM_ERROR("Unable to ioremap framebuffer\n"); return -EINVAL; } info->screen_base = fb; info->screen_size = info->fix.smem_len; /* FIXME */ info->pseudo_palette = drm_fb->pseudo_palette; info->var.xres_virtual = drm_fb->width; info->var.yres_virtual = drm_fb->height; info->var.bits_per_pixel = drm_fb->bits_per_pixel; info->var.xoffset = 0; info->var.yoffset = 0; info->var.activate = FB_ACTIVATE_NOW; info->var.height = -1; info->var.width = -1; /* TODO: improve this */ info->var.xres = drm_fb->width; info->var.yres = drm_fb->height; info->fix.mmio_start = drm_get_resource_start(dev, 0); info->fix.mmio_len = drm_get_resource_len(dev, 0); DRM_DEBUG("fb depth is %d\n", drm_fb->depth); DRM_DEBUG(" pitch is %d\n", drm_fb->pitch); switch(drm_fb->depth) { case 15: info->var.red.offset = 10; info->var.green.offset = 5; info->var.blue.offset = 0; info->var.red.length = 5; info->var.green.length = 5; info->var.blue.length = 5; info->var.transp.offset = 15; info->var.transp.length = 1; break; case 16: info->var.red.offset = 11; info->var.green.offset = 5; info->var.blue.offset = 0; info->var.red.length = 5; info->var.green.length = 6; info->var.blue.length = 5; info->var.transp.offset = 0; break; case 24: info->var.red.offset = 16; info->var.green.offset = 8; info->var.blue.offset = 0; info->var.red.length = 8; info->var.green.length = 8; info->var.blue.length = 8; info->var.transp.offset = 0; info->var.transp.length = 0; break; case 32: info->var.red.offset = 16; info->var.green.offset = 8; info->var.blue.offset = 0; info->var.red.length = 8; info->var.green.length = 8; info->var.blue.length = 8; info->var.transp.offset = 24; info->var.transp.length = 8; break; default: break; } drm_fb->fbdev = info; par->dev = dev; par->fb = drm_fb; register_framebuffer(info); DRM_INFO("nv50drmfb initialised\n"); return 0; } int nv50_fbcon_destroy(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_framebuffer *drm_fb; struct fb_info *info; struct mem_block *block; struct drm_file *file_priv; list_for_each_entry(drm_fb, &dev->mode_config.fb_kernel_list, filp_head) { break; /* first entry is the only entry */ } if (!drm_fb) { DRM_ERROR("No framebuffer to destroy\n"); return -EINVAL; } info = drm_fb->fbdev; if (!info) { DRM_ERROR("No fb_info\n"); return -EINVAL; } unregister_framebuffer(info); block = find_block_by_handle(dev_priv->fb_heap, drm_fb->mm_handle); if (!block) { DRM_ERROR("can't find mem_block\n"); return -EINVAL; } /* we need to free this after memory is freed */ file_priv = block->file_priv; /* free memory */ nouveau_mem_free(dev, block); if (file_priv) { kfree(file_priv); file_priv = NULL; } framebuffer_release(info); return 0; } '>381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 
/* mach64_drv.h -- Private header for mach64 driver -*- linux-c -*-
 * Created: Fri Nov 24 22:07:58 2000 by gareth@valinux.com
 *
 * Copyright 2000 Gareth Hughes
 * Copyright 2002 Frank C. Earl
 * Copyright 2002-2003 Leif Delgass
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Gareth Hughes <gareth@valinux.com>
 *    Frank C. Earl <fearl@airmail.net>
 *    Leif Delgass <ldelgass@retinalburn.net>
 *    José Fonseca <j_r_fonseca@yahoo.co.uk>
 */

#ifndef __MACH64_DRV_H__
#define __MACH64_DRV_H__


/* FIXME: remove these when not needed */
/* Development driver options */
#define MACH64_EXTRA_CHECKING     0 /* Extra sanity checks for DMA/freelist management */
#define MACH64_VERBOSE		  0 /* Verbose debugging output */

typedef struct drm_mach64_freelist {
	struct list_head  list;  /* List pointers for free_list, placeholders, or pending list */
   	drm_buf_t *buf;          /* Pointer to the buffer */
	int discard;             /* This flag is set when we're done (re)using a buffer */
	u32 ring_ofs;            /* dword offset in ring of last descriptor for this buffer */
} drm_mach64_freelist_t;

typedef struct drm_mach64_descriptor_ring {
	dma_addr_t handle;       /* handle (bus address) of ring returned by pci_alloc_consistent() */
	void *start;             /* write pointer (cpu address) to start of descriptor ring */
	u32 start_addr;          /* bus address of beginning of descriptor ring */
       	int size;                /* size of ring in bytes */

	u32 head_addr;           /* bus address of descriptor ring head */
	u32 head;                /* dword offset of descriptor ring head */
	u32 tail;                /* dword offset of descriptor ring tail */
	u32 tail_mask;           /* mask used to wrap ring */
	int space;               /* number of free bytes in ring */
} drm_mach64_descriptor_ring_t;

typedef struct drm_mach64_private {
	drm_mach64_sarea_t *sarea_priv;

	int is_pci;
	drm_mach64_dma_mode_t driver_mode;       /* Async DMA, sync DMA, or MMIO */

	int usec_timeout;                        /* Timeout for the wait functions */

	drm_mach64_descriptor_ring_t ring;       /* DMA descriptor table (ring buffer) */
	int ring_running;                        /* Is bus mastering is enabled */

	struct list_head free_list;              /* Free-list head */
	struct list_head placeholders;           /* Placeholder list for buffers held by clients */
	struct list_head pending;                /* Buffers pending completion */

	u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */

	unsigned int fb_bpp;
	unsigned int front_offset, front_pitch;
	unsigned int back_offset, back_pitch;

	unsigned int depth_bpp;
	unsigned int depth_offset, depth_pitch;

	u32 front_offset_pitch;
	u32 back_offset_pitch;
	u32 depth_offset_pitch;

	drm_local_map_t *sarea;
	drm_local_map_t *fb;
	drm_local_map_t *mmio;
	drm_local_map_t *ring_map;
	drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */
	drm_local_map_t *agp_textures;
} drm_mach64_private_t;

				/* mach64_dma.c */
extern int mach64_dma_init( DRM_IOCTL_ARGS );
extern int mach64_dma_idle( DRM_IOCTL_ARGS );
extern int mach64_dma_flush( DRM_IOCTL_ARGS );
extern int mach64_engine_reset( DRM_IOCTL_ARGS );
extern int mach64_dma_buffers( DRM_IOCTL_ARGS );

extern int mach64_init_freelist( drm_device_t *dev );
extern void mach64_destroy_freelist( drm_device_t *dev );
extern drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv );

extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv,
				    int entries );
extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv );
extern int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n );
extern int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv );
extern int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv );
extern void mach64_dump_engine_info( drm_mach64_private_t *dev_priv );
extern void mach64_dump_ring_info( drm_mach64_private_t *dev_priv );
extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv );

extern int mach64_do_dma_idle( drm_mach64_private_t *dev_priv );
extern int mach64_do_dma_flush( drm_mach64_private_t *dev_priv );
extern int mach64_do_cleanup_dma( drm_device_t *dev );

				/* mach64_state.c */
extern int mach64_dma_clear( DRM_IOCTL_ARGS );
extern int mach64_dma_swap( DRM_IOCTL_ARGS );
extern int mach64_dma_vertex( DRM_IOCTL_ARGS );
extern int mach64_dma_blit( DRM_IOCTL_ARGS );
extern int mach64_get_param( DRM_IOCTL_ARGS );
extern int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);

extern irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS );
extern void mach64_driver_irq_preinstall( drm_device_t *dev );
extern void mach64_driver_irq_postinstall( drm_device_t *dev );
extern void mach64_driver_irq_uninstall( drm_device_t *dev );

/* ================================================================
 * Registers
 */

#define MACH64_AGP_BASE				0x0148
#define MACH64_AGP_CNTL				0x014c
#define MACH64_ALPHA_TST_CNTL			0x0550


#define MACH64_DSP_CONFIG 			0x0420
#define MACH64_DSP_ON_OFF 			0x0424
#define MACH64_EXT_MEM_CNTL 			0x04ac
#define MACH64_GEN_TEST_CNTL 			0x04d0
#define MACH64_HW_DEBUG 			0x047c
#define MACH64_MEM_ADDR_CONFIG 			0x0434
#define MACH64_MEM_BUF_CNTL 			0x042c
#define MACH64_MEM_CNTL 			0x04b0


#define MACH64_BM_ADDR				0x0648
#define MACH64_BM_COMMAND			0x0188
#define MACH64_BM_DATA				0x0648
#define MACH64_BM_FRAME_BUF_OFFSET		0x0180
#define MACH64_BM_GUI_TABLE			0x01b8
#define MACH64_BM_GUI_TABLE_CMD			0x064c
#	define MACH64_CIRCULAR_BUF_SIZE_16KB		(0 << 0)
#	define MACH64_CIRCULAR_BUF_SIZE_32KB		(1 << 0)
#	define MACH64_CIRCULAR_BUF_SIZE_64KB		(2 << 0)
#	define MACH64_CIRCULAR_BUF_SIZE_128KB		(3 << 0)
#	define MACH64_LAST_DESCRIPTOR			(1 << 31)
#define MACH64_BM_HOSTDATA			0x0644
#define MACH64_BM_STATUS			0x018c
#define MACH64_BM_SYSTEM_MEM_ADDR		0x0184
#define MACH64_BM_SYSTEM_TABLE			0x01bc
#define MACH64_BUS_CNTL				0x04a0
#	define MACH64_BUS_MSTR_RESET			(1 << 1)
#	define MACH64_BUS_APER_REG_DIS			(1 << 4)
#	define MACH64_BUS_FLUSH_BUF			(1 << 2)
#	define MACH64_BUS_MASTER_DIS			(1 << 6)
#	define MACH64_BUS_EXT_REG_EN			(1 << 27)

#define MACH64_CLR_CMP_CLR			0x0700
#define MACH64_CLR_CMP_CNTL			0x0708
#define MACH64_CLR_CMP_MASK			0x0704
#define MACH64_CONFIG_CHIP_ID 			0x04e0
#define MACH64_CONFIG_CNTL 			0x04dc
#define MACH64_CONFIG_STAT0 			0x04e4
#define MACH64_CONFIG_STAT1 			0x0494
#define MACH64_CONFIG_STAT2 			0x0498
#define MACH64_CONTEXT_LOAD_CNTL		0x072c
#define MACH64_CONTEXT_MASK			0x0720
#define MACH64_COMPOSITE_SHADOW_ID		0x0798
#define MACH64_CRC_SIG 				0x04e8
#define MACH64_CUSTOM_MACRO_CNTL 		0x04d4

#define MACH64_DP_BKGD_CLR			0x06c0
#define MACH64_DP_FOG_CLR			0x06c4
#define MACH64_DP_FGRD_BKGD_CLR			0x06e0
#define MACH64_DP_FRGD_CLR			0x06c4
#define MACH64_DP_FGRD_CLR_MIX			0x06dc

#define MACH64_DP_MIX				0x06d4
#	define BKGD_MIX_NOT_D				(0 << 0)
#	define BKGD_MIX_ZERO				(1 << 0)
#	define BKGD_MIX_ONE				(2 << 0)
#	define MACH64_BKGD_MIX_D			(3 << 0)
#	define BKGD_MIX_NOT_S				(4 << 0)
#	define BKGD_MIX_D_XOR_S				(5 << 0)
#	define BKGD_MIX_NOT_D_XOR_S			(6 << 0)
#	define MACH64_BKGD_MIX_S			(7 << 0)
#	define BKGD_MIX_NOT_D_OR_NOT_S			(8 << 0)
#	define BKGD_MIX_D_OR_NOT_S			(9 << 0)
#	define BKGD_MIX_NOT_D_OR_S			(10 << 0)
#	define BKGD_MIX_D_OR_S				(11 << 0)
#	define BKGD_MIX_D_AND_S				(12 << 0)
#	define BKGD_MIX_NOT_D_AND_S			(13 << 0)
#	define BKGD_MIX_D_AND_NOT_S			(14 << 0)
#	define BKGD_MIX_NOT_D_AND_NOT_S			(15 << 0)
#	define BKGD_MIX_D_PLUS_S_DIV2			(23 << 0)
#	define FRGD_MIX_NOT_D				(0 << 16)
#	define FRGD_MIX_ZERO				(1 << 16)
#	define FRGD_MIX_ONE				(2 << 16)
#	define FRGD_MIX_D				(3 << 16)
#	define FRGD_MIX_NOT_S				(4 << 16)
#	define FRGD_MIX_D_XOR_S				(5 << 16)
#	define FRGD_MIX_NOT_D_XOR_S			(6 << 16)
#	define MACH64_FRGD_MIX_S			(7 << 16)
#	define FRGD_MIX_NOT_D_OR_NOT_S			(8 << 16)
#	define FRGD_MIX_D_OR_NOT_S			(9 << 16)
#	define FRGD_MIX_NOT_D_OR_S			(10 << 16)
#	define FRGD_MIX_D_OR_S				(11 << 16)
#	define FRGD_MIX_D_AND_S				(12 << 16)
#	define FRGD_MIX_NOT_D_AND_S			(13 << 16)
#	define FRGD_MIX_D_AND_NOT_S			(14 << 16)
#	define FRGD_MIX_NOT_D_AND_NOT_S			(15 << 16)
#	define FRGD_MIX_D_PLUS_S_DIV2			(23 << 16)

#define MACH64_DP_PIX_WIDTH			0x06d0
#	define MACH64_HOST_TRIPLE_ENABLE		(1 << 13)
#	define MACH64_BYTE_ORDER_MSB_TO_LSB		(0 << 24)
#	define MACH64_BYTE_ORDER_LSB_TO_MSB		(1 << 24)

#define MACH64_DP_SRC				0x06d8
#	define MACH64_BKGD_SRC_BKGD_CLR			(0 << 0)
#	define MACH64_BKGD_SRC_FRGD_CLR			(1 << 0)
#	define MACH64_BKGD_SRC_HOST			(2 << 0)
#	define MACH64_BKGD_SRC_BLIT			(3 << 0)
#	define MACH64_BKGD_SRC_PATTERN			(4 << 0)
#	define MACH64_BKGD_SRC_3D			(5 << 0)
#	define MACH64_FRGD_SRC_BKGD_CLR			(0 << 8)
#	define MACH64_FRGD_SRC_FRGD_CLR			(1 << 8)
#	define MACH64_FRGD_SRC_HOST			(2 << 8)
#	define MACH64_FRGD_SRC_BLIT			(3 << 8)
#	define MACH64_FRGD_SRC_PATTERN			(4 << 8)
#	define MACH64_FRGD_SRC_3D			(5 << 8)
#	define MACH64_MONO_SRC_ONE			(0 << 16)
#	define MACH64_MONO_SRC_PATTERN			(1 << 16)
#	define MACH64_MONO_SRC_HOST			(2 << 16)
#	define MACH64_MONO_SRC_BLIT			(3 << 16)

#define MACH64_DP_WRITE_MASK			0x06c8

#define MACH64_DST_CNTL				0x0530
#	define MACH64_DST_X_RIGHT_TO_LEFT		(0 << 0)
#	define MACH64_DST_X_LEFT_TO_RIGHT		(1 << 0)
#	define MACH64_DST_Y_BOTTOM_TO_TOP		(0 << 1)
#	define MACH64_DST_Y_TOP_TO_BOTTOM		(1 << 1)
#	define MACH64_DST_X_MAJOR			(0 << 2)
#	define MACH64_DST_Y_MAJOR			(1 << 2)
#	define MACH64_DST_X_TILE			(1 << 3)
#	define MACH64_DST_Y_TILE			(1 << 4)
#	define MACH64_DST_LAST_PEL			(1 << 5)
#	define MACH64_DST_POLYGON_ENABLE		(1 << 6)
#	define MACH64_DST_24_ROTATION_ENABLE		(1 << 7)

#define MACH64_DST_HEIGHT_WIDTH			0x0518
#define MACH64_DST_OFF_PITCH			0x0500
#define MACH64_DST_WIDTH_HEIGHT			0x06ec
#define MACH64_DST_X_Y				0x06e8
#define MACH64_DST_Y_X				0x050c

#define MACH64_FIFO_STAT			0x0710
#	define MACH64_FIFO_SLOT_MASK			0x0000ffff
#	define MACH64_FIFO_ERR				(1 << 31)

#define MACH64_GEN_TEST_CNTL			0x04d0
#	define MACH64_GUI_ENGINE_ENABLE			(1 << 8)
#define MACH64_GUI_CMDFIFO_DEBUG		0x0170
#define MACH64_GUI_CMDFIFO_DATA			0x0174
#define MACH64_GUI_CNTL				0x0178
#       define MACH64_CMDFIFO_SIZE_MASK                 0x00000003ul
#       define MACH64_CMDFIFO_SIZE_192                  0x00000000ul
#       define MACH64_CMDFIFO_SIZE_128                  0x00000001ul
#       define MACH64_CMDFIFO_SIZE_64                   0x00000002ul
#define MACH64_GUI_STAT				0x0738
#	define MACH64_GUI_ACTIVE			(1 << 0)
#define MACH64_GUI_TRAJ_CNTL			0x0730

#define MACH64_HOST_CNTL			0x0640
#define MACH64_HOST_DATA0			0x0600