/* $Id$ * ffb_context.c: Creator/Creator3D DRI/DRM context switching. * * Copyright (C) 2000 David S. Miller (davem@redhat.com) * * Almost entirely stolen from tdfx_context.c, see there * for authors. */ #include #include #include "drmP.h" #include "ffb_drv.h" static int ffb_alloc_queue(drm_device_t * dev, int is_2d_only) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int i; for (i = 0; i < FFB_MAX_CTXS; i++) { if (fpriv->hw_state[i] == NULL) break; } if (i == FFB_MAX_CTXS) return -1; fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL); if (fpriv->hw_state[i] == NULL) return -1; fpriv->hw_state[i]->is_2d_only = is_2d_only; /* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */ return i + 1; } static void ffb_save_context(ffb_dev_priv_t * fpriv, int idx) { ffb_fbcPtr ffb = fpriv->regs; struct ffb_hw_context *ctx; int i; ctx = fpriv->hw_state[idx - 1]; if (idx == 0 || ctx == NULL) return; if (ctx->is_2d_only) { /* 2D applications only care about certain pieces * of state. */ ctx->drawop = upa_readl(&ffb->drawop); ctx->ppc = upa_readl(&ffb->ppc); ctx->wid = upa_readl(&ffb->wid); ctx->fg = upa_readl(&ffb->fg); ctx->bg = upa_readl(&ffb->bg); ctx->xclip = upa_readl(&ffb->xclip); ctx->fbc = upa_readl(&ffb->fbc); ctx->rop = upa_readl(&ffb->rop); ctx->cmp = upa_readl(&ffb->cmp); ctx->matchab = upa_readl(&ffb->matchab); ctx->magnab = upa_readl(&ffb->magnab); ctx->pmask = upa_readl(&ffb->pmask); ctx->xpmask = upa_readl(&ffb->xpmask); ctx->lpat = upa_readl(&ffb->lpat); ctx->fontxy = upa_readl(&ffb->fontxy); ctx->fontw = upa_readl(&ffb->fontw); ctx->fontinc = upa_readl(&ffb->fontinc); /* stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. */ if (fpriv->ffb_type == ffb2_vertical_plus || fpriv->ffb_type == ffb2_horizontal_plus) { ctx->stencil = upa_readl(&ffb->stencil); ctx->stencilctl = upa_readl(&ffb->stencilctl); } for (i = 0; i < 32; i++) ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]); ctx->ucsr = upa_readl(&ffb->ucsr); return; } /* Fetch drawop. */ ctx->drawop = upa_readl(&ffb->drawop); /* If we were saving the vertex registers, this is where * we would do it. We would save 32 32-bit words starting * at ffb->suvtx. */ /* Capture rendering attributes. */ ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ ctx->wid = upa_readl(&ffb->wid); /* Current WID */ ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */ ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */ ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */ ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */ ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */ ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */ ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */ ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ /* Auxiliary Clips. */ ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min); ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max); ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min); ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max); ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min); ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max); ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min); ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max); ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */ /* These registers/features only exist on FFB2 and later chips. */ if (fpriv->ffb_type >= ffb2_prototype) { ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */ ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */ ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */ ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ /* And stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. */ if (fpriv->ffb_type == ffb2_vertical_plus || fpriv->ffb_type == ffb2_horizontal_plus) { ctx->stencil = upa_readl(&ffb->stencil); ctx->stencilctl = upa_readl(&ffb->stencilctl); } } /* Save the 32x32 area pattern. */ for (i = 0; i < 32; i++) ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]); /* Finally, stash away the User Constol/Status Register. */ ctx->ucsr = upa_readl(&ffb->ucsr); } static void ffb_restore_context(ffb_dev_priv_t * fpriv, int old, int idx) { ffb_fbcPtr ffb = fpriv->regs; struct ffb_hw_context *ctx; int i; ctx = fpriv->hw_state[idx - 1]; if (idx == 0 || ctx == NULL) return; if (ctx->is_2d_only) { /* 2D applications only care about certain pieces * of state. */ upa_writel(ctx->drawop, &ffb->drawop); /* If we were restoring the vertex registers, this is where * we would do it. We would restore 32 32-bit words starting * at ffb->suvtx. */ upa_writel(ctx->ppc, &ffb->ppc); upa_writel(ctx->wid, &ffb->wid); upa_writel(ctx->fg, &ffb->fg); upa_writel(ctx->bg, &ffb->bg); upa_writel(ctx->xclip, &ffb->xclip); upa_writel(ctx->fbc, &ffb->fbc); upa_writel(ctx->rop, &ffb->rop); upa_writel(ctx->cmp, &ffb->cmp); upa_writel(ctx->matchab, &ffb->matchab); upa_writel(ctx->magnab, &ffb->magnab); upa_writel(ctx->pmask, &ffb->pmask); upa_writel(ctx->xpmask, &ffb->xpmask); upa_writel(ctx->lpat, &ffb->lpat); upa_writel(ctx->fontxy, &ffb->fontxy); upa_writel(ctx->fontw, &ffb->fontw); upa_writel(ctx->fontinc, &ffb->fontinc); /* stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. */ if (fpriv->ffb_type == ffb2_vertical_plus || fpriv->ffb_type == ffb2_horizontal_plus) { upa_writel(ctx->stencil, &ffb->stencil); upa_writel(ctx->stencilctl, &ffb->stencilctl); upa_writel(0x80000000, &ffb->fbc); upa_writel((ctx->stencilctl | 0x80000), &ffb->rawstencilctl); upa_writel(ctx->fbc, &ffb->fbc); } for (i = 0; i < 32; i++) upa_writel(ctx->area_pattern[i], &ffb->pattern[i]); upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr); return; } /* Restore drawop. */ upa_writel(ctx->drawop, &ffb->drawop); /* If we were restoring the vertex registers, this is where * we would do it. We would restore 32 32-bit words starting * at ffb->suvtx. */ /* Restore rendering attributes. */ upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ upa_writel(ctx->wid, &ffb->wid); /* Current WID */ upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */ upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */ upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */ upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */ upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */ upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */ upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */ upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ /* Auxiliary Clips. */ upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min); upa_writel(ctx->auxclip0max, &ffb->auxclip[0].max); upa_writel(ctx->auxclip1min, &ffb->auxclip[1].min); upa_writel(ctx->auxclip1max, &ffb->auxclip[1].max); upa_writel(ctx->auxclip2min, &ffb->auxclip[2].min); upa_writel(ctx->auxclip2max, &ffb->auxclip[2].max); upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min); upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max); upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */ /* These registers/features only exist on FFB2 and later chips. */ if (fpriv->ffb_type >= ffb2_prototype) { upa_writel(ctx->dcss1, &ffb->dcss1); /* Depth Cue Scale Slope 1 */ upa_writel(ctx->dcss2, &ffb->dcss2); /* Depth Cue Scale Slope 2 */ upa_writel(ctx->dcss3, &ffb->dcss2); /* Depth Cue Scale Slope 3 */ upa_writel(ctx->dcs2, &ffb->dcs2); /* Depth Cue Scale 2 */ upa_writel(ctx->dcs3, &ffb->dcs3); /* Depth Cue Scale 3 */ upa_writel(ctx->dcs4, &ffb->dcs4); /* Depth Cue Scale 4 */ upa_writel(ctx->dcd2, &ffb->dcd2); /* Depth Cue Depth 2 */ upa_writel(ctx->dcd3, &ffb->dcd3); /* Depth Cue Depth 3 */ upa_writel(ctx->dcd4, &ffb->dcd4); /* Depth Cue Depth 4 */ /* And stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. */ if (fpriv->ffb_type == ffb2_vertical_plus || fpriv->ffb_type == ffb2_horizontal_plus) { /* Unfortunately, there is a hardware bug on * the FFB2+ chips which prevents a normal write * to the stencil control register from working * as it should. * * The state controlled by the FFB stencilctl register * really gets transferred to the per-buffer instances * of the stencilctl register in the 3DRAM chips. * * The bug is that FFB does not update buffer C correctly, * so we have to do it by hand for them. */ /* This will update buffers A and B. */ upa_writel(ctx->stencil, &ffb->stencil); upa_writel(ctx->stencilctl, &ffb->stencilctl); /* Force FFB to use buffer C 3dram regs. */ upa_writel(0x80000000, &ffb->fbc); upa_writel((ctx->stencilctl | 0x80000), &ffb->rawstencilctl); /* Now restore the correct FBC controls. */ upa_writel(ctx->fbc, &ffb->fbc); } } /* Restore the 32x32 area pattern. */ for (i = 0; i < 32; i++) upa_writel(ctx->area_pattern[i], &ffb->pattern[i]); /* Finally, stash away the User Constol/Status Register. * The only state we really preserve here is the picking * control. */ upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr); } #define FFB_UCSR_FB_BUSY 0x01000000 #define FFB_UCSR_RP_BUSY 0x02000000 #define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY) static void FFBWait(ffb_fbcPtr ffb) { int limit = 100000; do { u32 regval = upa_readl(&ffb->ucsr); if ((regval & FFB_UCSR_ALL_BUSY) == 0) break; } while (--limit); } int ffb_context_switch(drm_device_t * dev, int old, int new) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; #if DRM_DMA_HISTOGRAM dev->ctx_start = get_cycles(); #endif DRM_DEBUG("Context switch from %d to %d\n", old, new); if (new == dev->last_context || dev->last_context == 0) { dev->last_context = new; return 0; } FFBWait(fpriv->regs); ffb_save_context(fpriv, old); ffb_restore_context(fpriv, old, new); FFBWait(fpriv->regs); dev->last_context = new; return 0; } int ffb_resctx(struct inode * inode, struct file * filp, unsigned int cmd, unsigned long arg) { drm_ctx_res_t res; drm_ctx_t ctx; int i; DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); if (copy_from_user(&res, (drm_ctx_res_t __user *) arg, sizeof(res))) return -EFAULT; if (res.count >= DRM_RESERVED_CONTEXTS) { memset(&ctx, 0, sizeof(ctx)); for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { ctx.handle = i; if (copy_to_user(&res.contexts[i], &i, sizeof(i))) return -EFAULT; } } res.count = DRM_RESERVED_CONTEXTS; if (copy_to_user((drm_ctx_res_t __user *) arg, &res, sizeof(res))) return -EFAULT; return 0; } int ffb_addctx(struct inode * inode, struct file * filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_ctx_t ctx; int idx; if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; idx = ffb_alloc_queue(dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); if (idx < 0) return -ENFILE; DRM_DEBUG("%d\n", ctx.handle); ctx.handle = idx; if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx))) return -EFAULT; return 0; } int ffb_modctx(struct inode * inode, struct file * filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; struct ffb_hw_context *hwctx; drm_ctx_t ctx; int idx; if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; idx = ctx.handle; if (idx <= 0 || idx >= FFB_MAX_CTXS) return -EINVAL; hwctx = fpriv->hw_state[idx - 1]; if (hwctx == NULL) return -EINVAL; if ((ctx.flags & _DRM_CONTEXT_2DONLY) == 0) hwctx->is_2d_only = 0; else hwctx->is_2d_only = 1; return 0; } int ffb_getctx(struct inode * inode, struct file * filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; struct ffb_hw_context *hwctx; drm_ctx_t ctx; int idx; if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; idx = ctx.handle; if (idx <= 0 || idx >= FFB_MAX_CTXS) return -EINVAL; hwctx = fpriv->hw_state[idx - 1]; if (hwctx == NULL) return -EINVAL; if (hwctx->is_2d_only != 0) ctx.flags = _DRM_CONTEXT_2DONLY; else ctx.flags = 0; if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx))) return -EFAULT; return 0; } int ffb_switchctx(struct inode * inode, struct file * filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_ctx_t ctx; if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); return ffb_context_switch(dev, dev->last_context, ctx.handle); } int ffb_newctx(struct inode * inode, struct file * filp, unsigned int cmd, unsigned long arg) { drm_ctx_t ctx; if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); return 0; } int ffb_rmctx(struct inode * inode, struct file * filp, unsigned int cmd, unsigned long arg) { drm_ctx_t ctx; drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int idx; if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); idx = ctx.handle - 1; if (idx < 0 || idx >= FFB_MAX_CTXS) return -EINVAL; if (fpriv->hw_state[idx] != NULL) { kfree(fpriv->hw_state[idx]); fpriv->hw_state[idx] = NULL; } return 0; } static void ffb_driver_reclaim_buffers_locked(drm_device_t * dev) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock); int idx; idx = context - 1; if (fpriv && context != DRM_KERNEL_CONTEXT && fpriv->hw_state[idx] != NULL) { kfree(fpriv->hw_state[idx]); fpriv->hw_state[idx] = NULL; } } static void ffb_driver_lastclose(drm_device_t * dev) { if (dev->dev_private) kfree(dev->dev_private); } static void ffb_driver_unload(drm_device_t * dev) { if (ffb_position != NULL) kfree(ffb_position); } static int ffb_driver_kernel_context_switch_unlock(struct drm_device *dev) { dev->lock.filp = 0; { __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock; unsigned int old, new, prev, ctx; ctx = lock.context; do { old = *plock; new = ctx; prev = cmpxchg(plock, old, new); } while (prev != old); } wake_up_interruptible(&dev->lock.lock_queue); } unsigned long ffb_driver_get_map_ofs(drm_map_t * map) { return (map->offset & 0xffffffff); } unsigned long ffb_driver_get_reg_ofs(drm_device_t * dev) { ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private; if (ffb_priv) return ffb_priv->card_phys_base; return 0; } href='#n472'>472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 
/*
 * Copyright 2008 Advanced Micro Devices, Inc.  
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Author: Stanislaw Skowronek
 */

#include <linux/module.h>
#include <linux/sched.h>

#define ATOM_DEBUG

#include "atom.h"
#include "atom-names.h"
#include "atom-bits.h"

#define ATOM_COND_ABOVE		0
#define ATOM_COND_ABOVEOREQUAL	1
#define ATOM_COND_ALWAYS	2
#define ATOM_COND_BELOW		3
#define ATOM_COND_BELOWOREQUAL	4
#define ATOM_COND_EQUAL		5
#define ATOM_COND_NOTEQUAL	6

#define ATOM_PORT_ATI	0
#define ATOM_PORT_PCI	1
#define ATOM_PORT_SYSIO	2

#define ATOM_UNIT_MICROSEC	0
#define ATOM_UNIT_MILLISEC	1

#define PLL_INDEX	2
#define PLL_DATA	3

typedef struct {
    struct atom_context *ctx;

    uint32_t *ps, *ws;
    int ps_shift;
    uint16_t start;
} atom_exec_context;

int atom_debug = 0;
void atom_execute_table(struct atom_context *ctx, int index, uint32_t *params);

static uint32_t atom_arg_mask[8] = {0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 0xFF000000};
static int atom_arg_shift[8] = {0, 0, 8, 16, 0, 8, 16, 24};
static int atom_dst_to_src[8][4] = {	// translate destination alignment field to the source alignment encoding
    { 0, 0, 0, 0 },
    { 1, 2, 3, 0 },
    { 1, 2, 3, 0 },
    { 1, 2, 3, 0 },
    { 4, 5, 6, 7 },
    { 4, 5, 6, 7 },
    { 4, 5, 6, 7 },
    { 4, 5, 6, 7 },
};
static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };

static int debug_depth = 0;
#ifdef ATOM_DEBUG
static void debug_print_spaces(int n)
{
    while(n--)
	printk("   ");
}
#define DEBUG(...) do if(atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while(0)
#define SDEBUG(...) do if(atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while(0)
#else
#define DEBUG(...) do { } while(0)
#define SDEBUG(...) do { } while(0)
#endif

static uint32_t atom_iio_execute(struct atom_context *ctx, int base, uint32_t index, uint32_t data)
{
    uint32_t temp = 0xCDCDCDCD;
    while(1)
	switch(CU8(base)) {
	case ATOM_IIO_NOP:
	    base++;
	    break;
	case ATOM_IIO_READ:
	    temp = ctx->card->reg_read(ctx->card, CU16(base+1));
	    base+=3;
	    break;
	case ATOM_IIO_WRITE:
	    ctx->card->reg_write(ctx->card, CU16(base+1), temp);
	    base+=3;
	    break;
	case ATOM_IIO_CLEAR:
	    temp &= ~((0xFFFFFFFF >> (32-CU8(base+1))) << CU8(base+2));
	    base+=3;
	    break;
	case ATOM_IIO_SET:
	    temp |= (0xFFFFFFFF >> (32-CU8(base+1))) << CU8(base+2);
	    base+=3;
	    break;
	case ATOM_IIO_MOVE_INDEX:
	    temp &= ~((0xFFFFFFFF >> (32-CU8(base+1))) << CU8(base+2));
	    temp |= ((index >> CU8(base+2)) & (0xFFFFFFFF >> (32-CU8(base+1)))) << CU8(base+3);
	    base+=4;
	    break;
	case ATOM_IIO_MOVE_DATA:
	    temp &= ~((0xFFFFFFFF >> (32-CU8(base+1))) << CU8(base+2));
	    temp |= ((data >> CU8(base+2)) & (0xFFFFFFFF >> (32-CU8(base+1)))) << CU8(base+3);
	    base+=4;
	    break;
	case ATOM_IIO_MOVE_ATTR:
	    temp &= ~((0xFFFFFFFF >> (32-CU8(base+1))) << CU8(base+2));
	    temp |= ((ctx->io_attr >> CU8(base+2)) & (0xFFFFFFFF >> (32-CU8(base+1)))) << CU8(base+3);
	    base+=4;
	    break;
	case ATOM_IIO_END:
	    return temp;
	default:
	    printk(KERN_INFO "Unknown IIO opcode.\n");
	    return 0;
	}
}

static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr, uint32_t *saved, int print)
{
    uint32_t idx, val = 0xCDCDCDCD, align, arg;
    struct atom_context *gctx = ctx->ctx;
    arg = attr & 7;
    align = (attr >> 3) & 7;
    switch(arg) {
    case ATOM_ARG_REG:
	idx = U16(*ptr);
	(*ptr)+=2;
	if(print)
	    DEBUG("REG[0x%04X]", idx);
	idx += gctx->reg_block;
	switch(gctx->io_mode) {
	case ATOM_IO_MM:
	    val = gctx->card->reg_read(gctx->card, idx);
	    break;
	case ATOM_IO_PCI:
	    printk(KERN_INFO "PCI registers are not implemented.\n");
	    return 0;
	case ATOM_IO_SYSIO:
	    printk(KERN_INFO "SYSIO registers are not implemented.\n");
	    return 0;
	default:
	    if(!(gctx->io_mode&0x80)) {
		printk(KERN_INFO "Bad IO mode.\n");
		return 0;
	    }
	    if(!gctx->iio[gctx->io_mode&0x7F]) {
		printk(KERN_INFO "Undefined indirect IO read method %d.\n", gctx->io_mode&0x7F);
		return 0;
	    }
	    val = atom_iio_execute(gctx, gctx->iio[gctx->io_mode&0x7F], idx, 0);
	}
	break;
    case ATOM_ARG_PS:
	idx = U8(*ptr);
	(*ptr)++;
	val = ctx->ps[idx];
	if(print)
	    DEBUG("PS[0x%02X,0x%04X]", idx, val);
	break;
    case ATOM_ARG_WS:
	idx = U8(*ptr);
	(*ptr)++;
	if(print)
	    DEBUG("WS[0x%02X]", idx);
	switch(idx) {
	case ATOM_WS_QUOTIENT:
	    val = gctx->divmul[0];
	    break;
	case ATOM_WS_REMAINDER:
	    val = gctx->divmul[1];
	    break;
	case ATOM_WS_DATAPTR:
	    val = gctx->data_block;
	    break;
	case ATOM_WS_SHIFT:
	    val = gctx->shift;
	    break;
	case ATOM_WS_OR_MASK:
	    val = 1<<gctx->shift;
	    break;
	case ATOM_WS_AND_MASK:
	    val = ~(1<<gctx->shift);
	    break;
	case ATOM_WS_FB_WINDOW:
	    val = gctx->fb_base;
	    break;
	case ATOM_WS_ATTRIBUTES:
	    val = gctx->io_attr;
	    break;
	default:
	    val = ctx->ws[idx];
	}
	break;
    case ATOM_ARG_ID:
	idx = U16(*ptr);
	(*ptr)+=2;
	if(print) {
	    if(gctx->data_block)
		DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
	    else
		DEBUG("ID[0x%04X]", idx);
	}
	val = U32(idx + gctx->data_block);
	break;
    case ATOM_ARG_FB:
	idx = U8(*ptr);
	(*ptr)++;
	if(print)
	    DEBUG("FB[0x%02X]", idx);
	printk(KERN_INFO "FB access is not implemented.\n");
	return 0;
    case ATOM_ARG_IMM:
	switch(align) {
	case ATOM_SRC_DWORD:
	    val = U32(*ptr);
	    (*ptr)+=4;
	    if(print)
		DEBUG("IMM 0x%08X\n", val);
	    return val;
	case ATOM_SRC_WORD0:
	case ATOM_SRC_WORD8:
	case ATOM_SRC_WORD16:
	    val = U16(*ptr);
	    (*ptr)+=2;
	    if(print)
		DEBUG("IMM 0x%04X\n", val);
	    return val;
	case ATOM_SRC_BYTE0:
	case ATOM_SRC_BYTE8:
	case ATOM_SRC_BYTE16:
	case ATOM_SRC_BYTE24:
	    val = U8(*ptr);
	    (*ptr)++;
	    if(print)
		DEBUG("IMM 0x%02X\n", val);
	    return val;
	}
	return 0;
    case ATOM_ARG_PLL:
	idx = U8(*ptr);
	(*ptr)++;
	if(print)
	    DEBUG("PLL[0x%02X]", idx);
	gctx->card->reg_write(gctx->card, PLL_INDEX, idx);
	val = gctx->card->reg_read(gctx->card, PLL_DATA);
	break;
    case ATOM_ARG_MC:
	idx = U8(*ptr);
	(*ptr)++;
	if(print)
	    DEBUG("MC[0x%02X]", idx);
	val = gctx->card->mc_read(gctx->card, idx);
	printk(KERN_INFO "MC registers are not implemented.\n");
	return 0;
    }
    if(saved)
	*saved = val;
    val &= atom_arg_mask[align];
    val >>= atom_arg_shift[align];
    if(print)
	switch(align) {
	case ATOM_SRC_DWORD:
	    DEBUG(".[31:0] -> 0x%08X\n", val);
	    break;
	case ATOM_SRC_WORD0:
	    DEBUG(".[15:0] -> 0x%04X\n", val);
	    break;
	case ATOM_SRC_WORD8:
	    DEBUG(".[23:8] -> 0x%04X\n", val);
	    break;
	case ATOM_SRC_WORD16:
	    DEBUG(".[31:16] -> 0x%04X\n", val);
	    break;
	case ATOM_SRC_BYTE0:
	    DEBUG(".[7:0] -> 0x%02X\n", val);
	    break;
	case ATOM_SRC_BYTE8:
	    DEBUG(".[15:8] -> 0x%02X\n", val);
	    break;
	case ATOM_SRC_BYTE16:
	    DEBUG(".[23:16] -> 0x%02X\n", val);
	    break;
	case ATOM_SRC_BYTE24:
	    DEBUG(".[31:24] -> 0x%02X\n", val);
	    break;
	}
    return val;
}

static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
{
    uint32_t align = (attr >> 3) & 7, arg = attr & 7;
    switch(arg) {
    case ATOM_ARG_REG:
    case ATOM_ARG_ID:
	(*ptr)+=2;
	break;
    case ATOM_ARG_PLL:
    case ATOM_ARG_MC:
    case ATOM_ARG_PS:
    case ATOM_ARG_WS:
    case ATOM_ARG_FB:
	(*ptr)++;
	break;
    case ATOM_ARG_IMM:
	switch(align) {
	case ATOM_SRC_DWORD:
	    (*ptr)+=4;
	    return;
	case ATOM_SRC_WORD0:
	case ATOM_SRC_WORD8:
	case ATOM_SRC_WORD16:
	    (*ptr)+=2;
	    return;
	case ATOM_SRC_BYTE0:
	case ATOM_SRC_BYTE8:
	case ATOM_SRC_BYTE16:
	case ATOM_SRC_BYTE24:
	    (*ptr)++;
	    return;
	}
	return;
    }
}

static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
{
    return atom_get_src_int(ctx, attr, ptr, NULL, 1);
}

static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr, uint32_t *saved, int print)
{
    return atom_get_src_int(ctx, arg|atom_dst_to_src[(attr>>3)&7][(attr>>6)&3]<<3, ptr, saved, print);
}

static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
{
    atom_skip_src_int(ctx, arg|atom_dst_to_src[(attr>>3)&7][(attr>>6)&3]<<3, ptr);
}

static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr, uint32_t val, uint32_t saved)
{
    uint32_t align = atom_dst_to_src[(attr>>3)&7][(attr>>6)&3], old_val = val, idx;
    struct atom_context *gctx = ctx->ctx;
    old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
    val <<= atom_arg_shift[align];
    val &= atom_arg_mask[align];
    saved &= ~atom_arg_mask[align];
    val |= saved;
    switch(arg) {
    case ATOM_ARG_REG:
	idx = U16(*ptr);
	(*ptr)+=2;
	DEBUG("REG[0x%04X]", idx);
	idx += gctx->reg_block;
	switch(gctx->io_mode) {
	case ATOM_IO_MM:
	    if(idx == 0)
		gctx->card->reg_write(gctx->card, idx, val<<2);
	    else
		gctx->card->reg_write(gctx->card, idx, val);
	    break;
	case ATOM_IO_PCI:
	    printk(KERN_INFO "PCI registers are not implemented.\n");
	    return;
	case ATOM_IO_SYSIO:
	    printk(KERN_INFO "SYSIO registers are not implemented.\n");
	    return;
	default:
	    if(!(gctx->io_mode&0x80)) {
		printk(KERN_INFO "Bad IO mode.\n");
		return;
	    }
	    if(!gctx->iio[gctx->io_mode&0xFF]) {
		printk(KERN_INFO "Undefined indirect IO write method %d.\n", gctx->io_mode&0x7F);
		return;
	    }
	    atom_iio_execute(gctx, gctx->iio[gctx->io_mode&0xFF], idx, val);
	}
	break;
    case ATOM_ARG_PS:
	idx = U8(*ptr);
	(*ptr)++;
	DEBUG("PS[0x%02X]", idx);
	ctx->ps[idx] = val;
	break;
    case ATOM_ARG_WS:
	idx = U8(*ptr);
	(*ptr)++;
	DEBUG("WS[0x%02X]", idx);
	switch(idx) {
	case ATOM_WS_QUOTIENT:
	    gctx->divmul[0] = val;
	    break;
	case ATOM_WS_REMAINDER:
	    gctx->divmul[1] = val;
	    break;
	case ATOM_WS_DATAPTR:
	    gctx->data_block = val;
	    break;
	case ATOM_WS_SHIFT:
	    gctx->shift = val;
	    break;
	case ATOM_WS_OR_MASK:
	case ATOM_WS_AND_MASK:
	    break;
	case ATOM_WS_FB_WINDOW:
	    gctx->fb_base = val;
	    break;
	case ATOM_WS_ATTRIBUTES:
	    gctx->io_attr = val;
	    break;
	default:
	    ctx->ws[idx] = val;
	}
	break;
    case ATOM_ARG_FB:
	idx = U8(*ptr);
	(*ptr)++;
	DEBUG("FB[0x%02X]", idx);
	printk(KERN_INFO "FB access is not implemented.\n");
	return;
    case ATOM_ARG_PLL:
	idx = U8(*ptr);
	(*ptr)++;
	DEBUG("PLL[0x%02X]", idx);
	gctx->card->reg_write(gctx->card, PLL_INDEX, idx);
	gctx->card->reg_write(gctx->card, PLL_DATA, val);
	break;
    case ATOM_ARG_MC:
	idx = U8(*ptr);
	(*ptr)++;
	DEBUG("MC[0x%02X]", idx);
	gctx->card->mc_write(gctx->card, idx, val);
	printk(KERN_INFO "MC registers are not implemented.\n");
	return;
    }
    switch(align) {
    case ATOM_SRC_DWORD:
	DEBUG(".[31:0] <- 0x%08X\n", old_val);
	break;
    case ATOM_SRC_WORD0:
	DEBUG(".[15:0] <- 0x%04X\n", old_val);
	break;
    case ATOM_SRC_WORD8:
	DEBUG(".[23:8] <- 0x%04X\n", old_val);
	break;
    case ATOM_SRC_WORD16:
	DEBUG(".[31:16] <- 0x%04X\n", old_val);
	break;
    case ATOM_SRC_BYTE0:
	DEBUG(".[7:0] <- 0x%02X\n", old_val);
	break;
    case ATOM_SRC_BYTE8:
	DEBUG(".[15:8] <- 0x%02X\n", old_val);
	break;
    case ATOM_SRC_BYTE16:
	DEBUG(".[23:16] <- 0x%02X\n", old_val);
	break;
    case ATOM_SRC_BYTE24:
	DEBUG(".[31:24] <- 0x%02X\n", old_val);
	break;
    }
}

static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t attr = U8((*ptr)++);
    uint32_t dst, src, saved;
    int dptr = *ptr;
    SDEBUG("   dst: ");
    dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
    SDEBUG("   src: ");
    src = atom_get_src(ctx, attr, ptr);
    dst += src;
    SDEBUG("   dst: ");
    atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}

static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t attr = U8((*ptr)++);
    uint32_t dst, src, saved;
    int dptr = *ptr;
    SDEBUG("   dst: ");
    dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
    SDEBUG("   src: ");
    src = atom_get_src(ctx, attr, ptr);
    dst &= src;
    SDEBUG("   dst: ");
    atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}

static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
{
    printk("ATOM BIOS beeped!\n");
}

static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
{
    int idx = U8((*ptr)++);
    if(idx < ATOM_TABLE_NAMES_CNT)
	SDEBUG("   table: %d (%s)\n", idx, atom_table_names[idx]);
    else
	SDEBUG("   table: %d\n", idx);
    if(U16(ctx->ctx->cmd_table + 4 + 2*idx))
	atom_execute_table(ctx->ctx, idx, ctx->ps+ctx->ps_shift);
}

static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t attr = U8((*ptr)++);
    uint32_t saved;
    int dptr = *ptr;
    attr &= 0x38;
    attr |= atom_def_dst[attr>>3]<<6;
    atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
    SDEBUG("   dst: ");
    atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
}

static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t attr = U8((*ptr)++);
    uint32_t dst, src;
    SDEBUG("   src1: ");
    dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
    SDEBUG("   src2: ");
    src = atom_get_src(ctx, attr, ptr);
    ctx->ctx->cs_equal = (dst == src);
    ctx->ctx->cs_above = (dst > src);
    SDEBUG("   result: %s %s\n", ctx->ctx->cs_equal?"EQ":"NE", ctx->ctx->cs_above?"GT":"LE");
}

static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t count = U8((*ptr)++);
    SDEBUG("   count: %d\n", count);
    if(arg == ATOM_UNIT_MICROSEC)
	schedule_timeout_uninterruptible(usecs_to_jiffies(count));
    else
	schedule_timeout_uninterruptible(msecs_to_jiffies(count));
}

static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t attr = U8((*ptr)++);
    uint32_t dst, src;
    SDEBUG("   src1: ");
    dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
    SDEBUG("   src2: ");
    src = atom_get_src(ctx, attr, ptr);
    if(src != 0) {
	ctx->ctx->divmul[0] = dst/src;
	ctx->ctx->divmul[1] = dst%src;
    } else {
	ctx->ctx->divmul[0] = 0;
	ctx->ctx->divmul[1] = 0;
    }
}

static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
{
    /* functionally, a nop */
}

static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
{
    int execute = 0, target = U16(*ptr);
    (*ptr)+=2;
    switch(arg) {
    case ATOM_COND_ABOVE:
	execute = ctx->ctx->cs_above;
	break;
    case ATOM_COND_ABOVEOREQUAL:
	execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
	break;
    case ATOM_COND_ALWAYS:
	execute = 1;
	break;
    case ATOM_COND_BELOW:
	execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
	break;
    case ATOM_COND_BELOWOREQUAL:
	execute = !ctx->ctx->cs_above;
	break;
    case ATOM_COND_EQUAL:
	execute = ctx->ctx->cs_equal;
	break;
    case ATOM_COND_NOTEQUAL:
	execute = !ctx->ctx->cs_equal;
	break;
    }
    if(arg != ATOM_COND_ALWAYS)
	SDEBUG("   taken: %s\n", execute?"yes":"no");
    SDEBUG("   target: 0x%04X\n", target);
    if(execute)
	*ptr = ctx->start+target;
}

static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t attr = U8((*ptr)++);
    uint32_t dst, src1, src2, saved;
    int dptr = *ptr;
    SDEBUG("   dst: ");
    dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
    SDEBUG("   src1: ");
    src1 = atom_get_src(ctx, attr, ptr);
    SDEBUG("   src2: ");
    src2 = atom_get_src(ctx, attr, ptr);
    dst &= src1;
    dst |= src2;
    SDEBUG("   dst: ");
    atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
}

static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t attr = U8((*ptr)++);
    uint32_t src, saved;
    int dptr = *ptr;
    if(((attr>>3)&7) != ATOM_SRC_DWORD)
	atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
    else {
	atom_skip_dst(ctx, arg, attr, ptr);
	saved = 0xCDCDCDCD;
    }
    SDEBUG("   src: ");
    src = atom_get_src(ctx, attr, ptr);
    SDEBUG("   dst: ");
    atom_put_dst(ctx, arg, attr, &dptr, src, saved);
}

static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
{
    uint8_t attr = U8((*ptr)++);
    uint32_t dst, src;
    SDEBUG("   src1: ");
    dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
    SDEBUG("   src2: ");
    src = atom_get_src(ctx, attr, ptr);
    ctx->ctx->divmul[0] = dst*src;
}