/************************************************************************** Copyright © 2006 Dave Airlie All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sub license, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **************************************************************************/ #include "dvo.h" #define CH7xxx_REG_VID 0x4a #define CH7xxx_REG_DID 0x4b #define CH7011_VID 0x83 /* 7010 as well */ #define CH7009A_VID 0x84 #define CH7009B_VID 0x85 #define CH7301_VID 0x95 #define CH7xxx_VID 0x84 #define CH7xxx_DID 0x17 #define CH7xxx_NUM_REGS 0x4c #define CH7xxx_CM 0x1c #define CH7xxx_CM_XCM (1<<0) #define CH7xxx_CM_MCP (1<<2) #define CH7xxx_INPUT_CLOCK 0x1d #define CH7xxx_GPIO 0x1e #define CH7xxx_GPIO_HPIR (1<<3) #define CH7xxx_IDF 0x1f #define CH7xxx_IDF_HSP (1<<3) #define CH7xxx_IDF_VSP (1<<4) #define CH7xxx_CONNECTION_DETECT 0x20 #define CH7xxx_CDET_DVI (1<<5) #define CH7301_DAC_CNTL 0x21 #define CH7301_HOTPLUG 0x23 #define CH7xxx_TCTL 0x31 #define CH7xxx_TVCO 0x32 #define CH7xxx_TPCP 0x33 #define CH7xxx_TPD 0x34 #define CH7xxx_TPVT 0x35 #define CH7xxx_TLPF 0x36 #define CH7xxx_TCT 0x37 #define CH7301_TEST_PATTERN 0x48 #define CH7xxx_PM 0x49 #define CH7xxx_PM_FPD (1<<0) #define CH7301_PM_DACPD0 (1<<1) #define CH7301_PM_DACPD1 (1<<2) #define CH7301_PM_DACPD2 (1<<3) #define CH7xxx_PM_DVIL (1<<6) #define CH7xxx_PM_DVIP (1<<7) #define CH7301_SYNC_POLARITY 0x56 #define CH7301_SYNC_RGB_YUV (1<<0) #define CH7301_SYNC_POL_DVI (1<<5) /** @file * driver for the Chrontel 7xxx DVI chip over DVO. */ static struct ch7xxx_id_struct { uint8_t vid; char *name; } ch7xxx_ids[] = { { CH7011_VID, "CH7011" }, { CH7009A_VID, "CH7009A" }, { CH7009B_VID, "CH7009B" }, { CH7301_VID, "CH7301" }, }; struct ch7xxx_reg_state { uint8_t regs[CH7xxx_NUM_REGS]; }; struct ch7xxx_priv { bool quiet; struct ch7xxx_reg_state save_reg; struct ch7xxx_reg_state mode_reg; uint8_t save_TCTL, save_TPCP, save_TPD, save_TPVT; uint8_t save_TLPF, save_TCT, save_PM, save_IDF; }; static void ch7xxx_save(struct intel_dvo_device *dvo); static char *ch7xxx_get_id(uint8_t vid) { int i; for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) { if (ch7xxx_ids[i].vid == vid) return ch7xxx_ids[i].name; } return NULL; } /** Reads an 8 bit register */ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) { struct ch7xxx_priv *ch7xxx= dvo->dev_priv; struct intel_i2c_chan *i2cbus = dvo->i2c_bus; u8 out_buf[2]; u8 in_buf[2]; struct i2c_msg msgs[] = { { .addr = i2cbus->slave_addr, .flags = 0, .len = 1, .buf = out_buf, }, { .addr = i2cbus->slave_addr, .flags = I2C_M_RD, .len = 1, .buf = in_buf, } }; out_buf[0] = addr; out_buf[1] = 0; if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) { *ch = in_buf[0]; return true; }; if (!ch7xxx->quiet) { DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", addr, i2cbus->adapter.name, i2cbus->slave_addr); } return false; } /** Writes an 8 bit register */ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) { struct ch7xxx_priv *ch7xxx = dvo->dev_priv; struct intel_i2c_chan *i2cbus = dvo->i2c_bus; uint8_t out_buf[2]; struct i2c_msg msg = { .addr = i2cbus->slave_addr, .flags = 0, .len = 2, .buf = out_buf, }; out_buf[0] = addr; out_buf[1] = ch; if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1) return true; if (!ch7xxx->quiet) { DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", addr, i2cbus->adapter.name, i2cbus->slave_addr); } return false; } static bool ch7xxx_init(struct intel_dvo_device *dvo, struct intel_i2c_chan *i2cbus) { /* this will detect the CH7xxx chip on the specified i2c bus */ struct ch7xxx_priv *ch7xxx; uint8_t vendor, device; char *name; ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL); if (ch7xxx == NULL) return false; dvo->i2c_bus = i2cbus; dvo->i2c_bus->slave_addr = dvo->slave_addr; dvo->dev_priv = ch7xxx; ch7xxx->quiet = true; if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor)) goto out; name = ch7xxx_get_id(vendor); if (!name) { DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n", vendor, i2cbus->adapter.name, i2cbus->slave_addr); goto out; } if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device)) goto out; if (device != CH7xxx_DID) { DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n", vendor, i2cbus->adapter.name, i2cbus->slave_addr); goto out; } ch7xxx->quiet = FALSE; DRM_DEBUG("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", name, vendor, device); return true; out: kfree(ch7xxx); return false; } static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo) { uint8_t cdet, orig_pm, pm; ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm); pm = orig_pm; pm &= ~CH7xxx_PM_FPD; pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP; ch7xxx_writeb(dvo, CH7xxx_PM, pm); ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet); ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm); if (cdet & CH7xxx_CDET_DVI) return connector_status_connected; return connector_status_disconnected; } static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo, struct drm_display_mode *mode) { if (mode->clock > 165000) return MODE_CLOCK_HIGH; return MODE_OK; } static void ch7xxx_mode_set(struct intel_dvo_device *dvo, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { uint8_t tvco, tpcp, tpd, tlpf, idf; if (mode->clock <= 65000) { tvco = 0x23; tpcp = 0x08; tpd = 0x16; tlpf = 0x60; } else { tvco = 0x2d; tpcp = 0x06; tpd = 0x26; tlpf = 0xa0; } ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00); ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco); ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp); ch7xxx_writeb(dvo, CH7xxx_TPD, tpd); ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30); ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf); ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00); ch7xxx_readb(dvo, CH7xxx_IDF, &idf); idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); if (mode->flags & V_PHSYNC) idf |= CH7xxx_IDF_HSP; if (mode->flags & V_PVSYNC) idf |= CH7xxx_IDF_HSP; ch7xxx_writeb(dvo, CH7xxx_IDF, idf); } /* set the CH7xxx power state */ static void ch7xxx_dpms(struct intel_dvo_device *dvo, int mode) { if (mode == DPMSModeOn) ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP); else ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD); } static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) { struct ch7xxx_priv *ch7xxx = dvo->dev_priv; int i; for (i = 0; i < CH7xxx_NUM_REGS; i++) { if ((i % 8) == 0 ) DRM_DEBUG("\n %02X: ", i); DRM_DEBUG("%02X ", ch7xxx->mode_reg.regs[i]); } } static void ch7xxx_save(struct intel_dvo_device *dvo) { struct ch7xxx_priv *ch7xxx= dvo->dev_priv; ch7xxx_readb(dvo, CH7xxx_TCTL, &ch7xxx->save_TCTL); ch7xxx_readb(dvo, CH7xxx_TPCP, &ch7xxx->save_TPCP); ch7xxx_readb(dvo, CH7xxx_TPD, &ch7xxx->save_TPD); ch7xxx_readb(dvo, CH7xxx_TPVT, &ch7xxx->save_TPVT); ch7xxx_readb(dvo, CH7xxx_TLPF, &ch7xxx->save_TLPF); ch7xxx_readb(dvo, CH7xxx_PM, &ch7xxx->save_PM); ch7xxx_readb(dvo, CH7xxx_IDF, &ch7xxx->save_IDF); } static void ch7xxx_restore(struct intel_dvo_device *dvo) { struct ch7xxx_priv *ch7xxx = dvo->dev_priv; ch7xxx_writeb(dvo, CH7xxx_TCTL, ch7xxx->save_TCTL); ch7xxx_writeb(dvo, CH7xxx_TPCP, ch7xxx->save_TPCP); ch7xxx_writeb(dvo, CH7xxx_TPD, ch7xxx->save_TPD); ch7xxx_writeb(dvo, CH7xxx_TPVT, ch7xxx->save_TPVT); ch7xxx_writeb(dvo, CH7xxx_TLPF, ch7xxx->save_TLPF); ch7xxx_writeb(dvo, CH7xxx_IDF, ch7xxx->save_IDF); ch7xxx_writeb(dvo, CH7xxx_PM, ch7xxx->save_PM); } static void ch7xxx_destroy(struct intel_dvo_device *dvo) { struct ch7xxx_priv *ch7xxx = dvo->dev_priv; if (ch7xxx) { kfree(ch7xxx); dvo->dev_priv = NULL; } } struct intel_dvo_dev_ops ch7xxx_ops = { .init = ch7xxx_init, .detect = ch7xxx_detect, .mode_valid = ch7xxx_mode_valid, .mode_set = ch7xxx_mode_set, .dpms = ch7xxx_dpms, .dump_regs = ch7xxx_dump_regs, .save = ch7xxx_save, .restore = ch7xxx_restore, .destroy = ch7xxx_destroy, }; '#n189'>189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 
/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Kevin E. Martin <martin@valinux.com>
 *    Gareth Hughes <gareth@valinux.com>
 */

#ifndef __RADEON_DRV_H__
#define __RADEON_DRV_H__

enum radeon_family {
	CHIP_R100,
	CHIP_RS100,
	CHIP_RV100,
	CHIP_R200,
	CHIP_RV200,
	CHIP_RS200,
	CHIP_R250,
	CHIP_RS250,
	CHIP_RV250,
	CHIP_RV280,
	CHIP_R300,
	CHIP_RS300,
	CHIP_LAST,
};

enum radeon_cp_microcode_version {
	UCODE_R100,
	UCODE_R200,
	UCODE_R300,
};

#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
#include "radeon_i2c.h"
#endif

/*
 * Chip flags
 */
enum radeon_chip_flags {
	CHIP_FAMILY_MASK	= 0x0000ffffUL,
	CHIP_FLAGS_MASK		= 0xffff0000UL,
	CHIP_IS_MOBILITY	= 0x00010000UL,
	CHIP_IS_IGP		= 0x00020000UL,
	CHIP_SINGLE_CRTC	= 0x00040000UL,
	CHIP_IS_AGP		= 0x00080000UL, 
};

#define GET_RING_HEAD(dev_priv)		DRM_READ32(  (dev_priv)->ring_rptr, 0 )
#define SET_RING_HEAD(dev_priv,val)	DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )

typedef struct drm_radeon_freelist {
   	unsigned int age;
   	drm_buf_t *buf;
   	struct drm_radeon_freelist *next;
   	struct drm_radeon_freelist *prev;
} drm_radeon_freelist_t;

typedef struct drm_radeon_ring_buffer {
	u32 *start;
	u32 *end;
	int size;
	int size_l2qw;

	u32 tail;
	u32 tail_mask;
	int space;

	int high_mark;
} drm_radeon_ring_buffer_t;

typedef struct drm_radeon_depth_clear_t {
	u32 rb3d_cntl;
	u32 rb3d_zstencilcntl;
	u32 se_cntl;
} drm_radeon_depth_clear_t;

struct drm_radeon_driver_file_fields {
	int64_t radeon_fb_delta;
};

struct mem_block {
	struct mem_block *next;
	struct mem_block *prev;
	int start;
	int size;
	DRMFILE filp;		/* 0: free, -1: heap, other: real files */
};

typedef struct drm_radeon_private {

	drm_radeon_ring_buffer_t ring;
	drm_radeon_sarea_t *sarea_priv;

	u32 fb_location;

	int gart_size;
	u32 gart_vm_start;
	unsigned long gart_buffers_offset;

	int cp_mode;
	int cp_running;

   	drm_radeon_freelist_t *head;
   	drm_radeon_freelist_t *tail;
	int last_buf;
	volatile u32 *scratch;
	int writeback_works;

	int usec_timeout;

	int microcode_version;

	unsigned long phys_pci_gart;
	dma_addr_t bus_pci_gart;

	struct {
		u32 boxes;
		int freelist_timeouts;
		int freelist_loops;
		int requested_bufs;
		int last_frame_reads;
		int last_clear_reads;
		int clears;
		int texture_uploads;
	} stats;

	int do_boxes;
	int page_flipping;
	int current_page;

	u32 color_fmt;
	unsigned int front_offset;
	unsigned int front_pitch;
	unsigned int back_offset;
	unsigned int back_pitch;

	u32 depth_fmt;
	unsigned int depth_offset;
	unsigned int depth_pitch;

	u32 front_pitch_offset;
	u32 back_pitch_offset;
	u32 depth_pitch_offset;

	drm_radeon_depth_clear_t depth_clear;
	
	unsigned long fb_offset;
	unsigned long mmio_offset;
	unsigned long ring_offset;
	unsigned long ring_rptr_offset;
	unsigned long buffers_offset;
	unsigned long gart_textures_offset;

	drm_local_map_t *sarea;
	drm_local_map_t *mmio;
	drm_local_map_t *cp_ring;
	drm_local_map_t *ring_rptr;
	drm_local_map_t *gart_textures;

	struct mem_block *gart_heap;
	struct mem_block *fb_heap;

	/* SW interrupt */
   	wait_queue_head_t swi_queue;
   	atomic_t swi_emitted;

	/* starting from here on, data is preserved accross an open */
	uint32_t flags;		/* see radeon_chip_flags */
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)